Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / mmp2.dtsi
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (C) 2012 Marvell Technology Group Ltd.
4  *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
5  */
6
7 #include <dt-bindings/clock/marvell,mmp2.h>
8
9 / {
10         #address-cells = <1>;
11         #size-cells = <1>;
12
13         aliases {
14                 serial0 = &uart1;
15                 serial1 = &uart2;
16                 serial2 = &uart3;
17                 serial3 = &uart4;
18                 i2c0 = &twsi1;
19                 i2c1 = &twsi2;
20         };
21
22         soc {
23                 #address-cells = <1>;
24                 #size-cells = <1>;
25                 compatible = "simple-bus";
26                 interrupt-parent = <&intc>;
27                 ranges;
28
29                 L2: l2-cache {
30                         compatible = "marvell,tauros2-cache";
31                         marvell,tauros2-cache-features = <0x3>;
32                 };
33
34                 axi@d4200000 {  /* AXI */
35                         compatible = "mrvl,axi-bus", "simple-bus";
36                         #address-cells = <1>;
37                         #size-cells = <1>;
38                         reg = <0xd4200000 0x00200000>;
39                         ranges;
40
41                         intc: interrupt-controller@d4282000 {
42                                 compatible = "mrvl,mmp2-intc";
43                                 interrupt-controller;
44                                 #interrupt-cells = <1>;
45                                 reg = <0xd4282000 0x1000>;
46                                 mrvl,intc-nr-irqs = <64>;
47                         };
48
49                         intcmux4: interrupt-controller@d4282150 {
50                                 compatible = "mrvl,mmp2-mux-intc";
51                                 interrupts = <4>;
52                                 interrupt-controller;
53                                 #interrupt-cells = <1>;
54                                 reg = <0x150 0x4>, <0x168 0x4>;
55                                 reg-names = "mux status", "mux mask";
56                                 mrvl,intc-nr-irqs = <2>;
57                         };
58
59                         intcmux5: interrupt-controller@d4282154 {
60                                 compatible = "mrvl,mmp2-mux-intc";
61                                 interrupts = <5>;
62                                 interrupt-controller;
63                                 #interrupt-cells = <1>;
64                                 reg = <0x154 0x4>, <0x16c 0x4>;
65                                 reg-names = "mux status", "mux mask";
66                                 mrvl,intc-nr-irqs = <2>;
67                                 mrvl,clr-mfp-irq = <1>;
68                         };
69
70                         intcmux9: interrupt-controller@d4282180 {
71                                 compatible = "mrvl,mmp2-mux-intc";
72                                 interrupts = <9>;
73                                 interrupt-controller;
74                                 #interrupt-cells = <1>;
75                                 reg = <0x180 0x4>, <0x17c 0x4>;
76                                 reg-names = "mux status", "mux mask";
77                                 mrvl,intc-nr-irqs = <3>;
78                         };
79
80                         intcmux17: interrupt-controller@d4282158 {
81                                 compatible = "mrvl,mmp2-mux-intc";
82                                 interrupts = <17>;
83                                 interrupt-controller;
84                                 #interrupt-cells = <1>;
85                                 reg = <0x158 0x4>, <0x170 0x4>;
86                                 reg-names = "mux status", "mux mask";
87                                 mrvl,intc-nr-irqs = <5>;
88                         };
89
90                         intcmux35: interrupt-controller@d428215c {
91                                 compatible = "mrvl,mmp2-mux-intc";
92                                 interrupts = <35>;
93                                 interrupt-controller;
94                                 #interrupt-cells = <1>;
95                                 reg = <0x15c 0x4>, <0x174 0x4>;
96                                 reg-names = "mux status", "mux mask";
97                                 mrvl,intc-nr-irqs = <15>;
98                         };
99
100                         intcmux51: interrupt-controller@d4282160 {
101                                 compatible = "mrvl,mmp2-mux-intc";
102                                 interrupts = <51>;
103                                 interrupt-controller;
104                                 #interrupt-cells = <1>;
105                                 reg = <0x160 0x4>, <0x178 0x4>;
106                                 reg-names = "mux status", "mux mask";
107                                 mrvl,intc-nr-irqs = <2>;
108                         };
109
110                         intcmux55: interrupt-controller@d4282188 {
111                                 compatible = "mrvl,mmp2-mux-intc";
112                                 interrupts = <55>;
113                                 interrupt-controller;
114                                 #interrupt-cells = <1>;
115                                 reg = <0x188 0x4>, <0x184 0x4>;
116                                 reg-names = "mux status", "mux mask";
117                                 mrvl,intc-nr-irqs = <2>;
118                         };
119
120                         usb_phy0: usb-phy@d4207000 {
121                                 compatible = "marvell,mmp2-usb-phy";
122                                 reg = <0xd4207000 0x40>;
123                                 #phy-cells = <0>;
124                                 status = "disabled";
125                         };
126
127                         usb_otg0: usb-otg@d4208000 {
128                                 compatible = "marvell,pxau2o-ehci";
129                                 reg = <0xd4208000 0x200>;
130                                 interrupts = <44>;
131                                 clocks = <&soc_clocks MMP2_CLK_USB>;
132                                 clock-names = "USBCLK";
133                                 phys = <&usb_phy0>;
134                                 phy-names = "usb";
135                                 status = "disabled";
136                         };
137
138                         mmc1: mmc@d4280000 {
139                                 compatible = "mrvl,pxav3-mmc";
140                                 reg = <0xd4280000 0x120>;
141                                 clocks = <&soc_clocks MMP2_CLK_SDH0>;
142                                 clock-names = "io";
143                                 interrupts = <39>;
144                                 status = "disabled";
145                         };
146
147                         mmc2: mmc@d4280800 {
148                                 compatible = "mrvl,pxav3-mmc";
149                                 reg = <0xd4280800 0x120>;
150                                 clocks = <&soc_clocks MMP2_CLK_SDH1>;
151                                 clock-names = "io";
152                                 interrupts = <52>;
153                                 status = "disabled";
154                         };
155
156                         mmc3: mmc@d4281000 {
157                                 compatible = "mrvl,pxav3-mmc";
158                                 reg = <0xd4281000 0x120>;
159                                 clocks = <&soc_clocks MMP2_CLK_SDH2>;
160                                 clock-names = "io";
161                                 interrupts = <53>;
162                                 status = "disabled";
163                         };
164
165                         mmc4: mmc@d4281800 {
166                                 compatible = "mrvl,pxav3-mmc";
167                                 reg = <0xd4281800 0x120>;
168                                 clocks = <&soc_clocks MMP2_CLK_SDH3>;
169                                 clock-names = "io";
170                                 interrupts = <54>;
171                                 status = "disabled";
172                         };
173
174                         camera0: camera@d420a000 {
175                                 compatible = "marvell,mmp2-ccic";
176                                 reg = <0xd420a000 0x800>;
177                                 interrupts = <42>;
178                                 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
179                                 clock-names = "axi";
180                                 #clock-cells = <0>;
181                                 clock-output-names = "mclk";
182                                 status = "disabled";
183                         };
184
185                         camera1: camera@d420a800 {
186                                 compatible = "marvell,mmp2-ccic";
187                                 reg = <0xd420a800 0x800>;
188                                 interrupts = <30>;
189                                 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
190                                 clock-names = "axi";
191                                 #clock-cells = <0>;
192                                 clock-output-names = "mclk";
193                                 status = "disabled";
194                         };
195                 };
196
197                 apb@d4000000 {  /* APB */
198                         compatible = "mrvl,apb-bus", "simple-bus";
199                         #address-cells = <1>;
200                         #size-cells = <1>;
201                         reg = <0xd4000000 0x00200000>;
202                         ranges;
203
204                         timer0: timer@d4014000 {
205                                 compatible = "mrvl,mmp-timer";
206                                 reg = <0xd4014000 0x100>;
207                                 interrupts = <13>;
208                                 clocks = <&soc_clocks MMP2_CLK_TIMER>;
209                         };
210
211                         uart1: uart@d4030000 {
212                                 compatible = "mrvl,mmp-uart";
213                                 reg = <0xd4030000 0x1000>;
214                                 interrupts = <27>;
215                                 clocks = <&soc_clocks MMP2_CLK_UART0>;
216                                 resets = <&soc_clocks MMP2_CLK_UART0>;
217                                 reg-shift = <2>;
218                                 status = "disabled";
219                         };
220
221                         uart2: uart@d4017000 {
222                                 compatible = "mrvl,mmp-uart";
223                                 reg = <0xd4017000 0x1000>;
224                                 interrupts = <28>;
225                                 clocks = <&soc_clocks MMP2_CLK_UART1>;
226                                 resets = <&soc_clocks MMP2_CLK_UART1>;
227                                 reg-shift = <2>;
228                                 status = "disabled";
229                         };
230
231                         uart3: uart@d4018000 {
232                                 compatible = "mrvl,mmp-uart";
233                                 reg = <0xd4018000 0x1000>;
234                                 interrupts = <24>;
235                                 clocks = <&soc_clocks MMP2_CLK_UART2>;
236                                 resets = <&soc_clocks MMP2_CLK_UART2>;
237                                 reg-shift = <2>;
238                                 status = "disabled";
239                         };
240
241                         uart4: uart@d4016000 {
242                                 compatible = "mrvl,mmp-uart";
243                                 reg = <0xd4016000 0x1000>;
244                                 interrupts = <46>;
245                                 clocks = <&soc_clocks MMP2_CLK_UART3>;
246                                 resets = <&soc_clocks MMP2_CLK_UART3>;
247                                 reg-shift = <2>;
248                                 status = "disabled";
249                         };
250
251                         gpio: gpio@d4019000 {
252                                 compatible = "marvell,mmp2-gpio";
253                                 #address-cells = <1>;
254                                 #size-cells = <1>;
255                                 reg = <0xd4019000 0x1000>;
256                                 gpio-controller;
257                                 #gpio-cells = <2>;
258                                 interrupts = <49>;
259                                 interrupt-names = "gpio_mux";
260                                 clocks = <&soc_clocks MMP2_CLK_GPIO>;
261                                 resets = <&soc_clocks MMP2_CLK_GPIO>;
262                                 interrupt-controller;
263                                 #interrupt-cells = <2>;
264                                 ranges;
265
266                                 gcb0: gpio@d4019000 {
267                                         reg = <0xd4019000 0x4>;
268                                 };
269
270                                 gcb1: gpio@d4019004 {
271                                         reg = <0xd4019004 0x4>;
272                                 };
273
274                                 gcb2: gpio@d4019008 {
275                                         reg = <0xd4019008 0x4>;
276                                 };
277
278                                 gcb3: gpio@d4019100 {
279                                         reg = <0xd4019100 0x4>;
280                                 };
281
282                                 gcb4: gpio@d4019104 {
283                                         reg = <0xd4019104 0x4>;
284                                 };
285
286                                 gcb5: gpio@d4019108 {
287                                         reg = <0xd4019108 0x4>;
288                                 };
289                         };
290
291                         twsi1: i2c@d4011000 {
292                                 compatible = "mrvl,mmp-twsi";
293                                 reg = <0xd4011000 0x1000>;
294                                 interrupts = <7>;
295                                 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
296                                 resets = <&soc_clocks MMP2_CLK_TWSI0>;
297                                 #address-cells = <1>;
298                                 #size-cells = <0>;
299                                 mrvl,i2c-fast-mode;
300                                 status = "disabled";
301                         };
302
303                         twsi2: i2c@d4031000 {
304                                 compatible = "mrvl,mmp-twsi";
305                                 reg = <0xd4031000 0x1000>;
306                                 interrupt-parent = <&intcmux17>;
307                                 interrupts = <0>;
308                                 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
309                                 resets = <&soc_clocks MMP2_CLK_TWSI1>;
310                                 #address-cells = <1>;
311                                 #size-cells = <0>;
312                                 status = "disabled";
313                         };
314
315                         twsi3: i2c@d4032000 {
316                                 compatible = "mrvl,mmp-twsi";
317                                 reg = <0xd4032000 0x1000>;
318                                 interrupt-parent = <&intcmux17>;
319                                 interrupts = <1>;
320                                 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
321                                 resets = <&soc_clocks MMP2_CLK_TWSI2>;
322                                 #address-cells = <1>;
323                                 #size-cells = <0>;
324                                 status = "disabled";
325                         };
326
327                         twsi4: i2c@d4033000 {
328                                 compatible = "mrvl,mmp-twsi";
329                                 reg = <0xd4033000 0x1000>;
330                                 interrupt-parent = <&intcmux17>;
331                                 interrupts = <2>;
332                                 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
333                                 resets = <&soc_clocks MMP2_CLK_TWSI3>;
334                                 #address-cells = <1>;
335                                 #size-cells = <0>;
336                                 status = "disabled";
337                         };
338
339
340                         twsi5: i2c@d4033800 {
341                                 compatible = "mrvl,mmp-twsi";
342                                 reg = <0xd4033800 0x1000>;
343                                 interrupt-parent = <&intcmux17>;
344                                 interrupts = <3>;
345                                 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
346                                 resets = <&soc_clocks MMP2_CLK_TWSI4>;
347                                 #address-cells = <1>;
348                                 #size-cells = <0>;
349                                 status = "disabled";
350                         };
351
352                         twsi6: i2c@d4034000 {
353                                 compatible = "mrvl,mmp-twsi";
354                                 reg = <0xd4034000 0x1000>;
355                                 interrupt-parent = <&intcmux17>;
356                                 interrupts = <4>;
357                                 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
358                                 resets = <&soc_clocks MMP2_CLK_TWSI5>;
359                                 #address-cells = <1>;
360                                 #size-cells = <0>;
361                                 status = "disabled";
362                         };
363
364                         rtc: rtc@d4010000 {
365                                 compatible = "mrvl,mmp-rtc";
366                                 reg = <0xd4010000 0x1000>;
367                                 interrupts = <1 0>;
368                                 interrupt-names = "rtc 1Hz", "rtc alarm";
369                                 interrupt-parent = <&intcmux5>;
370                                 clocks = <&soc_clocks MMP2_CLK_RTC>;
371                                 resets = <&soc_clocks MMP2_CLK_RTC>;
372                                 status = "disabled";
373                         };
374
375                         ssp1: spi@d4035000 {
376                                 compatible = "marvell,mmp2-ssp";
377                                 reg = <0xd4035000 0x1000>;
378                                 clocks = <&soc_clocks MMP2_CLK_SSP0>;
379                                 interrupts = <0>;
380                                 #address-cells = <1>;
381                                 #size-cells = <0>;
382                                 status = "disabled";
383                         };
384
385                         ssp2: spi@d4036000 {
386                                 compatible = "marvell,mmp2-ssp";
387                                 reg = <0xd4036000 0x1000>;
388                                 clocks = <&soc_clocks MMP2_CLK_SSP1>;
389                                 interrupts = <1>;
390                                 #address-cells = <1>;
391                                 #size-cells = <0>;
392                                 status = "disabled";
393                         };
394
395                         ssp3: spi@d4037000 {
396                                 compatible = "marvell,mmp2-ssp";
397                                 reg = <0xd4037000 0x1000>;
398                                 clocks = <&soc_clocks MMP2_CLK_SSP2>;
399                                 interrupts = <20>;
400                                 #address-cells = <1>;
401                                 #size-cells = <0>;
402                                 status = "disabled";
403                         };
404
405                         ssp4: spi@d4039000 {
406                                 compatible = "marvell,mmp2-ssp";
407                                 reg = <0xd4039000 0x1000>;
408                                 clocks = <&soc_clocks MMP2_CLK_SSP3>;
409                                 interrupts = <21>;
410                                 #address-cells = <1>;
411                                 #size-cells = <0>;
412                                 status = "disabled";
413                         };
414                 };
415
416                 soc_clocks: clocks {
417                         compatible = "marvell,mmp2-clock";
418                         reg = <0xd4050000 0x1000>,
419                               <0xd4282800 0x400>,
420                               <0xd4015000 0x1000>;
421                         reg-names = "mpmu", "apmu", "apbc";
422                         #clock-cells = <1>;
423                         #reset-cells = <1>;
424                 };
425         };
426 };