arch/arm/boot/dts/meson8m2.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
   4  */
   5
   6 #include "meson8.dtsi"
   7
   8 / {
   9         model = "Amlogic Meson8m2 SoC";
  10         compatible = "amlogic,meson8m2";
  11 }; /* end of / */
  12
  13 &clkc {
  14         compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
  15 };
  16
  17 &ethmac {
  18         compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
  19         reg = <0xc9410000 0x10000
  20                 0xc1108140 0x8>;
  21         clocks = <&clkc CLKID_ETH>,
  22                  <&clkc CLKID_MPLL2>,
  23                  <&clkc CLKID_MPLL2>;
  24         clock-names = "stmmaceth", "clkin0", "clkin1";
  25         resets = <&reset RESET_ETHERNET>;
  26         reset-names = "stmmaceth";
  27 };
  28
  29 &pinctrl_aobus {
  30         compatible = "amlogic,meson8m2-aobus-pinctrl",
  31                      "amlogic,meson8-aobus-pinctrl";
  32 };
  33
  34 &pinctrl_cbus {
  35         compatible = "amlogic,meson8m2-cbus-pinctrl",
  36                      "amlogic,meson8-cbus-pinctrl";
  37
  38         eth_rgmii_pins: ethernet {
  39                 mux {
  40                         groups = "eth_tx_clk_50m", "eth_tx_en",
  41                                  "eth_txd3", "eth_txd2",
  42                                  "eth_txd1", "eth_txd0",
  43                                  "eth_rx_clk_in", "eth_rx_dv",
  44                                  "eth_rxd3", "eth_rxd2",
  45                                  "eth_rxd1", "eth_rxd0",
  46                                  "eth_mdio", "eth_mdc";
  47                         function = "ethernet";
  48                 };
  49         };
  50 };
  51
  52 &wdt {
  53         compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
  54 };