arch/arm/boot/dts/meson8b.dtsi

   1 /*
   2  * Copyright 2015 Endless Mobile, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  *     You should have received a copy of the GNU General Public License
  21  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/clock/meson8b-clkc.h>
  48 #include <dt-bindings/gpio/meson8b-gpio.h>
  49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  50 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  51 #include "meson.dtsi"
  52
  53 / {
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@200 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a5";
  61                         next-level-cache = <&L2>;
  62                         reg = <0x200>;
  63                         enable-method = "amlogic,meson8b-smp";
  64                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  65                 };
  66
  67                 cpu1: cpu@201 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a5";
  70                         next-level-cache = <&L2>;
  71                         reg = <0x201>;
  72                         enable-method = "amlogic,meson8b-smp";
  73                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  74                 };
  75
  76                 cpu2: cpu@202 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a5";
  79                         next-level-cache = <&L2>;
  80                         reg = <0x202>;
  81                         enable-method = "amlogic,meson8b-smp";
  82                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  83                 };
  84
  85                 cpu3: cpu@203 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a5";
  88                         next-level-cache = <&L2>;
  89                         reg = <0x203>;
  90                         enable-method = "amlogic,meson8b-smp";
  91                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
  92                 };
  93         };
  94
  95         pmu {
  96                 compatible = "arm,cortex-a5-pmu";
  97                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  98                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  99                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 100                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 101                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 102         };
 103
 104         reserved-memory {
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 ranges;
 108
 109                 /* 2 MiB reserved for Hardware ROM Firmware? */
 110                 hwrom@0 {
 111                         reg = <0x0 0x200000>;
 112                         no-map;
 113                 };
 114         };
 115
 116         scu@c4300000 {
 117                 compatible = "arm,cortex-a5-scu";
 118                 reg = <0xc4300000 0x100>;
 119         };
 120 }; /* end of / */
 121
 122 &aobus {
 123         pmu: pmu@e0 {
 124                 compatible = "amlogic,meson8b-pmu", "syscon";
 125                 reg = <0xe0 0x18>;
 126         };
 127
 128         pinctrl_aobus: pinctrl@84 {
 129                 compatible = "amlogic,meson8b-aobus-pinctrl";
 130                 reg = <0x84 0xc>;
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 ranges;
 134
 135                 gpio_ao: ao-bank@14 {
 136                         reg = <0x14 0x4>,
 137                                 <0x2c 0x4>,
 138                                 <0x24 0x8>;
 139                         reg-names = "mux", "pull", "gpio";
 140                         gpio-controller;
 141                         #gpio-cells = <2>;
 142                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 143                 };
 144
 145                 uart_ao_a_pins: uart_ao_a {
 146                         mux {
 147                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 148                                 function = "uart_ao";
 149                         };
 150                 };
 151
 152                 ir_recv_pins: remote {
 153                         mux {
 154                                 groups = "remote_input";
 155                                 function = "remote";
 156                         };
 157                 };
 158         };
 159 };
 160
 161 &cbus {
 162         clkc: clock-controller@4000 {
 163                 #clock-cells = <1>;
 164                 #reset-cells = <1>;
 165                 compatible = "amlogic,meson8b-clkc";
 166                 reg = <0x8000 0x4>, <0x4000 0x400>;
 167         };
 168
 169         reset: reset-controller@4404 {
 170                 compatible = "amlogic,meson8b-reset";
 171                 reg = <0x4404 0x9c>;
 172                 #reset-cells = <1>;
 173         };
 174
 175         analog_top: analog-top@81a8 {
 176                 compatible = "amlogic,meson8b-analog-top", "syscon";
 177                 reg = <0x81a8 0x14>;
 178         };
 179
 180         pwm_ef: pwm@86c0 {
 181                 compatible = "amlogic,meson8b-pwm";
 182                 reg = <0x86c0 0x10>;
 183                 #pwm-cells = <3>;
 184                 status = "disabled";
 185         };
 186
 187         pinctrl_cbus: pinctrl@9880 {
 188                 compatible = "amlogic,meson8b-cbus-pinctrl";
 189                 reg = <0x9880 0x10>;
 190                 #address-cells = <1>;
 191                 #size-cells = <1>;
 192                 ranges;
 193
 194                 gpio: banks@80b0 {
 195                         reg = <0x80b0 0x28>,
 196                                 <0x80e8 0x18>,
 197                                 <0x8120 0x18>,
 198                                 <0x8030 0x38>;
 199                         reg-names = "mux", "pull", "pull-enable", "gpio";
 200                         gpio-controller;
 201                         #gpio-cells = <2>;
 202                         gpio-ranges = <&pinctrl_cbus 0 0 83>;
 203                 };
 204
 205                 eth_rgmii_pins: eth-rgmii {
 206                         mux {
 207                                 groups = "eth_tx_clk",
 208                                          "eth_tx_en",
 209                                          "eth_txd1_0",
 210                                          "eth_txd1_1",
 211                                          "eth_txd0_0",
 212                                          "eth_txd0_1",
 213                                          "eth_rx_clk",
 214                                          "eth_rx_dv",
 215                                          "eth_rxd1",
 216                                          "eth_rxd0",
 217                                          "eth_mdio_en",
 218                                          "eth_mdc",
 219                                          "eth_ref_clk",
 220                                          "eth_txd2",
 221                                          "eth_txd3";
 222                                 function = "ethernet";
 223                         };
 224                 };
 225
 226                 eth_rmii_pins: eth-rmii {
 227                         mux {
 228                                 groups = "eth_tx_en",
 229                                          "eth_txd1_0",
 230                                          "eth_txd0_0",
 231                                          "eth_rx_clk",
 232                                          "eth_rx_dv",
 233                                          "eth_rxd1",
 234                                          "eth_rxd0",
 235                                          "eth_mdio_en",
 236                                          "eth_mdc";
 237                                 function = "ethernet";
 238                         };
 239                 };
 240
 241                 i2c_a_pins: i2c-a {
 242                         mux {
 243                                 groups = "i2c_sda_a", "i2c_sck_a";
 244                                 function = "i2c_a";
 245                         };
 246                 };
 247
 248                 sd_b_pins: sd-b {
 249                         mux {
 250                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
 251                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
 252                                 function = "sd_b";
 253                         };
 254                 };
 255
 256                 pwm_c1_pins: pwm-c1 {
 257                         mux {
 258                                 groups = "pwm_c1";
 259                                 function = "pwm_c";
 260                         };
 261                 };
 262
 263                 uart_b0_pins: uart-b0 {
 264                         mux {
 265                                 groups = "uart_tx_b0",
 266                                        "uart_rx_b0";
 267                                 function = "uart_b";
 268                         };
 269                 };
 270
 271                 uart_b0_cts_rts_pins: uart-b0-cts-rts {
 272                         mux {
 273                                 groups = "uart_cts_b0",
 274                                        "uart_rts_b0";
 275                                 function = "uart_b";
 276                         };
 277                 };
 278         };
 279 };
 280
 281 &ahb_sram {
 282         smp-sram@1ff80 {
 283                 compatible = "amlogic,meson8b-smp-sram";
 284                 reg = <0x1ff80 0x8>;
 285         };
 286 };
 287
 288
 289 &efuse {
 290         compatible = "amlogic,meson8b-efuse";
 291         clocks = <&clkc CLKID_EFUSE>;
 292         clock-names = "core";
 293 };
 294
 295 &ethmac {
 296         compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
 297
 298         reg = <0xc9410000 0x10000
 299                0xc1108140 0x4>;
 300
 301         clocks = <&clkc CLKID_ETH>,
 302                  <&clkc CLKID_MPLL2>,
 303                  <&clkc CLKID_MPLL2>;
 304         clock-names = "stmmaceth", "clkin0", "clkin1";
 305
 306         resets = <&reset RESET_ETHERNET>;
 307         reset-names = "stmmaceth";
 308 };
 309
 310 &gpio_intc {
 311         compatible = "amlogic,meson-gpio-intc",
 312                      "amlogic,meson8b-gpio-intc";
 313         status = "okay";
 314 };
 315
 316 &hwrng {
 317         compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
 318         clocks = <&clkc CLKID_RNG0>;
 319         clock-names = "core";
 320 };
 321
 322 &i2c_AO {
 323         clocks = <&clkc CLKID_CLK81>;
 324 };
 325
 326 &i2c_A {
 327         clocks = <&clkc CLKID_I2C>;
 328 };
 329
 330 &i2c_B {
 331         clocks = <&clkc CLKID_I2C>;
 332 };
 333
 334 &L2 {
 335         arm,data-latency = <3 3 3>;
 336         arm,tag-latency = <2 2 2>;
 337         arm,filter-ranges = <0x100000 0xc0000000>;
 338         prefetch-data = <1>;
 339         prefetch-instr = <1>;
 340         arm,shared-override;
 341 };
 342
 343 &pwm_ab {
 344         compatible = "amlogic,meson8b-pwm";
 345 };
 346
 347 &pwm_cd {
 348         compatible = "amlogic,meson8b-pwm";
 349 };
 350
 351 &saradc {
 352         compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
 353         clocks = <&clkc CLKID_XTAL>,
 354                 <&clkc CLKID_SAR_ADC>;
 355         clock-names = "clkin", "core";
 356 };
 357
 358 &sdio {
 359         compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
 360         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 361         clock-names = "core", "clkin";
 362 };
 363
 364 &uart_AO {
 365         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 366         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
 367         clock-names = "baud", "xtal", "pclk";
 368 };
 369
 370 &uart_A {
 371         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 372         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
 373         clock-names = "baud", "xtal", "pclk";
 374 };
 375
 376 &uart_B {
 377         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 378         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
 379         clock-names = "baud", "xtal", "pclk";
 380 };
 381
 382 &uart_C {
 383         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 384         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
 385         clock-names = "baud", "xtal", "pclk";
 386 };
 387
 388 &usb0 {
 389         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 390         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 391         clock-names = "otg";
 392 };
 393
 394 &usb1 {
 395         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 396         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 397         clock-names = "otg";
 398 };
 399
 400 &usb0_phy {
 401         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 402         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 403         clock-names = "usb_general", "usb";
 404         resets = <&reset RESET_USB_OTG>;
 405 };
 406
 407 &usb1_phy {
 408         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 409         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 410         clock-names = "usb_general", "usb";
 411         resets = <&reset RESET_USB_OTG>;
 412 };
 413
 414 &wdt {
 415         compatible = "amlogic,meson8b-wdt";
 416 };