arch/arm/boot/dts/meson8b.dtsi

   1 /*
   2  * Copyright 2015 Endless Mobile, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  *     You should have received a copy of the GNU General Public License
  21  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/clock/meson8b-clkc.h>
  48 #include <dt-bindings/gpio/meson8b-gpio.h>
  49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  50 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  51 #include "meson.dtsi"
  52
  53 / {
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu@200 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a5";
  61                         next-level-cache = <&L2>;
  62                         reg = <0x200>;
  63                         enable-method = "amlogic,meson8b-smp";
  64                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  65                 };
  66
  67                 cpu@201 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a5";
  70                         next-level-cache = <&L2>;
  71                         reg = <0x201>;
  72                         enable-method = "amlogic,meson8b-smp";
  73                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  74                 };
  75
  76                 cpu@202 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a5";
  79                         next-level-cache = <&L2>;
  80                         reg = <0x202>;
  81                         enable-method = "amlogic,meson8b-smp";
  82                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  83                 };
  84
  85                 cpu@203 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a5";
  88                         next-level-cache = <&L2>;
  89                         reg = <0x203>;
  90                         enable-method = "amlogic,meson8b-smp";
  91                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
  92                 };
  93         };
  94
  95         reserved-memory {
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges;
  99
 100                 /* 2 MiB reserved for Hardware ROM Firmware? */
 101                 hwrom@0 {
 102                         reg = <0x0 0x200000>;
 103                         no-map;
 104                 };
 105         };
 106
 107         scu@c4300000 {
 108                 compatible = "arm,cortex-a5-scu";
 109                 reg = <0xc4300000 0x100>;
 110         };
 111 }; /* end of / */
 112
 113 &aobus {
 114         pmu: pmu@e0 {
 115                 compatible = "amlogic,meson8b-pmu", "syscon";
 116                 reg = <0xe0 0x18>;
 117         };
 118
 119         pinctrl_aobus: pinctrl@84 {
 120                 compatible = "amlogic,meson8b-aobus-pinctrl";
 121                 reg = <0x84 0xc>;
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124                 ranges;
 125
 126                 gpio_ao: ao-bank@14 {
 127                         reg = <0x14 0x4>,
 128                                 <0x2c 0x4>,
 129                                 <0x24 0x8>;
 130                         reg-names = "mux", "pull", "gpio";
 131                         gpio-controller;
 132                         #gpio-cells = <2>;
 133                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 134                 };
 135
 136                 uart_ao_a_pins: uart_ao_a {
 137                         mux {
 138                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 139                                 function = "uart_ao";
 140                         };
 141                 };
 142         };
 143 };
 144
 145 &cbus {
 146         clkc: clock-controller@4000 {
 147                 #clock-cells = <1>;
 148                 #reset-cells = <1>;
 149                 compatible = "amlogic,meson8b-clkc";
 150                 reg = <0x8000 0x4>, <0x4000 0x460>;
 151         };
 152
 153         reset: reset-controller@4404 {
 154                 compatible = "amlogic,meson8b-reset";
 155                 reg = <0x4404 0x20>;
 156                 #reset-cells = <1>;
 157         };
 158
 159         analog_top: analog-top@81a8 {
 160                 compatible = "amlogic,meson8b-analog-top", "syscon";
 161                 reg = <0x81a8 0x14>;
 162         };
 163
 164         pwm_ef: pwm@86c0 {
 165                 compatible = "amlogic,meson8b-pwm";
 166                 reg = <0x86c0 0x10>;
 167                 #pwm-cells = <3>;
 168                 status = "disabled";
 169         };
 170
 171         pinctrl_cbus: pinctrl@9880 {
 172                 compatible = "amlogic,meson8b-cbus-pinctrl";
 173                 reg = <0x9880 0x10>;
 174                 #address-cells = <1>;
 175                 #size-cells = <1>;
 176                 ranges;
 177
 178                 gpio: banks@80b0 {
 179                         reg = <0x80b0 0x28>,
 180                                 <0x80e8 0x18>,
 181                                 <0x8120 0x18>,
 182                                 <0x8030 0x38>;
 183                         reg-names = "mux", "pull", "pull-enable", "gpio";
 184                         gpio-controller;
 185                         #gpio-cells = <2>;
 186                         gpio-ranges = <&pinctrl_cbus 0 0 130>;
 187                 };
 188         };
 189 };
 190
 191 &ahb_sram {
 192         smp-sram@1ff80 {
 193                 compatible = "amlogic,meson8b-smp-sram";
 194                 reg = <0x1ff80 0x8>;
 195         };
 196 };
 197
 198
 199 &efuse {
 200         compatible = "amlogic,meson8b-efuse";
 201         clocks = <&clkc CLKID_EFUSE>;
 202         clock-names = "core";
 203 };
 204
 205 &ethmac {
 206         clocks = <&clkc CLKID_ETH>;
 207         clock-names = "stmmaceth";
 208 };
 209
 210 &gpio_intc {
 211         compatible = "amlogic,meson-gpio-intc",
 212                      "amlogic,meson8b-gpio-intc";
 213         status = "okay";
 214 };
 215
 216 &hwrng {
 217         compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
 218         clocks = <&clkc CLKID_RNG0>;
 219         clock-names = "core";
 220 };
 221
 222 &L2 {
 223         arm,data-latency = <3 3 3>;
 224         arm,tag-latency = <2 2 2>;
 225         arm,filter-ranges = <0x100000 0xc0000000>;
 226         prefetch-data = <1>;
 227         prefetch-instr = <1>;
 228         arm,shared-override;
 229 };
 230
 231 &pwm_ab {
 232         compatible = "amlogic,meson8b-pwm";
 233 };
 234
 235 &pwm_cd {
 236         compatible = "amlogic,meson8b-pwm";
 237 };
 238
 239 &saradc {
 240         compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
 241         clocks = <&clkc CLKID_XTAL>,
 242                 <&clkc CLKID_SAR_ADC>;
 243         clock-names = "clkin", "core";
 244 };
 245
 246 &sdio {
 247         compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
 248         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 249         clock-names = "core", "clkin";
 250 };
 251
 252 &uart_AO {
 253         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 254         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
 255         clock-names = "baud", "xtal", "pclk";
 256 };
 257
 258 &uart_A {
 259         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 260         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
 261         clock-names = "baud", "xtal", "pclk";
 262 };
 263
 264 &uart_B {
 265         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 266         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
 267         clock-names = "baud", "xtal", "pclk";
 268 };
 269
 270 &uart_C {
 271         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 272         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
 273         clock-names = "baud", "xtal", "pclk";
 274 };
 275
 276 &usb0 {
 277         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 278         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 279         clock-names = "otg";
 280 };
 281
 282 &usb1 {
 283         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 284         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 285         clock-names = "otg";
 286 };
 287
 288 &usb0_phy {
 289         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 290         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 291         clock-names = "usb_general", "usb";
 292         resets = <&reset RESET_USB_OTG>;
 293 };
 294
 295 &usb1_phy {
 296         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 297         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 298         clock-names = "usb_general", "usb";
 299         resets = <&reset RESET_USB_OTG>;
 300 };
 301
 302 &wdt {
 303         compatible = "amlogic,meson8b-wdt";
 304 };