arch/arm/boot/dts/meson8b.dtsi

   1 /*
   2  * Copyright 2015 Endless Mobile, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  *     You should have received a copy of the GNU General Public License
  21  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/clock/meson8b-clkc.h>
  48 #include <dt-bindings/gpio/meson8b-gpio.h>
  49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  50 #include "meson.dtsi"
  51
  52 / {
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu@200 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a5";
  60                         next-level-cache = <&L2>;
  61                         reg = <0x200>;
  62                 };
  63
  64                 cpu@201 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a5";
  67                         next-level-cache = <&L2>;
  68                         reg = <0x201>;
  69                 };
  70
  71                 cpu@202 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a5";
  74                         next-level-cache = <&L2>;
  75                         reg = <0x202>;
  76                 };
  77
  78                 cpu@203 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a5";
  81                         next-level-cache = <&L2>;
  82                         reg = <0x203>;
  83                 };
  84         };
  85
  86         scu@c4300000 {
  87                 compatible = "arm,cortex-a5-scu";
  88                 reg = <0xc4300000 0x100>;
  89         };
  90 }; /* end of / */
  91
  92 &aobus {
  93         pinctrl_aobus: pinctrl@84 {
  94                 compatible = "amlogic,meson8b-aobus-pinctrl";
  95                 reg = <0x84 0xc>;
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges;
  99
 100                 gpio_ao: ao-bank@14 {
 101                         reg = <0x14 0x4>,
 102                                 <0x2c 0x4>,
 103                                 <0x24 0x8>;
 104                         reg-names = "mux", "pull", "gpio";
 105                         gpio-controller;
 106                         #gpio-cells = <2>;
 107                         gpio-ranges = <&pinctrl_aobus 0 130 16>;
 108                 };
 109
 110                 uart_ao_a_pins: uart_ao_a {
 111                         mux {
 112                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 113                                 function = "uart_ao";
 114                         };
 115                 };
 116         };
 117 };
 118
 119 &cbus {
 120         clkc: clock-controller@4000 {
 121                 #clock-cells = <1>;
 122                 compatible = "amlogic,meson8b-clkc";
 123                 reg = <0x8000 0x4>, <0x4000 0x460>;
 124         };
 125
 126         reset: reset-controller@4404 {
 127                 compatible = "amlogic,meson8b-reset";
 128                 reg = <0x4404 0x20>;
 129                 #reset-cells = <1>;
 130         };
 131
 132         pwm_ab: pwm@8550 {
 133                 compatible = "amlogic,meson8b-pwm";
 134                 reg = <0x8550 0x10>;
 135                 #pwm-cells = <3>;
 136                 status = "disabled";
 137         };
 138
 139         pwm_cd: pwm@8650 {
 140                 compatible = "amlogic,meson8b-pwm";
 141                 reg = <0x8650 0x10>;
 142                 #pwm-cells = <3>;
 143                 status = "disabled";
 144         };
 145
 146         pwm_ef: pwm@86c0 {
 147                 compatible = "amlogic,meson8b-pwm";
 148                 reg = <0x86c0 0x10>;
 149                 #pwm-cells = <3>;
 150                 status = "disabled";
 151         };
 152
 153         wdt: watchdog@9900 {
 154                 compatible = "amlogic,meson8b-wdt";
 155                 reg = <0x9900 0x8>;
 156                 interrupts = <0 0 1>;
 157         };
 158
 159         pinctrl_cbus: pinctrl@9880 {
 160                 compatible = "amlogic,meson8b-cbus-pinctrl";
 161                 reg = <0x9880 0x10>;
 162                 #address-cells = <1>;
 163                 #size-cells = <1>;
 164                 ranges;
 165
 166                 gpio: banks@80b0 {
 167                         reg = <0x80b0 0x28>,
 168                                 <0x80e8 0x18>,
 169                                 <0x8120 0x18>,
 170                                 <0x8030 0x38>;
 171                         reg-names = "mux", "pull", "pull-enable", "gpio";
 172                         gpio-controller;
 173                         #gpio-cells = <2>;
 174                         gpio-ranges = <&pinctrl_cbus 0 0 130>;
 175                 };
 176         };
 177 };
 178
 179 &ethmac {
 180         clocks = <&clkc CLKID_ETH>;
 181         clock-names = "stmmaceth";
 182 };
 183
 184 &hwrng {
 185         compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
 186         clocks = <&clkc CLKID_RNG0>;
 187         clock-names = "core";
 188 };
 189
 190 &L2 {
 191         arm,data-latency = <3 3 3>;
 192         arm,tag-latency = <2 2 2>;
 193         arm,filter-ranges = <0x100000 0xc0000000>;
 194 };
 195
 196 &saradc {
 197         compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
 198         clocks = <&clkc CLKID_XTAL>,
 199                 <&clkc CLKID_SAR_ADC>,
 200                 <&clkc CLKID_SANA>;
 201         clock-names = "clkin", "core", "sana";
 202 };
 203
 204 &uart_AO {
 205         clocks = <&clkc CLKID_CLK81>;
 206 };
 207
 208 &uart_A {
 209         clocks = <&clkc CLKID_CLK81>;
 210 };
 211
 212 &uart_B {
 213         clocks = <&clkc CLKID_CLK81>;
 214 };
 215
 216 &uart_C {
 217         clocks = <&clkc CLKID_CLK81>;
 218 };
 219
 220 &usb0 {
 221         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 222         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 223         clock-names = "otg";
 224 };
 225
 226 &usb1 {
 227         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 228         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 229         clock-names = "otg";
 230 };
 231
 232 &usb0_phy {
 233         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 234         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 235         clock-names = "usb_general", "usb";
 236         resets = <&reset RESET_USB_OTG>;
 237 };
 238
 239 &usb1_phy {
 240         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 241         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 242         clock-names = "usb_general", "usb";
 243         resets = <&reset RESET_USB_OTG>;
 244 };