arch/arm/boot/dts/meson8b.dtsi

   1 /*
   2  * Copyright 2015 Endless Mobile, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  *     You should have received a copy of the GNU General Public License
  21  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/clock/meson8b-clkc.h>
  48 #include <dt-bindings/gpio/meson8b-gpio.h>
  49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  50 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  51 #include "meson.dtsi"
  52
  53 / {
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@200 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a5";
  61                         next-level-cache = <&L2>;
  62                         reg = <0x200>;
  63                         enable-method = "amlogic,meson8b-smp";
  64                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  65                         operating-points-v2 = <&cpu_opp_table>;
  66                         clocks = <&clkc CLKID_CPUCLK>;
  67                 };
  68
  69                 cpu1: cpu@201 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a5";
  72                         next-level-cache = <&L2>;
  73                         reg = <0x201>;
  74                         enable-method = "amlogic,meson8b-smp";
  75                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  76                         operating-points-v2 = <&cpu_opp_table>;
  77                         clocks = <&clkc CLKID_CPUCLK>;
  78                 };
  79
  80                 cpu2: cpu@202 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a5";
  83                         next-level-cache = <&L2>;
  84                         reg = <0x202>;
  85                         enable-method = "amlogic,meson8b-smp";
  86                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  87                         operating-points-v2 = <&cpu_opp_table>;
  88                         clocks = <&clkc CLKID_CPUCLK>;
  89                 };
  90
  91                 cpu3: cpu@203 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a5";
  94                         next-level-cache = <&L2>;
  95                         reg = <0x203>;
  96                         enable-method = "amlogic,meson8b-smp";
  97                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
  98                         operating-points-v2 = <&cpu_opp_table>;
  99                         clocks = <&clkc CLKID_CPUCLK>;
 100                 };
 101         };
 102
 103         cpu_opp_table: opp-table {
 104                 compatible = "operating-points-v2";
 105                 opp-shared;
 106
 107                 opp-96000000 {
 108                         opp-hz = /bits/ 64 <96000000>;
 109                         opp-microvolt = <860000>;
 110                 };
 111                 opp-192000000 {
 112                         opp-hz = /bits/ 64 <192000000>;
 113                         opp-microvolt = <860000>;
 114                 };
 115                 opp-312000000 {
 116                         opp-hz = /bits/ 64 <312000000>;
 117                         opp-microvolt = <860000>;
 118                 };
 119                 opp-408000000 {
 120                         opp-hz = /bits/ 64 <408000000>;
 121                         opp-microvolt = <860000>;
 122                 };
 123                 opp-504000000 {
 124                         opp-hz = /bits/ 64 <504000000>;
 125                         opp-microvolt = <860000>;
 126                 };
 127                 opp-600000000 {
 128                         opp-hz = /bits/ 64 <600000000>;
 129                         opp-microvolt = <860000>;
 130                 };
 131                 opp-720000000 {
 132                         opp-hz = /bits/ 64 <720000000>;
 133                         opp-microvolt = <860000>;
 134                 };
 135                 opp-816000000 {
 136                         opp-hz = /bits/ 64 <816000000>;
 137                         opp-microvolt = <900000>;
 138                 };
 139                 opp-1008000000 {
 140                         opp-hz = /bits/ 64 <1008000000>;
 141                         opp-microvolt = <1140000>;
 142                 };
 143                 opp-1200000000 {
 144                         opp-hz = /bits/ 64 <1200000000>;
 145                         opp-microvolt = <1140000>;
 146                 };
 147                 opp-1320000000 {
 148                         opp-hz = /bits/ 64 <1320000000>;
 149                         opp-microvolt = <1140000>;
 150                 };
 151                 opp-1488000000 {
 152                         opp-hz = /bits/ 64 <1488000000>;
 153                         opp-microvolt = <1140000>;
 154                 };
 155                 opp-1536000000 {
 156                         opp-hz = /bits/ 64 <1536000000>;
 157                         opp-microvolt = <1140000>;
 158                 };
 159         };
 160
 161         pmu {
 162                 compatible = "arm,cortex-a5-pmu";
 163                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 167                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 168         };
 169
 170         reserved-memory {
 171                 #address-cells = <1>;
 172                 #size-cells = <1>;
 173                 ranges;
 174
 175                 /* 2 MiB reserved for Hardware ROM Firmware? */
 176                 hwrom@0 {
 177                         reg = <0x0 0x200000>;
 178                         no-map;
 179                 };
 180         };
 181 }; /* end of / */
 182
 183 &aobus {
 184         pmu: pmu@e0 {
 185                 compatible = "amlogic,meson8b-pmu", "syscon";
 186                 reg = <0xe0 0x18>;
 187         };
 188
 189         pinctrl_aobus: pinctrl@84 {
 190                 compatible = "amlogic,meson8b-aobus-pinctrl";
 191                 reg = <0x84 0xc>;
 192                 #address-cells = <1>;
 193                 #size-cells = <1>;
 194                 ranges;
 195
 196                 gpio_ao: ao-bank@14 {
 197                         reg = <0x14 0x4>,
 198                                 <0x2c 0x4>,
 199                                 <0x24 0x8>;
 200                         reg-names = "mux", "pull", "gpio";
 201                         gpio-controller;
 202                         #gpio-cells = <2>;
 203                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 204                 };
 205
 206                 uart_ao_a_pins: uart_ao_a {
 207                         mux {
 208                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 209                                 function = "uart_ao";
 210                                 bias-disable;
 211                         };
 212                 };
 213
 214                 ir_recv_pins: remote {
 215                         mux {
 216                                 groups = "remote_input";
 217                                 function = "remote";
 218                                 bias-disable;
 219                         };
 220                 };
 221         };
 222 };
 223
 224 &cbus {
 225         clkc: clock-controller@4000 {
 226                 #clock-cells = <1>;
 227                 #reset-cells = <1>;
 228                 compatible = "amlogic,meson8b-clkc";
 229                 reg = <0x8000 0x4>, <0x4000 0x400>;
 230         };
 231
 232         reset: reset-controller@4404 {
 233                 compatible = "amlogic,meson8b-reset";
 234                 reg = <0x4404 0x9c>;
 235                 #reset-cells = <1>;
 236         };
 237
 238         analog_top: analog-top@81a8 {
 239                 compatible = "amlogic,meson8b-analog-top", "syscon";
 240                 reg = <0x81a8 0x14>;
 241         };
 242
 243         pwm_ef: pwm@86c0 {
 244                 compatible = "amlogic,meson8b-pwm";
 245                 reg = <0x86c0 0x10>;
 246                 #pwm-cells = <3>;
 247                 status = "disabled";
 248         };
 249
 250         pinctrl_cbus: pinctrl@9880 {
 251                 compatible = "amlogic,meson8b-cbus-pinctrl";
 252                 reg = <0x9880 0x10>;
 253                 #address-cells = <1>;
 254                 #size-cells = <1>;
 255                 ranges;
 256
 257                 gpio: banks@80b0 {
 258                         reg = <0x80b0 0x28>,
 259                                 <0x80e8 0x18>,
 260                                 <0x8120 0x18>,
 261                                 <0x8030 0x38>;
 262                         reg-names = "mux", "pull", "pull-enable", "gpio";
 263                         gpio-controller;
 264                         #gpio-cells = <2>;
 265                         gpio-ranges = <&pinctrl_cbus 0 0 83>;
 266                 };
 267
 268                 eth_rgmii_pins: eth-rgmii {
 269                         mux {
 270                                 groups = "eth_tx_clk",
 271                                          "eth_tx_en",
 272                                          "eth_txd1_0",
 273                                          "eth_txd1_1",
 274                                          "eth_txd0_0",
 275                                          "eth_txd0_1",
 276                                          "eth_rx_clk",
 277                                          "eth_rx_dv",
 278                                          "eth_rxd1",
 279                                          "eth_rxd0",
 280                                          "eth_mdio_en",
 281                                          "eth_mdc",
 282                                          "eth_ref_clk",
 283                                          "eth_txd2",
 284                                          "eth_txd3";
 285                                 function = "ethernet";
 286                                 bias-disable;
 287                         };
 288                 };
 289
 290                 eth_rmii_pins: eth-rmii {
 291                         mux {
 292                                 groups = "eth_tx_en",
 293                                          "eth_txd1_0",
 294                                          "eth_txd0_0",
 295                                          "eth_rx_clk",
 296                                          "eth_rx_dv",
 297                                          "eth_rxd1",
 298                                          "eth_rxd0",
 299                                          "eth_mdio_en",
 300                                          "eth_mdc";
 301                                 function = "ethernet";
 302                                 bias-disable;
 303                         };
 304                 };
 305
 306                 i2c_a_pins: i2c-a {
 307                         mux {
 308                                 groups = "i2c_sda_a", "i2c_sck_a";
 309                                 function = "i2c_a";
 310                                 bias-disable;
 311                         };
 312                 };
 313
 314                 sd_b_pins: sd-b {
 315                         mux {
 316                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
 317                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
 318                                 function = "sd_b";
 319                                 bias-disable;
 320                         };
 321                 };
 322
 323                 pwm_c1_pins: pwm-c1 {
 324                         mux {
 325                                 groups = "pwm_c1";
 326                                 function = "pwm_c";
 327                                 bias-disable;
 328                         };
 329                 };
 330
 331                 uart_b0_pins: uart-b0 {
 332                         mux {
 333                                 groups = "uart_tx_b0",
 334                                        "uart_rx_b0";
 335                                 function = "uart_b";
 336                                 bias-disable;
 337                         };
 338                 };
 339
 340                 uart_b0_cts_rts_pins: uart-b0-cts-rts {
 341                         mux {
 342                                 groups = "uart_cts_b0",
 343                                        "uart_rts_b0";
 344                                 function = "uart_b";
 345                                 bias-disable;
 346                         };
 347                 };
 348         };
 349 };
 350
 351 &ahb_sram {
 352         smp-sram@1ff80 {
 353                 compatible = "amlogic,meson8b-smp-sram";
 354                 reg = <0x1ff80 0x8>;
 355         };
 356 };
 357
 358
 359 &efuse {
 360         compatible = "amlogic,meson8b-efuse";
 361         clocks = <&clkc CLKID_EFUSE>;
 362         clock-names = "core";
 363 };
 364
 365 &ethmac {
 366         compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
 367
 368         reg = <0xc9410000 0x10000
 369                0xc1108140 0x4>;
 370
 371         clocks = <&clkc CLKID_ETH>,
 372                  <&clkc CLKID_MPLL2>,
 373                  <&clkc CLKID_MPLL2>;
 374         clock-names = "stmmaceth", "clkin0", "clkin1";
 375
 376         resets = <&reset RESET_ETHERNET>;
 377         reset-names = "stmmaceth";
 378 };
 379
 380 &gpio_intc {
 381         compatible = "amlogic,meson-gpio-intc",
 382                      "amlogic,meson8b-gpio-intc";
 383         status = "okay";
 384 };
 385
 386 &hwrng {
 387         compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
 388         clocks = <&clkc CLKID_RNG0>;
 389         clock-names = "core";
 390 };
 391
 392 &i2c_AO {
 393         clocks = <&clkc CLKID_CLK81>;
 394 };
 395
 396 &i2c_A {
 397         clocks = <&clkc CLKID_I2C>;
 398 };
 399
 400 &i2c_B {
 401         clocks = <&clkc CLKID_I2C>;
 402 };
 403
 404 &L2 {
 405         arm,data-latency = <3 3 3>;
 406         arm,tag-latency = <2 2 2>;
 407         arm,filter-ranges = <0x100000 0xc0000000>;
 408         prefetch-data = <1>;
 409         prefetch-instr = <1>;
 410         arm,shared-override;
 411 };
 412
 413 &periph {
 414         scu@0 {
 415                 compatible = "arm,cortex-a5-scu";
 416                 reg = <0x0 0x100>;
 417         };
 418
 419         timer@200 {
 420                 compatible = "arm,cortex-a5-global-timer";
 421                 reg = <0x200 0x20>;
 422                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 423                 clocks = <&clkc CLKID_PERIPH>;
 424
 425                 /*
 426                  * the arm_global_timer driver currently does not handle clock
 427                  * rate changes. Keep it disabled for now.
 428                  */
 429                 status = "disabled";
 430         };
 431
 432         timer@600 {
 433                 compatible = "arm,cortex-a5-twd-timer";
 434                 reg = <0x600 0x20>;
 435                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 436                 clocks = <&clkc CLKID_PERIPH>;
 437         };
 438 };
 439
 440 &pwm_ab {
 441         compatible = "amlogic,meson8b-pwm";
 442 };
 443
 444 &pwm_cd {
 445         compatible = "amlogic,meson8b-pwm";
 446 };
 447
 448 &saradc {
 449         compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
 450         clocks = <&clkc CLKID_XTAL>,
 451                 <&clkc CLKID_SAR_ADC>;
 452         clock-names = "clkin", "core";
 453 };
 454
 455 &sdio {
 456         compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
 457         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 458         clock-names = "core", "clkin";
 459 };
 460
 461 &timer_abcde {
 462         clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
 463         clock-names = "xtal", "pclk";
 464 };
 465
 466 &uart_AO {
 467         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 468         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
 469         clock-names = "baud", "xtal", "pclk";
 470 };
 471
 472 &uart_A {
 473         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 474         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
 475         clock-names = "baud", "xtal", "pclk";
 476 };
 477
 478 &uart_B {
 479         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 480         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
 481         clock-names = "baud", "xtal", "pclk";
 482 };
 483
 484 &uart_C {
 485         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 486         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
 487         clock-names = "baud", "xtal", "pclk";
 488 };
 489
 490 &usb0 {
 491         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 492         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 493         clock-names = "otg";
 494 };
 495
 496 &usb1 {
 497         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 498         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 499         clock-names = "otg";
 500 };
 501
 502 &usb0_phy {
 503         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 504         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 505         clock-names = "usb_general", "usb";
 506         resets = <&reset RESET_USB_OTG>;
 507 };
 508
 509 &usb1_phy {
 510         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 511         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 512         clock-names = "usb_general", "usb";
 513         resets = <&reset RESET_USB_OTG>;
 514 };
 515
 516 &wdt {
 517         compatible = "amlogic,meson8b-wdt";
 518 };