arch/arm/boot/dts/meson8.dtsi

   1 /*
   2  * Copyright 2014 Carlo Caione <carlo@caione.org>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public License
  20  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include <dt-bindings/clock/meson8b-clkc.h>
  47 #include <dt-bindings/gpio/meson8-gpio.h>
  48 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  49 #include "meson.dtsi"
  50
  51 / {
  52         model = "Amlogic Meson8 SoC";
  53         compatible = "amlogic,meson8";
  54
  55         cpus {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 cpu@200 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a9";
  62                         next-level-cache = <&L2>;
  63                         reg = <0x200>;
  64                         enable-method = "amlogic,meson8-smp";
  65                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  66                 };
  67
  68                 cpu@201 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a9";
  71                         next-level-cache = <&L2>;
  72                         reg = <0x201>;
  73                         enable-method = "amlogic,meson8-smp";
  74                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  75                 };
  76
  77                 cpu@202 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a9";
  80                         next-level-cache = <&L2>;
  81                         reg = <0x202>;
  82                         enable-method = "amlogic,meson8-smp";
  83                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  84                 };
  85
  86                 cpu@203 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a9";
  89                         next-level-cache = <&L2>;
  90                         reg = <0x203>;
  91                         enable-method = "amlogic,meson8-smp";
  92                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
  93                 };
  94         };
  95
  96         reserved-memory {
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 ranges;
 100
 101                 /* 2 MiB reserved for Hardware ROM Firmware? */
 102                 hwrom@0 {
 103                         reg = <0x0 0x200000>;
 104                         no-map;
 105                 };
 106
 107                 /*
 108                  * 1 MiB reserved for the "ARM Power Firmware": this is ARM
 109                  * code which is responsible for system suspend. It loads a
 110                  * piece of ARC code ("arc_power" in the vendor u-boot tree)
 111                  * into SRAM, executes that and shuts down the (last) ARM core.
 112                  * The arc_power firmware then checks various wakeup sources
 113                  * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
 114                  * simply the power key) and re-starts the ARM core once it
 115                  * detects a wakeup request.
 116                  */
 117                 power-firmware@4f00000 {
 118                         reg = <0x4f00000 0x100000>;
 119                         no-map;
 120                 };
 121         };
 122
 123         scu@c4300000 {
 124                 compatible = "arm,cortex-a9-scu";
 125                 reg = <0xc4300000 0x100>;
 126         };
 127 }; /* end of / */
 128
 129 &aobus {
 130         pmu: pmu@e0 {
 131                 compatible = "amlogic,meson8-pmu", "syscon";
 132                 reg = <0xe0 0x8>;
 133         };
 134
 135         pinctrl_aobus: pinctrl@84 {
 136                 compatible = "amlogic,meson8-aobus-pinctrl";
 137                 reg = <0x84 0xc>;
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 gpio_ao: ao-bank@14 {
 143                         reg = <0x14 0x4>,
 144                               <0x2c 0x4>,
 145                               <0x24 0x8>;
 146                         reg-names = "mux", "pull", "gpio";
 147                         gpio-controller;
 148                         #gpio-cells = <2>;
 149                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 150                 };
 151
 152                 uart_ao_a_pins: uart_ao_a {
 153                         mux {
 154                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 155                                 function = "uart_ao";
 156                         };
 157                 };
 158
 159                 i2c_ao_pins: i2c_mst_ao {
 160                         mux {
 161                                 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
 162                                 function = "i2c_mst_ao";
 163                         };
 164                 };
 165
 166                 ir_recv_pins: remote {
 167                         mux {
 168                                 groups = "remote_input";
 169                                 function = "remote";
 170                         };
 171                 };
 172
 173                 pwm_f_ao_pins: pwm-f-ao {
 174                         mux {
 175                                 groups = "pwm_f_ao";
 176                                 function = "pwm_f_ao";
 177                         };
 178                 };
 179         };
 180 };
 181
 182 &cbus {
 183         clkc: clock-controller@4000 {
 184                 #clock-cells = <1>;
 185                 #reset-cells = <1>;
 186                 compatible = "amlogic,meson8-clkc";
 187                 reg = <0x8000 0x4>, <0x4000 0x460>;
 188         };
 189
 190         analog_top: analog-top@81a8 {
 191                 compatible = "amlogic,meson8-analog-top", "syscon";
 192                 reg = <0x81a8 0x14>;
 193         };
 194
 195         pwm_ef: pwm@86c0 {
 196                 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 197                 reg = <0x86c0 0x10>;
 198                 #pwm-cells = <3>;
 199                 status = "disabled";
 200         };
 201
 202         pinctrl_cbus: pinctrl@9880 {
 203                 compatible = "amlogic,meson8-cbus-pinctrl";
 204                 reg = <0x9880 0x10>;
 205                 #address-cells = <1>;
 206                 #size-cells = <1>;
 207                 ranges;
 208
 209                 gpio: banks@80b0 {
 210                         reg = <0x80b0 0x28>,
 211                               <0x80e8 0x18>,
 212                               <0x8120 0x18>,
 213                               <0x8030 0x30>;
 214                         reg-names = "mux", "pull", "pull-enable", "gpio";
 215                         gpio-controller;
 216                         #gpio-cells = <2>;
 217                         gpio-ranges = <&pinctrl_cbus 0 0 120>;
 218                 };
 219
 220                 sd_a_pins: sd-a {
 221                         mux {
 222                                 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
 223                                         "sd_d3_a", "sd_clk_a", "sd_cmd_a";
 224                                 function = "sd_a";
 225                         };
 226                 };
 227
 228                 sd_b_pins: sd-b {
 229                         mux {
 230                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
 231                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
 232                                 function = "sd_b";
 233                         };
 234                 };
 235
 236                 sd_c_pins: sd-c {
 237                         mux {
 238                                 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
 239                                         "sd_d3_c", "sd_clk_c", "sd_cmd_c";
 240                                 function = "sd_c";
 241                         };
 242                 };
 243
 244                 spi_nor_pins: nor {
 245                         mux {
 246                                 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
 247                                 function = "nor";
 248                         };
 249                 };
 250
 251                 eth_pins: ethernet {
 252                         mux {
 253                                 groups = "eth_tx_clk_50m", "eth_tx_en",
 254                                          "eth_txd1", "eth_txd0",
 255                                          "eth_rx_clk_in", "eth_rx_dv",
 256                                          "eth_rxd1", "eth_rxd0", "eth_mdio",
 257                                          "eth_mdc";
 258                                 function = "ethernet";
 259                         };
 260                 };
 261
 262                 pwm_e_pins: pwm-e {
 263                         mux {
 264                                 groups = "pwm_e";
 265                                 function = "pwm_e";
 266                         };
 267                 };
 268         };
 269 };
 270
 271 &ahb_sram {
 272         smp-sram@1ff80 {
 273                 compatible = "amlogic,meson8-smp-sram";
 274                 reg = <0x1ff80 0x8>;
 275         };
 276 };
 277
 278 &efuse {
 279         compatible = "amlogic,meson8-efuse";
 280         clocks = <&clkc CLKID_EFUSE>;
 281         clock-names = "core";
 282 };
 283
 284 &ethmac {
 285         clocks = <&clkc CLKID_ETH>;
 286         clock-names = "stmmaceth";
 287 };
 288
 289 &hwrng {
 290         compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
 291         clocks = <&clkc CLKID_RNG0>;
 292         clock-names = "core";
 293 };
 294
 295 &i2c_AO {
 296         clocks = <&clkc CLKID_CLK81>;
 297 };
 298
 299 &i2c_A {
 300         clocks = <&clkc CLKID_CLK81>;
 301 };
 302
 303 &i2c_B {
 304         clocks = <&clkc CLKID_CLK81>;
 305 };
 306
 307 &L2 {
 308         arm,data-latency = <3 3 3>;
 309         arm,tag-latency = <2 2 2>;
 310         arm,filter-ranges = <0x100000 0xc0000000>;
 311 };
 312
 313 &pwm_ab {
 314         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 315 };
 316
 317 &pwm_cd {
 318         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 319 };
 320
 321 &saradc {
 322         compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
 323         clocks = <&clkc CLKID_XTAL>,
 324                 <&clkc CLKID_SAR_ADC>,
 325                 <&clkc CLKID_SANA>;
 326         clock-names = "clkin", "core", "sana";
 327 };
 328
 329 &sdio {
 330         compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
 331         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 332         clock-names = "core", "clkin";
 333 };
 334
 335 &spifc {
 336         clocks = <&clkc CLKID_CLK81>;
 337 };
 338
 339 &uart_AO {
 340         clocks = <&clkc CLKID_CLK81>;
 341 };
 342
 343 &uart_A {
 344         clocks = <&clkc CLKID_CLK81>;
 345 };
 346
 347 &uart_B {
 348         clocks = <&clkc CLKID_CLK81>;
 349 };
 350
 351 &uart_C {
 352         clocks = <&clkc CLKID_CLK81>;
 353 };
 354
 355 &usb0 {
 356         compatible = "amlogic,meson8-usb", "snps,dwc2";
 357         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 358         clock-names = "otg";
 359 };
 360
 361 &usb1 {
 362         compatible = "amlogic,meson8-usb", "snps,dwc2";
 363         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 364         clock-names = "otg";
 365 };
 366
 367 &usb0_phy {
 368         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 369         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 370         clock-names = "usb_general", "usb";
 371 };
 372
 373 &usb1_phy {
 374         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 375         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 376         clock-names = "usb_general", "usb";
 377 };