arch/arm/boot/dts/ls1021a.dtsi

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54         compatible = "fsl,ls1021a";
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 crypto = &crypto;
  59                 ethernet0 = &enet0;
  60                 ethernet1 = &enet1;
  61                 ethernet2 = &enet2;
  62                 serial0 = &lpuart0;
  63                 serial1 = &lpuart1;
  64                 serial2 = &lpuart2;
  65                 serial3 = &lpuart3;
  66                 serial4 = &lpuart4;
  67                 serial5 = &lpuart5;
  68                 sysclk = &sysclk;
  69         };
  70
  71         cpus {
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74
  75                 cpu0: cpu@f00 {
  76                         compatible = "arm,cortex-a7";
  77                         device_type = "cpu";
  78                         reg = <0xf00>;
  79                         clocks = <&clockgen 1 0>;
  80                         #cooling-cells = <2>;
  81                 };
  82
  83                 cpu1: cpu@f01 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <0xf01>;
  87                         clocks = <&clockgen 1 0>;
  88                         #cooling-cells = <2>;
  89                 };
  90         };
  91
  92         memory {
  93                 device_type = "memory";
  94                 reg = <0x0 0x0 0x0 0x0>;
  95         };
  96
  97         sysclk: sysclk {
  98                 compatible = "fixed-clock";
  99                 #clock-cells = <0>;
 100                 clock-frequency = <100000000>;
 101                 clock-output-names = "sysclk";
 102         };
 103
 104         timer {
 105                 compatible = "arm,armv7-timer";
 106                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 107                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 108                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 109                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 110         };
 111
 112         pmu {
 113                 compatible = "arm,cortex-a7-pmu";
 114                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 115                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 116                 interrupt-affinity = <&cpu0>, <&cpu1>;
 117         };
 118
 119         reboot {
 120                 compatible = "syscon-reboot";
 121                 regmap = <&dcfg>;
 122                 offset = <0xb0>;
 123                 mask = <0x02>;
 124         };
 125
 126         soc {
 127                 compatible = "simple-bus";
 128                 #address-cells = <2>;
 129                 #size-cells = <2>;
 130                 device_type = "soc";
 131                 interrupt-parent = <&gic>;
 132                 ranges;
 133
 134                 ddr: memory-controller@1080000 {
 135                         compatible = "fsl,qoriq-memory-controller";
 136                         reg = <0x0 0x1080000 0x0 0x1000>;
 137                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 138                         big-endian;
 139                 };
 140
 141                 gic: interrupt-controller@1400000 {
 142                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
 143                         #interrupt-cells = <3>;
 144                         interrupt-controller;
 145                         reg = <0x0 0x1401000 0x0 0x1000>,
 146                               <0x0 0x1402000 0x0 0x2000>,
 147                               <0x0 0x1404000 0x0 0x2000>,
 148                               <0x0 0x1406000 0x0 0x2000>;
 149                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 150
 151                 };
 152
 153                 msi1: msi-controller@1570e00 {
 154                         compatible = "fsl,ls1021a-msi";
 155                         reg = <0x0 0x1570e00 0x0 0x8>;
 156                         msi-controller;
 157                         interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 158                 };
 159
 160                 msi2: msi-controller@1570e08 {
 161                         compatible = "fsl,ls1021a-msi";
 162                         reg = <0x0 0x1570e08 0x0 0x8>;
 163                         msi-controller;
 164                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 165                 };
 166
 167                 ifc: ifc@1530000 {
 168                         compatible = "fsl,ifc", "simple-bus";
 169                         reg = <0x0 0x1530000 0x0 0x10000>;
 170                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 171                 };
 172
 173                 dcfg: dcfg@1ee0000 {
 174                         compatible = "fsl,ls1021a-dcfg", "syscon";
 175                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 176                         big-endian;
 177                 };
 178
 179                 qspi: spi@1550000 {
 180                         compatible = "fsl,ls1021a-qspi";
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                         reg = <0x0 0x1550000 0x0 0x10000>,
 184                               <0x0 0x40000000 0x0 0x40000000>;
 185                         reg-names = "QuadSPI", "QuadSPI-memory";
 186                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 187                         clock-names = "qspi_en", "qspi";
 188                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 189                         big-endian;
 190                         status = "disabled";
 191                 };
 192
 193                 esdhc: esdhc@1560000 {
 194                         compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
 195                         reg = <0x0 0x1560000 0x0 0x10000>;
 196                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 197                         clock-frequency = <0>;
 198                         voltage-ranges = <1800 1800 3300 3300>;
 199                         sdhci,auto-cmd12;
 200                         big-endian;
 201                         bus-width = <4>;
 202                         status = "disabled";
 203                 };
 204
 205                 sata: sata@3200000 {
 206                         compatible = "fsl,ls1021a-ahci";
 207                         reg = <0x0 0x3200000 0x0 0x10000>,
 208                               <0x0 0x20220520 0x0 0x4>;
 209                         reg-names = "ahci", "sata-ecc";
 210                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 211                         clocks = <&clockgen 4 1>;
 212                         dma-coherent;
 213                         status = "disabled";
 214                 };
 215
 216                 scfg: scfg@1570000 {
 217                         compatible = "fsl,ls1021a-scfg", "syscon";
 218                         reg = <0x0 0x1570000 0x0 0x10000>;
 219                         big-endian;
 220                 };
 221
 222                 crypto: crypto@1700000 {
 223                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 224                         fsl,sec-era = <7>;
 225                         #address-cells = <1>;
 226                         #size-cells = <1>;
 227                         reg              = <0x0 0x1700000 0x0 0x100000>;
 228                         ranges           = <0x0 0x0 0x1700000 0x100000>;
 229                         interrupts       = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 230
 231                         sec_jr0: jr@10000 {
 232                                 compatible = "fsl,sec-v5.0-job-ring",
 233                                      "fsl,sec-v4.0-job-ring";
 234                                 reg = <0x10000 0x10000>;
 235                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 236                         };
 237
 238                         sec_jr1: jr@20000 {
 239                                 compatible = "fsl,sec-v5.0-job-ring",
 240                                      "fsl,sec-v4.0-job-ring";
 241                                 reg = <0x20000 0x10000>;
 242                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 243                         };
 244
 245                         sec_jr2: jr@30000 {
 246                                 compatible = "fsl,sec-v5.0-job-ring",
 247                                      "fsl,sec-v4.0-job-ring";
 248                                 reg = <0x30000 0x10000>;
 249                                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 250                         };
 251
 252                         sec_jr3: jr@40000 {
 253                                 compatible = "fsl,sec-v5.0-job-ring",
 254                                      "fsl,sec-v4.0-job-ring";
 255                                 reg = <0x40000 0x10000>;
 256                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 257                         };
 258
 259                 };
 260
 261                 clockgen: clocking@1ee1000 {
 262                         compatible = "fsl,ls1021a-clockgen";
 263                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 264                         #clock-cells = <2>;
 265                         clocks = <&sysclk>;
 266                 };
 267
 268                 tmu: tmu@1f00000 {
 269                         compatible = "fsl,qoriq-tmu";
 270                         reg = <0x0 0x1f00000 0x0 0x10000>;
 271                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 272                         fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
 273                         fsl,tmu-calibration = <0x00000000 0x0000000f
 274                                                0x00000001 0x00000017
 275                                                0x00000002 0x0000001e
 276                                                0x00000003 0x00000026
 277                                                0x00000004 0x0000002e
 278                                                0x00000005 0x00000035
 279                                                0x00000006 0x0000003d
 280                                                0x00000007 0x00000044
 281                                                0x00000008 0x0000004c
 282                                                0x00000009 0x00000053
 283                                                0x0000000a 0x0000005b
 284                                                0x0000000b 0x00000064
 285
 286                                                0x00010000 0x00000011
 287                                                0x00010001 0x0000001c
 288                                                0x00010002 0x00000024
 289                                                0x00010003 0x0000002b
 290                                                0x00010004 0x00000034
 291                                                0x00010005 0x00000039
 292                                                0x00010006 0x00000042
 293                                                0x00010007 0x0000004c
 294                                                0x00010008 0x00000051
 295                                                0x00010009 0x0000005a
 296                                                0x0001000a 0x00000063
 297
 298                                                0x00020000 0x00000013
 299                                                0x00020001 0x00000019
 300                                                0x00020002 0x00000024
 301                                                0x00020003 0x0000002c
 302                                                0x00020004 0x00000035
 303                                                0x00020005 0x0000003d
 304                                                0x00020006 0x00000046
 305                                                0x00020007 0x00000050
 306                                                0x00020008 0x00000059
 307
 308                                                0x00030000 0x00000002
 309                                                0x00030001 0x0000000d
 310                                                0x00030002 0x00000019
 311                                                0x00030003 0x00000024>;
 312                         #thermal-sensor-cells = <1>;
 313                 };
 314
 315                 thermal-zones {
 316                         cpu_thermal: cpu-thermal {
 317                                 polling-delay-passive = <1000>;
 318                                 polling-delay = <5000>;
 319
 320                                 thermal-sensors = <&tmu 0>;
 321
 322                                 trips {
 323                                         cpu_alert: cpu-alert {
 324                                                 temperature = <85000>;
 325                                                 hysteresis = <2000>;
 326                                                 type = "passive";
 327                                         };
 328                                         cpu_crit: cpu-crit {
 329                                                 temperature = <95000>;
 330                                                 hysteresis = <2000>;
 331                                                 type = "critical";
 332                                         };
 333                                 };
 334
 335                                 cooling-maps {
 336                                         map0 {
 337                                                 trip = <&cpu_alert>;
 338                                                 cooling-device =
 339                                                         <&cpu0 THERMAL_NO_LIMIT
 340                                                         THERMAL_NO_LIMIT>,
 341                                                         <&cpu1 THERMAL_NO_LIMIT
 342                                                         THERMAL_NO_LIMIT>;
 343                                         };
 344                                 };
 345                         };
 346                 };
 347
 348                 dspi0: spi@2100000 {
 349                         compatible = "fsl,ls1021a-v1.0-dspi";
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         reg = <0x0 0x2100000 0x0 0x10000>;
 353                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 354                         clock-names = "dspi";
 355                         clocks = <&clockgen 4 1>;
 356                         spi-num-chipselects = <6>;
 357                         big-endian;
 358                         status = "disabled";
 359                 };
 360
 361                 dspi1: spi@2110000 {
 362                         compatible = "fsl,ls1021a-v1.0-dspi";
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         reg = <0x0 0x2110000 0x0 0x10000>;
 366                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 367                         clock-names = "dspi";
 368                         clocks = <&clockgen 4 1>;
 369                         spi-num-chipselects = <6>;
 370                         big-endian;
 371                         status = "disabled";
 372                 };
 373
 374                 i2c0: i2c@2180000 {
 375                         compatible = "fsl,vf610-i2c";
 376                         #address-cells = <1>;
 377                         #size-cells = <0>;
 378                         reg = <0x0 0x2180000 0x0 0x10000>;
 379                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 380                         clock-names = "i2c";
 381                         clocks = <&clockgen 4 1>;
 382                         dma-names = "tx", "rx";
 383                         dmas = <&edma0 1 39>, <&edma0 1 38>;
 384                         status = "disabled";
 385                 };
 386
 387                 i2c1: i2c@2190000 {
 388                         compatible = "fsl,vf610-i2c";
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         reg = <0x0 0x2190000 0x0 0x10000>;
 392                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 393                         clock-names = "i2c";
 394                         clocks = <&clockgen 4 1>;
 395                         dma-names = "tx", "rx";
 396                         dmas = <&edma0 1 37>, <&edma0 1 36>;
 397                         status = "disabled";
 398                 };
 399
 400                 i2c2: i2c@21a0000 {
 401                         compatible = "fsl,vf610-i2c";
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         reg = <0x0 0x21a0000 0x0 0x10000>;
 405                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 406                         clock-names = "i2c";
 407                         clocks = <&clockgen 4 1>;
 408                         dma-names = "tx", "rx";
 409                         dmas = <&edma0 1 35>, <&edma0 1 34>;
 410                         status = "disabled";
 411                 };
 412
 413                 uart0: serial@21c0500 {
 414                         compatible = "fsl,16550-FIFO64", "ns16550a";
 415                         reg = <0x0 0x21c0500 0x0 0x100>;
 416                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 417                         clock-frequency = <0>;
 418                         fifo-size = <15>;
 419                         status = "disabled";
 420                 };
 421
 422                 uart1: serial@21c0600 {
 423                         compatible = "fsl,16550-FIFO64", "ns16550a";
 424                         reg = <0x0 0x21c0600 0x0 0x100>;
 425                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 426                         clock-frequency = <0>;
 427                         fifo-size = <15>;
 428                         status = "disabled";
 429                 };
 430
 431                 uart2: serial@21d0500 {
 432                         compatible = "fsl,16550-FIFO64", "ns16550a";
 433                         reg = <0x0 0x21d0500 0x0 0x100>;
 434                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 435                         clock-frequency = <0>;
 436                         fifo-size = <15>;
 437                         status = "disabled";
 438                 };
 439
 440                 uart3: serial@21d0600 {
 441                         compatible = "fsl,16550-FIFO64", "ns16550a";
 442                         reg = <0x0 0x21d0600 0x0 0x100>;
 443                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 444                         clock-frequency = <0>;
 445                         fifo-size = <15>;
 446                         status = "disabled";
 447                 };
 448
 449                 counter0: counter@29d0000 {
 450                         compatible = "fsl,ftm-quaddec";
 451                         reg = <0x0 0x29d0000 0x0 0x10000>;
 452                         big-endian;
 453                         status = "disabled";
 454                 };
 455
 456                 counter1: counter@29e0000 {
 457                         compatible = "fsl,ftm-quaddec";
 458                         reg = <0x0 0x29e0000 0x0 0x10000>;
 459                         big-endian;
 460                         status = "disabled";
 461                 };
 462
 463                 counter2: counter@29f0000 {
 464                         compatible = "fsl,ftm-quaddec";
 465                         reg = <0x0 0x29f0000 0x0 0x10000>;
 466                         big-endian;
 467                         status = "disabled";
 468                 };
 469
 470                 counter3: counter@2a00000 {
 471                         compatible = "fsl,ftm-quaddec";
 472                         reg = <0x0 0x2a00000 0x0 0x10000>;
 473                         big-endian;
 474                         status = "disabled";
 475                 };
 476
 477                 gpio0: gpio@2300000 {
 478                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 479                         reg = <0x0 0x2300000 0x0 0x10000>;
 480                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 481                         gpio-controller;
 482                         #gpio-cells = <2>;
 483                         interrupt-controller;
 484                         #interrupt-cells = <2>;
 485                 };
 486
 487                 gpio1: gpio@2310000 {
 488                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 489                         reg = <0x0 0x2310000 0x0 0x10000>;
 490                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 491                         gpio-controller;
 492                         #gpio-cells = <2>;
 493                         interrupt-controller;
 494                         #interrupt-cells = <2>;
 495                 };
 496
 497                 gpio2: gpio@2320000 {
 498                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 499                         reg = <0x0 0x2320000 0x0 0x10000>;
 500                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 501                         gpio-controller;
 502                         #gpio-cells = <2>;
 503                         interrupt-controller;
 504                         #interrupt-cells = <2>;
 505                 };
 506
 507                 gpio3: gpio@2330000 {
 508                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 509                         reg = <0x0 0x2330000 0x0 0x10000>;
 510                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 511                         gpio-controller;
 512                         #gpio-cells = <2>;
 513                         interrupt-controller;
 514                         #interrupt-cells = <2>;
 515                 };
 516
 517                 lpuart0: serial@2950000 {
 518                         compatible = "fsl,ls1021a-lpuart";
 519                         reg = <0x0 0x2950000 0x0 0x1000>;
 520                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 521                         clocks = <&sysclk>;
 522                         clock-names = "ipg";
 523                         status = "disabled";
 524                 };
 525
 526                 lpuart1: serial@2960000 {
 527                         compatible = "fsl,ls1021a-lpuart";
 528                         reg = <0x0 0x2960000 0x0 0x1000>;
 529                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 530                         clocks = <&clockgen 4 1>;
 531                         clock-names = "ipg";
 532                         status = "disabled";
 533                 };
 534
 535                 lpuart2: serial@2970000 {
 536                         compatible = "fsl,ls1021a-lpuart";
 537                         reg = <0x0 0x2970000 0x0 0x1000>;
 538                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 539                         clocks = <&clockgen 4 1>;
 540                         clock-names = "ipg";
 541                         status = "disabled";
 542                 };
 543
 544                 lpuart3: serial@2980000 {
 545                         compatible = "fsl,ls1021a-lpuart";
 546                         reg = <0x0 0x2980000 0x0 0x1000>;
 547                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 548                         clocks = <&clockgen 4 1>;
 549                         clock-names = "ipg";
 550                         status = "disabled";
 551                 };
 552
 553                 lpuart4: serial@2990000 {
 554                         compatible = "fsl,ls1021a-lpuart";
 555                         reg = <0x0 0x2990000 0x0 0x1000>;
 556                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 557                         clocks = <&clockgen 4 1>;
 558                         clock-names = "ipg";
 559                         status = "disabled";
 560                 };
 561
 562                 lpuart5: serial@29a0000 {
 563                         compatible = "fsl,ls1021a-lpuart";
 564                         reg = <0x0 0x29a0000 0x0 0x1000>;
 565                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 566                         clocks = <&clockgen 4 1>;
 567                         clock-names = "ipg";
 568                         status = "disabled";
 569                 };
 570
 571                 pwm0: pwm@29d0000 {
 572                         compatible = "fsl,vf610-ftm-pwm";
 573                         #pwm-cells = <3>;
 574                         reg = <0x0 0x29d0000 0x0 0x10000>;
 575                         clock-names = "ftm_sys", "ftm_ext",
 576                                 "ftm_fix", "ftm_cnt_clk_en";
 577                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 578                                 <&clockgen 4 1>, <&clockgen 4 1>;
 579                         big-endian;
 580                         status = "disabled";
 581                 };
 582
 583                 pwm1: pwm@29e0000 {
 584                         compatible = "fsl,vf610-ftm-pwm";
 585                         #pwm-cells = <3>;
 586                         reg = <0x0 0x29e0000 0x0 0x10000>;
 587                         clock-names = "ftm_sys", "ftm_ext",
 588                                 "ftm_fix", "ftm_cnt_clk_en";
 589                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 590                                 <&clockgen 4 1>, <&clockgen 4 1>;
 591                         big-endian;
 592                         status = "disabled";
 593                 };
 594
 595                 pwm2: pwm@29f0000 {
 596                         compatible = "fsl,vf610-ftm-pwm";
 597                         #pwm-cells = <3>;
 598                         reg = <0x0 0x29f0000 0x0 0x10000>;
 599                         clock-names = "ftm_sys", "ftm_ext",
 600                                 "ftm_fix", "ftm_cnt_clk_en";
 601                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 602                                 <&clockgen 4 1>, <&clockgen 4 1>;
 603                         big-endian;
 604                         status = "disabled";
 605                 };
 606
 607                 pwm3: pwm@2a00000 {
 608                         compatible = "fsl,vf610-ftm-pwm";
 609                         #pwm-cells = <3>;
 610                         reg = <0x0 0x2a00000 0x0 0x10000>;
 611                         clock-names = "ftm_sys", "ftm_ext",
 612                                 "ftm_fix", "ftm_cnt_clk_en";
 613                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 614                                 <&clockgen 4 1>, <&clockgen 4 1>;
 615                         big-endian;
 616                         status = "disabled";
 617                 };
 618
 619                 pwm4: pwm@2a10000 {
 620                         compatible = "fsl,vf610-ftm-pwm";
 621                         #pwm-cells = <3>;
 622                         reg = <0x0 0x2a10000 0x0 0x10000>;
 623                         clock-names = "ftm_sys", "ftm_ext",
 624                                 "ftm_fix", "ftm_cnt_clk_en";
 625                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 626                                 <&clockgen 4 1>, <&clockgen 4 1>;
 627                         big-endian;
 628                         status = "disabled";
 629                 };
 630
 631                 pwm5: pwm@2a20000 {
 632                         compatible = "fsl,vf610-ftm-pwm";
 633                         #pwm-cells = <3>;
 634                         reg = <0x0 0x2a20000 0x0 0x10000>;
 635                         clock-names = "ftm_sys", "ftm_ext",
 636                                 "ftm_fix", "ftm_cnt_clk_en";
 637                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 638                                 <&clockgen 4 1>, <&clockgen 4 1>;
 639                         big-endian;
 640                         status = "disabled";
 641                 };
 642
 643                 pwm6: pwm@2a30000 {
 644                         compatible = "fsl,vf610-ftm-pwm";
 645                         #pwm-cells = <3>;
 646                         reg = <0x0 0x2a30000 0x0 0x10000>;
 647                         clock-names = "ftm_sys", "ftm_ext",
 648                                 "ftm_fix", "ftm_cnt_clk_en";
 649                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 650                                 <&clockgen 4 1>, <&clockgen 4 1>;
 651                         big-endian;
 652                         status = "disabled";
 653                 };
 654
 655                 pwm7: pwm@2a40000 {
 656                         compatible = "fsl,vf610-ftm-pwm";
 657                         #pwm-cells = <3>;
 658                         reg = <0x0 0x2a40000 0x0 0x10000>;
 659                         clock-names = "ftm_sys", "ftm_ext",
 660                                 "ftm_fix", "ftm_cnt_clk_en";
 661                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 662                                 <&clockgen 4 1>, <&clockgen 4 1>;
 663                         big-endian;
 664                         status = "disabled";
 665                 };
 666
 667                 wdog0: watchdog@2ad0000 {
 668                         compatible = "fsl,imx21-wdt";
 669                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 670                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 671                         clocks = <&clockgen 4 1>;
 672                         clock-names = "wdog-en";
 673                         big-endian;
 674                 };
 675
 676                 sai1: sai@2b50000 {
 677                         #sound-dai-cells = <0>;
 678                         compatible = "fsl,vf610-sai";
 679                         reg = <0x0 0x2b50000 0x0 0x10000>;
 680                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 681                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 682                                  <&clockgen 4 1>, <&clockgen 4 1>;
 683                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 684                         dma-names = "tx", "rx";
 685                         dmas = <&edma0 1 47>,
 686                                <&edma0 1 46>;
 687                         status = "disabled";
 688                 };
 689
 690                 sai2: sai@2b60000 {
 691                         #sound-dai-cells = <0>;
 692                         compatible = "fsl,vf610-sai";
 693                         reg = <0x0 0x2b60000 0x0 0x10000>;
 694                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 695                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 696                                  <&clockgen 4 1>, <&clockgen 4 1>;
 697                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 698                         dma-names = "tx", "rx";
 699                         dmas = <&edma0 1 45>,
 700                                <&edma0 1 44>;
 701                         status = "disabled";
 702                 };
 703
 704                 edma0: edma@2c00000 {
 705                         #dma-cells = <2>;
 706                         compatible = "fsl,vf610-edma";
 707                         reg = <0x0 0x2c00000 0x0 0x10000>,
 708                               <0x0 0x2c10000 0x0 0x10000>,
 709                               <0x0 0x2c20000 0x0 0x10000>;
 710                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 711                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 712                         interrupt-names = "edma-tx", "edma-err";
 713                         dma-channels = <32>;
 714                         big-endian;
 715                         clock-names = "dmamux0", "dmamux1";
 716                         clocks = <&clockgen 4 1>,
 717                                  <&clockgen 4 1>;
 718                 };
 719
 720                 dcu: dcu@2ce0000 {
 721                         compatible = "fsl,ls1021a-dcu";
 722                         reg = <0x0 0x2ce0000 0x0 0x10000>;
 723                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 724                         clocks = <&clockgen 4 0>,
 725                                 <&clockgen 4 0>;
 726                         clock-names = "dcu", "pix";
 727                         big-endian;
 728                         status = "disabled";
 729                 };
 730
 731                 mdio0: mdio@2d24000 {
 732                         compatible = "gianfar";
 733                         device_type = "mdio";
 734                         #address-cells = <1>;
 735                         #size-cells = <0>;
 736                         reg = <0x0 0x2d24000 0x0 0x4000>,
 737                               <0x0 0x2d10030 0x0 0x4>;
 738                 };
 739
 740                 ptp_clock@2d10e00 {
 741                         compatible = "fsl,etsec-ptp";
 742                         reg = <0x0 0x2d10e00 0x0 0xb0>;
 743                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 744                         fsl,tclk-period = <5>;
 745                         fsl,tmr-prsc    = <2>;
 746                         fsl,tmr-add     = <0xaaaaaaab>;
 747                         fsl,tmr-fiper1  = <999999995>;
 748                         fsl,tmr-fiper2  = <99990>;
 749                         fsl,max-adj     = <499999999>;
 750                         fsl,extts-fifo;
 751                 };
 752
 753                 enet0: ethernet@2d10000 {
 754                         compatible = "fsl,etsec2";
 755                         device_type = "network";
 756                         #address-cells = <2>;
 757                         #size-cells = <2>;
 758                         interrupt-parent = <&gic>;
 759                         model = "eTSEC";
 760                         fsl,magic-packet;
 761                         ranges;
 762                         dma-coherent;
 763
 764                         queue-group@2d10000 {
 765                                 #address-cells = <2>;
 766                                 #size-cells = <2>;
 767                                 reg = <0x0 0x2d10000 0x0 0x1000>;
 768                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 769                                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 770                                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 771                         };
 772
 773                         queue-group@2d14000  {
 774                                 #address-cells = <2>;
 775                                 #size-cells = <2>;
 776                                 reg = <0x0 0x2d14000 0x0 0x1000>;
 777                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 778                                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 779                                         <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 780                         };
 781                 };
 782
 783                 enet1: ethernet@2d50000 {
 784                         compatible = "fsl,etsec2";
 785                         device_type = "network";
 786                         #address-cells = <2>;
 787                         #size-cells = <2>;
 788                         interrupt-parent = <&gic>;
 789                         model = "eTSEC";
 790                         ranges;
 791                         dma-coherent;
 792
 793                         queue-group@2d50000  {
 794                                 #address-cells = <2>;
 795                                 #size-cells = <2>;
 796                                 reg = <0x0 0x2d50000 0x0 0x1000>;
 797                                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 798                                         <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 799                                         <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 800                         };
 801
 802                         queue-group@2d54000  {
 803                                 #address-cells = <2>;
 804                                 #size-cells = <2>;
 805                                 reg = <0x0 0x2d54000 0x0 0x1000>;
 806                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 807                                         <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 808                                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 809                         };
 810                 };
 811
 812                 enet2: ethernet@2d90000 {
 813                         compatible = "fsl,etsec2";
 814                         device_type = "network";
 815                         #address-cells = <2>;
 816                         #size-cells = <2>;
 817                         interrupt-parent = <&gic>;
 818                         model = "eTSEC";
 819                         ranges;
 820                         dma-coherent;
 821
 822                         queue-group@2d90000  {
 823                                 #address-cells = <2>;
 824                                 #size-cells = <2>;
 825                                 reg = <0x0 0x2d90000 0x0 0x1000>;
 826                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 827                                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 828                                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 829                         };
 830
 831                         queue-group@2d94000  {
 832                                 #address-cells = <2>;
 833                                 #size-cells = <2>;
 834                                 reg = <0x0 0x2d94000 0x0 0x1000>;
 835                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 836                                         <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 837                                         <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 838                         };
 839                 };
 840
 841                 usb2: usb@8600000 {
 842                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 843                         reg = <0x0 0x8600000 0x0 0x1000>;
 844                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 845                         dr_mode = "host";
 846                         phy_type = "ulpi";
 847                 };
 848
 849                 usb3: usb3@3100000 {
 850                         compatible = "snps,dwc3";
 851                         reg = <0x0 0x3100000 0x0 0x10000>;
 852                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 853                         dr_mode = "host";
 854                         snps,quirk-frame-length-adjustment = <0x20>;
 855                         snps,dis_rxdet_inp3_quirk;
 856                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 857                 };
 858
 859                 pcie@3400000 {
 860                         compatible = "fsl,ls1021a-pcie";
 861                         reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 862                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 863                         reg-names = "regs", "config";
 864                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 865                         fsl,pcie-scfg = <&scfg 0>;
 866                         #address-cells = <3>;
 867                         #size-cells = <2>;
 868                         device_type = "pci";
 869                         num-lanes = <4>;
 870                         num-viewport = <6>;
 871                         bus-range = <0x0 0xff>;
 872                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 873                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 874                         msi-parent = <&msi1>, <&msi2>;
 875                         #interrupt-cells = <1>;
 876                         interrupt-map-mask = <0 0 0 7>;
 877                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
 878                                         <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 879                                         <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 880                                         <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 881                         status = "disabled";
 882                 };
 883
 884                 pcie@3500000 {
 885                         compatible = "fsl,ls1021a-pcie";
 886                         reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
 887                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 888                         reg-names = "regs", "config";
 889                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 890                         fsl,pcie-scfg = <&scfg 1>;
 891                         #address-cells = <3>;
 892                         #size-cells = <2>;
 893                         device_type = "pci";
 894                         num-lanes = <4>;
 895                         num-viewport = <6>;
 896                         bus-range = <0x0 0xff>;
 897                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 898                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 899                         msi-parent = <&msi1>, <&msi2>;
 900                         #interrupt-cells = <1>;
 901                         interrupt-map-mask = <0 0 0 7>;
 902                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
 903                                         <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 904                                         <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 905                                         <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 906                         status = "disabled";
 907                 };
 908
 909                 can0: can@2a70000 {
 910                         compatible = "fsl,ls1021ar2-flexcan";
 911                         reg = <0x0 0x2a70000 0x0 0x1000>;
 912                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 913                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 914                         clock-names = "ipg", "per";
 915                         big-endian;
 916                 };
 917
 918                 can1: can@2a80000 {
 919                         compatible = "fsl,ls1021ar2-flexcan";
 920                         reg = <0x0 0x2a80000 0x0 0x1000>;
 921                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 922                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 923                         clock-names = "ipg", "per";
 924                         big-endian;
 925                 };
 926
 927                 can2: can@2a90000 {
 928                         compatible = "fsl,ls1021ar2-flexcan";
 929                         reg = <0x0 0x2a90000 0x0 0x1000>;
 930                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 931                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 932                         clock-names = "ipg", "per";
 933                         big-endian;
 934                 };
 935
 936                 can3: can@2aa0000 {
 937                         compatible = "fsl,ls1021ar2-flexcan";
 938                         reg = <0x0 0x2aa0000 0x0 0x1000>;
 939                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 940                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 941                         clock-names = "ipg", "per";
 942                         big-endian;
 943                 };
 944
 945                 ocram1: sram@10000000 {
 946                         compatible = "mmio-sram";
 947                         reg = <0x0 0x10000000 0x0 0x10000>;
 948                         #address-cells = <1>;
 949                         #size-cells = <1>;
 950                         ranges = <0x0 0x0 0x10000000 0x10000>;
 951                 };
 952
 953                 ocram2: sram@10010000 {
 954                         compatible = "mmio-sram";
 955                         reg = <0x0 0x10010000 0x0 0x10000>;
 956                         #address-cells = <1>;
 957                         #size-cells = <1>;
 958                         ranges = <0x0 0x0 0x10010000 0x10000>;
 959                 };
 960
 961                 qdma: dma-controller@8390000 {
 962                         compatible = "fsl,ls1021a-qdma";
 963                         reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
 964                               <0x0 0x8389000 0x0 0x1000>, /* Status regs */
 965                               <0x0 0x838a000 0x0 0x2000>; /* Block regs */
 966                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 967                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 968                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 969                         interrupt-names = "qdma-error",
 970                                 "qdma-queue0", "qdma-queue1";
 971                         dma-channels = <8>;
 972                         block-number = <1>;
 973                         block-offset = <0x1000>;
 974                         fsl,dma-queues = <2>;
 975                         status-sizes = <64>;
 976                         queue-sizes = <64 64>;
 977                         big-endian;
 978                 };
 979
 980         };
 981 };