Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / ls1021a.dtsi
1 /*
2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This file is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of
12  *     the License, or (at your option) any later version.
13  *
14  *     This file is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  *     You should have received a copy of the GNU General Public
20  *     License along with this file; if not, write to the Free
21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22  *     MA 02110-1301 USA
23  *
24  * Or, alternatively,
25  *
26  *  b) Permission is hereby granted, free of charge, to any person
27  *     obtaining a copy of this software and associated documentation
28  *     files (the "Software"), to deal in the Software without
29  *     restriction, including without limitation the rights to use,
30  *     copy, modify, merge, publish, distribute, sublicense, and/or
31  *     sell copies of the Software, and to permit persons to whom the
32  *     Software is furnished to do so, subject to the following
33  *     conditions:
34  *
35  *     The above copyright notice and this permission notice shall be
36  *     included in all copies or substantial portions of the Software.
37  *
38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45  *     OTHER DEALINGS IN THE SOFTWARE.
46  */
47
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/thermal/thermal.h>
50
51 / {
52         #address-cells = <2>;
53         #size-cells = <2>;
54         compatible = "fsl,ls1021a";
55         interrupt-parent = <&gic>;
56
57         aliases {
58                 crypto = &crypto;
59                 ethernet0 = &enet0;
60                 ethernet1 = &enet1;
61                 ethernet2 = &enet2;
62                 serial0 = &lpuart0;
63                 serial1 = &lpuart1;
64                 serial2 = &lpuart2;
65                 serial3 = &lpuart3;
66                 serial4 = &lpuart4;
67                 serial5 = &lpuart5;
68                 sysclk = &sysclk;
69         };
70
71         cpus {
72                 #address-cells = <1>;
73                 #size-cells = <0>;
74
75                 cpu0: cpu@f00 {
76                         compatible = "arm,cortex-a7";
77                         device_type = "cpu";
78                         reg = <0xf00>;
79                         clocks = <&clockgen 1 0>;
80                         #cooling-cells = <2>;
81                 };
82
83                 cpu1: cpu@f01 {
84                         compatible = "arm,cortex-a7";
85                         device_type = "cpu";
86                         reg = <0xf01>;
87                         clocks = <&clockgen 1 0>;
88                         #cooling-cells = <2>;
89                 };
90         };
91
92         memory {
93                 device_type = "memory";
94                 reg = <0x0 0x0 0x0 0x0>;
95         };
96
97         sysclk: sysclk {
98                 compatible = "fixed-clock";
99                 #clock-cells = <0>;
100                 clock-frequency = <100000000>;
101                 clock-output-names = "sysclk";
102         };
103
104         timer {
105                 compatible = "arm,armv7-timer";
106                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
107                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
108                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
109                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
110         };
111
112         pmu {
113                 compatible = "arm,cortex-a7-pmu";
114                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
115                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
116                 interrupt-affinity = <&cpu0>, <&cpu1>;
117         };
118
119         reboot {
120                 compatible = "syscon-reboot";
121                 regmap = <&dcfg>;
122                 offset = <0xb0>;
123                 mask = <0x02>;
124         };
125
126         soc {
127                 compatible = "simple-bus";
128                 #address-cells = <2>;
129                 #size-cells = <2>;
130                 device_type = "soc";
131                 interrupt-parent = <&gic>;
132                 ranges;
133
134                 ddr: memory-controller@1080000 {
135                         compatible = "fsl,qoriq-memory-controller";
136                         reg = <0x0 0x1080000 0x0 0x1000>;
137                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
138                         big-endian;
139                 };
140
141                 gic: interrupt-controller@1400000 {
142                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
143                         #interrupt-cells = <3>;
144                         interrupt-controller;
145                         reg = <0x0 0x1401000 0x0 0x1000>,
146                               <0x0 0x1402000 0x0 0x2000>,
147                               <0x0 0x1404000 0x0 0x2000>,
148                               <0x0 0x1406000 0x0 0x2000>;
149                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
150
151                 };
152
153                 msi1: msi-controller@1570e00 {
154                         compatible = "fsl,ls1021a-msi";
155                         reg = <0x0 0x1570e00 0x0 0x8>;
156                         msi-controller;
157                         interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
158                 };
159
160                 msi2: msi-controller@1570e08 {
161                         compatible = "fsl,ls1021a-msi";
162                         reg = <0x0 0x1570e08 0x0 0x8>;
163                         msi-controller;
164                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
165                 };
166
167                 ifc: ifc@1530000 {
168                         compatible = "fsl,ifc", "simple-bus";
169                         reg = <0x0 0x1530000 0x0 0x10000>;
170                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
171                 };
172
173                 dcfg: dcfg@1ee0000 {
174                         compatible = "fsl,ls1021a-dcfg", "syscon";
175                         reg = <0x0 0x1ee0000 0x0 0x10000>;
176                         big-endian;
177                 };
178
179                 qspi: spi@1550000 {
180                         compatible = "fsl,ls1021a-qspi";
181                         #address-cells = <1>;
182                         #size-cells = <0>;
183                         reg = <0x0 0x1550000 0x0 0x10000>,
184                               <0x0 0x40000000 0x0 0x40000000>;
185                         reg-names = "QuadSPI", "QuadSPI-memory";
186                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
187                         clock-names = "qspi_en", "qspi";
188                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
189                         status = "disabled";
190                 };
191
192                 esdhc: esdhc@1560000 {
193                         compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
194                         reg = <0x0 0x1560000 0x0 0x10000>;
195                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
196                         clock-frequency = <0>;
197                         voltage-ranges = <1800 1800 3300 3300>;
198                         sdhci,auto-cmd12;
199                         big-endian;
200                         bus-width = <4>;
201                         status = "disabled";
202                 };
203
204                 sata: sata@3200000 {
205                         compatible = "fsl,ls1021a-ahci";
206                         reg = <0x0 0x3200000 0x0 0x10000>,
207                               <0x0 0x20220520 0x0 0x4>;
208                         reg-names = "ahci", "sata-ecc";
209                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
210                         clocks = <&clockgen 4 1>;
211                         dma-coherent;
212                         status = "disabled";
213                 };
214
215                 scfg: scfg@1570000 {
216                         compatible = "fsl,ls1021a-scfg", "syscon";
217                         reg = <0x0 0x1570000 0x0 0x10000>;
218                         big-endian;
219                 };
220
221                 crypto: crypto@1700000 {
222                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
223                         fsl,sec-era = <7>;
224                         #address-cells = <1>;
225                         #size-cells = <1>;
226                         reg              = <0x0 0x1700000 0x0 0x100000>;
227                         ranges           = <0x0 0x0 0x1700000 0x100000>;
228                         interrupts       = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
229
230                         sec_jr0: jr@10000 {
231                                 compatible = "fsl,sec-v5.0-job-ring",
232                                      "fsl,sec-v4.0-job-ring";
233                                 reg = <0x10000 0x10000>;
234                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
235                         };
236
237                         sec_jr1: jr@20000 {
238                                 compatible = "fsl,sec-v5.0-job-ring",
239                                      "fsl,sec-v4.0-job-ring";
240                                 reg = <0x20000 0x10000>;
241                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
242                         };
243
244                         sec_jr2: jr@30000 {
245                                 compatible = "fsl,sec-v5.0-job-ring",
246                                      "fsl,sec-v4.0-job-ring";
247                                 reg = <0x30000 0x10000>;
248                                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
249                         };
250
251                         sec_jr3: jr@40000 {
252                                 compatible = "fsl,sec-v5.0-job-ring",
253                                      "fsl,sec-v4.0-job-ring";
254                                 reg = <0x40000 0x10000>;
255                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
256                         };
257
258                 };
259
260                 clockgen: clocking@1ee1000 {
261                         compatible = "fsl,ls1021a-clockgen";
262                         reg = <0x0 0x1ee1000 0x0 0x1000>;
263                         #clock-cells = <2>;
264                         clocks = <&sysclk>;
265                 };
266
267                 tmu: tmu@1f00000 {
268                         compatible = "fsl,qoriq-tmu";
269                         reg = <0x0 0x1f00000 0x0 0x10000>;
270                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
271                         fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
272                         fsl,tmu-calibration = <0x00000000 0x0000000f
273                                                0x00000001 0x00000017
274                                                0x00000002 0x0000001e
275                                                0x00000003 0x00000026
276                                                0x00000004 0x0000002e
277                                                0x00000005 0x00000035
278                                                0x00000006 0x0000003d
279                                                0x00000007 0x00000044
280                                                0x00000008 0x0000004c
281                                                0x00000009 0x00000053
282                                                0x0000000a 0x0000005b
283                                                0x0000000b 0x00000064
284
285                                                0x00010000 0x00000011
286                                                0x00010001 0x0000001c
287                                                0x00010002 0x00000024
288                                                0x00010003 0x0000002b
289                                                0x00010004 0x00000034
290                                                0x00010005 0x00000039
291                                                0x00010006 0x00000042
292                                                0x00010007 0x0000004c
293                                                0x00010008 0x00000051
294                                                0x00010009 0x0000005a
295                                                0x0001000a 0x00000063
296
297                                                0x00020000 0x00000013
298                                                0x00020001 0x00000019
299                                                0x00020002 0x00000024
300                                                0x00020003 0x0000002c
301                                                0x00020004 0x00000035
302                                                0x00020005 0x0000003d
303                                                0x00020006 0x00000046
304                                                0x00020007 0x00000050
305                                                0x00020008 0x00000059
306
307                                                0x00030000 0x00000002
308                                                0x00030001 0x0000000d
309                                                0x00030002 0x00000019
310                                                0x00030003 0x00000024>;
311                         #thermal-sensor-cells = <1>;
312                 };
313
314                 thermal-zones {
315                         cpu_thermal: cpu-thermal {
316                                 polling-delay-passive = <1000>;
317                                 polling-delay = <5000>;
318
319                                 thermal-sensors = <&tmu 0>;
320
321                                 trips {
322                                         cpu_alert: cpu-alert {
323                                                 temperature = <85000>;
324                                                 hysteresis = <2000>;
325                                                 type = "passive";
326                                         };
327                                         cpu_crit: cpu-crit {
328                                                 temperature = <95000>;
329                                                 hysteresis = <2000>;
330                                                 type = "critical";
331                                         };
332                                 };
333
334                                 cooling-maps {
335                                         map0 {
336                                                 trip = <&cpu_alert>;
337                                                 cooling-device =
338                                                         <&cpu0 THERMAL_NO_LIMIT
339                                                         THERMAL_NO_LIMIT>,
340                                                         <&cpu1 THERMAL_NO_LIMIT
341                                                         THERMAL_NO_LIMIT>;
342                                         };
343                                 };
344                         };
345                 };
346
347                 dspi0: spi@2100000 {
348                         compatible = "fsl,ls1021a-v1.0-dspi";
349                         #address-cells = <1>;
350                         #size-cells = <0>;
351                         reg = <0x0 0x2100000 0x0 0x10000>;
352                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
353                         clock-names = "dspi";
354                         clocks = <&clockgen 4 1>;
355                         spi-num-chipselects = <6>;
356                         big-endian;
357                         status = "disabled";
358                 };
359
360                 dspi1: spi@2110000 {
361                         compatible = "fsl,ls1021a-v1.0-dspi";
362                         #address-cells = <1>;
363                         #size-cells = <0>;
364                         reg = <0x0 0x2110000 0x0 0x10000>;
365                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
366                         clock-names = "dspi";
367                         clocks = <&clockgen 4 1>;
368                         spi-num-chipselects = <6>;
369                         big-endian;
370                         status = "disabled";
371                 };
372
373                 i2c0: i2c@2180000 {
374                         compatible = "fsl,vf610-i2c";
375                         #address-cells = <1>;
376                         #size-cells = <0>;
377                         reg = <0x0 0x2180000 0x0 0x10000>;
378                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
379                         clock-names = "i2c";
380                         clocks = <&clockgen 4 1>;
381                         dma-names = "tx", "rx";
382                         dmas = <&edma0 1 39>, <&edma0 1 38>;
383                         status = "disabled";
384                 };
385
386                 i2c1: i2c@2190000 {
387                         compatible = "fsl,vf610-i2c";
388                         #address-cells = <1>;
389                         #size-cells = <0>;
390                         reg = <0x0 0x2190000 0x0 0x10000>;
391                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
392                         clock-names = "i2c";
393                         clocks = <&clockgen 4 1>;
394                         dma-names = "tx", "rx";
395                         dmas = <&edma0 1 37>, <&edma0 1 36>;
396                         status = "disabled";
397                 };
398
399                 i2c2: i2c@21a0000 {
400                         compatible = "fsl,vf610-i2c";
401                         #address-cells = <1>;
402                         #size-cells = <0>;
403                         reg = <0x0 0x21a0000 0x0 0x10000>;
404                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
405                         clock-names = "i2c";
406                         clocks = <&clockgen 4 1>;
407                         dma-names = "tx", "rx";
408                         dmas = <&edma0 1 35>, <&edma0 1 34>;
409                         status = "disabled";
410                 };
411
412                 uart0: serial@21c0500 {
413                         compatible = "fsl,16550-FIFO64", "ns16550a";
414                         reg = <0x0 0x21c0500 0x0 0x100>;
415                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
416                         clock-frequency = <0>;
417                         fifo-size = <15>;
418                         status = "disabled";
419                 };
420
421                 uart1: serial@21c0600 {
422                         compatible = "fsl,16550-FIFO64", "ns16550a";
423                         reg = <0x0 0x21c0600 0x0 0x100>;
424                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
425                         clock-frequency = <0>;
426                         fifo-size = <15>;
427                         status = "disabled";
428                 };
429
430                 uart2: serial@21d0500 {
431                         compatible = "fsl,16550-FIFO64", "ns16550a";
432                         reg = <0x0 0x21d0500 0x0 0x100>;
433                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
434                         clock-frequency = <0>;
435                         fifo-size = <15>;
436                         status = "disabled";
437                 };
438
439                 uart3: serial@21d0600 {
440                         compatible = "fsl,16550-FIFO64", "ns16550a";
441                         reg = <0x0 0x21d0600 0x0 0x100>;
442                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
443                         clock-frequency = <0>;
444                         fifo-size = <15>;
445                         status = "disabled";
446                 };
447
448                 counter0: counter@29d0000 {
449                         compatible = "fsl,ftm-quaddec";
450                         reg = <0x0 0x29d0000 0x0 0x10000>;
451                         big-endian;
452                         status = "disabled";
453                 };
454
455                 counter1: counter@29e0000 {
456                         compatible = "fsl,ftm-quaddec";
457                         reg = <0x0 0x29e0000 0x0 0x10000>;
458                         big-endian;
459                         status = "disabled";
460                 };
461
462                 counter2: counter@29f0000 {
463                         compatible = "fsl,ftm-quaddec";
464                         reg = <0x0 0x29f0000 0x0 0x10000>;
465                         big-endian;
466                         status = "disabled";
467                 };
468
469                 counter3: counter@2a00000 {
470                         compatible = "fsl,ftm-quaddec";
471                         reg = <0x0 0x2a00000 0x0 0x10000>;
472                         big-endian;
473                         status = "disabled";
474                 };
475
476                 gpio0: gpio@2300000 {
477                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
478                         reg = <0x0 0x2300000 0x0 0x10000>;
479                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
480                         gpio-controller;
481                         #gpio-cells = <2>;
482                         interrupt-controller;
483                         #interrupt-cells = <2>;
484                 };
485
486                 gpio1: gpio@2310000 {
487                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
488                         reg = <0x0 0x2310000 0x0 0x10000>;
489                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
490                         gpio-controller;
491                         #gpio-cells = <2>;
492                         interrupt-controller;
493                         #interrupt-cells = <2>;
494                 };
495
496                 gpio2: gpio@2320000 {
497                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
498                         reg = <0x0 0x2320000 0x0 0x10000>;
499                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
500                         gpio-controller;
501                         #gpio-cells = <2>;
502                         interrupt-controller;
503                         #interrupt-cells = <2>;
504                 };
505
506                 gpio3: gpio@2330000 {
507                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
508                         reg = <0x0 0x2330000 0x0 0x10000>;
509                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
510                         gpio-controller;
511                         #gpio-cells = <2>;
512                         interrupt-controller;
513                         #interrupt-cells = <2>;
514                 };
515
516                 lpuart0: serial@2950000 {
517                         compatible = "fsl,ls1021a-lpuart";
518                         reg = <0x0 0x2950000 0x0 0x1000>;
519                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
520                         clocks = <&sysclk>;
521                         clock-names = "ipg";
522                         status = "disabled";
523                 };
524
525                 lpuart1: serial@2960000 {
526                         compatible = "fsl,ls1021a-lpuart";
527                         reg = <0x0 0x2960000 0x0 0x1000>;
528                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
529                         clocks = <&clockgen 4 1>;
530                         clock-names = "ipg";
531                         status = "disabled";
532                 };
533
534                 lpuart2: serial@2970000 {
535                         compatible = "fsl,ls1021a-lpuart";
536                         reg = <0x0 0x2970000 0x0 0x1000>;
537                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
538                         clocks = <&clockgen 4 1>;
539                         clock-names = "ipg";
540                         status = "disabled";
541                 };
542
543                 lpuart3: serial@2980000 {
544                         compatible = "fsl,ls1021a-lpuart";
545                         reg = <0x0 0x2980000 0x0 0x1000>;
546                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
547                         clocks = <&clockgen 4 1>;
548                         clock-names = "ipg";
549                         status = "disabled";
550                 };
551
552                 lpuart4: serial@2990000 {
553                         compatible = "fsl,ls1021a-lpuart";
554                         reg = <0x0 0x2990000 0x0 0x1000>;
555                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
556                         clocks = <&clockgen 4 1>;
557                         clock-names = "ipg";
558                         status = "disabled";
559                 };
560
561                 lpuart5: serial@29a0000 {
562                         compatible = "fsl,ls1021a-lpuart";
563                         reg = <0x0 0x29a0000 0x0 0x1000>;
564                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
565                         clocks = <&clockgen 4 1>;
566                         clock-names = "ipg";
567                         status = "disabled";
568                 };
569
570                 pwm0: pwm@29d0000 {
571                         compatible = "fsl,vf610-ftm-pwm";
572                         #pwm-cells = <3>;
573                         reg = <0x0 0x29d0000 0x0 0x10000>;
574                         clock-names = "ftm_sys", "ftm_ext",
575                                 "ftm_fix", "ftm_cnt_clk_en";
576                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
577                                 <&clockgen 4 1>, <&clockgen 4 1>;
578                         big-endian;
579                         status = "disabled";
580                 };
581
582                 pwm1: pwm@29e0000 {
583                         compatible = "fsl,vf610-ftm-pwm";
584                         #pwm-cells = <3>;
585                         reg = <0x0 0x29e0000 0x0 0x10000>;
586                         clock-names = "ftm_sys", "ftm_ext",
587                                 "ftm_fix", "ftm_cnt_clk_en";
588                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
589                                 <&clockgen 4 1>, <&clockgen 4 1>;
590                         big-endian;
591                         status = "disabled";
592                 };
593
594                 pwm2: pwm@29f0000 {
595                         compatible = "fsl,vf610-ftm-pwm";
596                         #pwm-cells = <3>;
597                         reg = <0x0 0x29f0000 0x0 0x10000>;
598                         clock-names = "ftm_sys", "ftm_ext",
599                                 "ftm_fix", "ftm_cnt_clk_en";
600                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
601                                 <&clockgen 4 1>, <&clockgen 4 1>;
602                         big-endian;
603                         status = "disabled";
604                 };
605
606                 pwm3: pwm@2a00000 {
607                         compatible = "fsl,vf610-ftm-pwm";
608                         #pwm-cells = <3>;
609                         reg = <0x0 0x2a00000 0x0 0x10000>;
610                         clock-names = "ftm_sys", "ftm_ext",
611                                 "ftm_fix", "ftm_cnt_clk_en";
612                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
613                                 <&clockgen 4 1>, <&clockgen 4 1>;
614                         big-endian;
615                         status = "disabled";
616                 };
617
618                 pwm4: pwm@2a10000 {
619                         compatible = "fsl,vf610-ftm-pwm";
620                         #pwm-cells = <3>;
621                         reg = <0x0 0x2a10000 0x0 0x10000>;
622                         clock-names = "ftm_sys", "ftm_ext",
623                                 "ftm_fix", "ftm_cnt_clk_en";
624                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
625                                 <&clockgen 4 1>, <&clockgen 4 1>;
626                         big-endian;
627                         status = "disabled";
628                 };
629
630                 pwm5: pwm@2a20000 {
631                         compatible = "fsl,vf610-ftm-pwm";
632                         #pwm-cells = <3>;
633                         reg = <0x0 0x2a20000 0x0 0x10000>;
634                         clock-names = "ftm_sys", "ftm_ext",
635                                 "ftm_fix", "ftm_cnt_clk_en";
636                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
637                                 <&clockgen 4 1>, <&clockgen 4 1>;
638                         big-endian;
639                         status = "disabled";
640                 };
641
642                 pwm6: pwm@2a30000 {
643                         compatible = "fsl,vf610-ftm-pwm";
644                         #pwm-cells = <3>;
645                         reg = <0x0 0x2a30000 0x0 0x10000>;
646                         clock-names = "ftm_sys", "ftm_ext",
647                                 "ftm_fix", "ftm_cnt_clk_en";
648                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
649                                 <&clockgen 4 1>, <&clockgen 4 1>;
650                         big-endian;
651                         status = "disabled";
652                 };
653
654                 pwm7: pwm@2a40000 {
655                         compatible = "fsl,vf610-ftm-pwm";
656                         #pwm-cells = <3>;
657                         reg = <0x0 0x2a40000 0x0 0x10000>;
658                         clock-names = "ftm_sys", "ftm_ext",
659                                 "ftm_fix", "ftm_cnt_clk_en";
660                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
661                                 <&clockgen 4 1>, <&clockgen 4 1>;
662                         big-endian;
663                         status = "disabled";
664                 };
665
666                 wdog0: watchdog@2ad0000 {
667                         compatible = "fsl,imx21-wdt";
668                         reg = <0x0 0x2ad0000 0x0 0x10000>;
669                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
670                         clocks = <&clockgen 4 1>;
671                         clock-names = "wdog-en";
672                         big-endian;
673                 };
674
675                 sai1: sai@2b50000 {
676                         #sound-dai-cells = <0>;
677                         compatible = "fsl,vf610-sai";
678                         reg = <0x0 0x2b50000 0x0 0x10000>;
679                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
680                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
681                                  <&clockgen 4 1>, <&clockgen 4 1>;
682                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
683                         dma-names = "tx", "rx";
684                         dmas = <&edma0 1 47>,
685                                <&edma0 1 46>;
686                         status = "disabled";
687                 };
688
689                 sai2: sai@2b60000 {
690                         #sound-dai-cells = <0>;
691                         compatible = "fsl,vf610-sai";
692                         reg = <0x0 0x2b60000 0x0 0x10000>;
693                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
694                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
695                                  <&clockgen 4 1>, <&clockgen 4 1>;
696                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
697                         dma-names = "tx", "rx";
698                         dmas = <&edma0 1 45>,
699                                <&edma0 1 44>;
700                         status = "disabled";
701                 };
702
703                 edma0: edma@2c00000 {
704                         #dma-cells = <2>;
705                         compatible = "fsl,vf610-edma";
706                         reg = <0x0 0x2c00000 0x0 0x10000>,
707                               <0x0 0x2c10000 0x0 0x10000>,
708                               <0x0 0x2c20000 0x0 0x10000>;
709                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
710                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
711                         interrupt-names = "edma-tx", "edma-err";
712                         dma-channels = <32>;
713                         big-endian;
714                         clock-names = "dmamux0", "dmamux1";
715                         clocks = <&clockgen 4 1>,
716                                  <&clockgen 4 1>;
717                 };
718
719                 dcu: dcu@2ce0000 {
720                         compatible = "fsl,ls1021a-dcu";
721                         reg = <0x0 0x2ce0000 0x0 0x10000>;
722                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
723                         clocks = <&clockgen 4 0>,
724                                 <&clockgen 4 0>;
725                         clock-names = "dcu", "pix";
726                         big-endian;
727                         status = "disabled";
728                 };
729
730                 mdio0: mdio@2d24000 {
731                         compatible = "fsl,etsec2-mdio";
732                         device_type = "mdio";
733                         #address-cells = <1>;
734                         #size-cells = <0>;
735                         reg = <0x0 0x2d24000 0x0 0x4000>,
736                               <0x0 0x2d10030 0x0 0x4>;
737                 };
738
739                 mdio1: mdio@2d64000 {
740                         compatible = "fsl,etsec2-mdio";
741                         device_type = "mdio";
742                         #address-cells = <1>;
743                         #size-cells = <0>;
744                         reg = <0x0 0x2d64000 0x0 0x4000>,
745                               <0x0 0x2d50030 0x0 0x4>;
746                 };
747
748                 ptp_clock@2d10e00 {
749                         compatible = "fsl,etsec-ptp";
750                         reg = <0x0 0x2d10e00 0x0 0xb0>;
751                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
752                         fsl,tclk-period = <5>;
753                         fsl,tmr-prsc    = <2>;
754                         fsl,tmr-add     = <0xaaaaaaab>;
755                         fsl,tmr-fiper1  = <999999995>;
756                         fsl,tmr-fiper2  = <99990>;
757                         fsl,max-adj     = <499999999>;
758                         fsl,extts-fifo;
759                 };
760
761                 enet0: ethernet@2d10000 {
762                         compatible = "fsl,etsec2";
763                         device_type = "network";
764                         #address-cells = <2>;
765                         #size-cells = <2>;
766                         interrupt-parent = <&gic>;
767                         model = "eTSEC";
768                         fsl,magic-packet;
769                         ranges;
770                         dma-coherent;
771
772                         queue-group@2d10000 {
773                                 #address-cells = <2>;
774                                 #size-cells = <2>;
775                                 reg = <0x0 0x2d10000 0x0 0x1000>;
776                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
777                                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
778                                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
779                         };
780
781                         queue-group@2d14000  {
782                                 #address-cells = <2>;
783                                 #size-cells = <2>;
784                                 reg = <0x0 0x2d14000 0x0 0x1000>;
785                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
786                                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
787                                         <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
788                         };
789                 };
790
791                 enet1: ethernet@2d50000 {
792                         compatible = "fsl,etsec2";
793                         device_type = "network";
794                         #address-cells = <2>;
795                         #size-cells = <2>;
796                         interrupt-parent = <&gic>;
797                         model = "eTSEC";
798                         ranges;
799                         dma-coherent;
800
801                         queue-group@2d50000  {
802                                 #address-cells = <2>;
803                                 #size-cells = <2>;
804                                 reg = <0x0 0x2d50000 0x0 0x1000>;
805                                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
806                                         <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
807                                         <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
808                         };
809
810                         queue-group@2d54000  {
811                                 #address-cells = <2>;
812                                 #size-cells = <2>;
813                                 reg = <0x0 0x2d54000 0x0 0x1000>;
814                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
815                                         <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
816                                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
817                         };
818                 };
819
820                 enet2: ethernet@2d90000 {
821                         compatible = "fsl,etsec2";
822                         device_type = "network";
823                         #address-cells = <2>;
824                         #size-cells = <2>;
825                         interrupt-parent = <&gic>;
826                         model = "eTSEC";
827                         ranges;
828                         dma-coherent;
829
830                         queue-group@2d90000  {
831                                 #address-cells = <2>;
832                                 #size-cells = <2>;
833                                 reg = <0x0 0x2d90000 0x0 0x1000>;
834                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
835                                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
836                                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
837                         };
838
839                         queue-group@2d94000  {
840                                 #address-cells = <2>;
841                                 #size-cells = <2>;
842                                 reg = <0x0 0x2d94000 0x0 0x1000>;
843                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
844                                         <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
845                                         <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
846                         };
847                 };
848
849                 usb2: usb@8600000 {
850                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
851                         reg = <0x0 0x8600000 0x0 0x1000>;
852                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
853                         dr_mode = "host";
854                         phy_type = "ulpi";
855                 };
856
857                 usb3: usb3@3100000 {
858                         compatible = "snps,dwc3";
859                         reg = <0x0 0x3100000 0x0 0x10000>;
860                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
861                         dr_mode = "host";
862                         snps,quirk-frame-length-adjustment = <0x20>;
863                         snps,dis_rxdet_inp3_quirk;
864                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
865                 };
866
867                 pcie@3400000 {
868                         compatible = "fsl,ls1021a-pcie";
869                         reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
870                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
871                         reg-names = "regs", "config";
872                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
873                         fsl,pcie-scfg = <&scfg 0>;
874                         #address-cells = <3>;
875                         #size-cells = <2>;
876                         device_type = "pci";
877                         num-lanes = <4>;
878                         num-viewport = <6>;
879                         bus-range = <0x0 0xff>;
880                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
881                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
882                         msi-parent = <&msi1>, <&msi2>;
883                         #interrupt-cells = <1>;
884                         interrupt-map-mask = <0 0 0 7>;
885                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
886                                         <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
887                                         <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
888                                         <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
889                         status = "disabled";
890                 };
891
892                 pcie@3500000 {
893                         compatible = "fsl,ls1021a-pcie";
894                         reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
895                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
896                         reg-names = "regs", "config";
897                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
898                         fsl,pcie-scfg = <&scfg 1>;
899                         #address-cells = <3>;
900                         #size-cells = <2>;
901                         device_type = "pci";
902                         num-lanes = <4>;
903                         num-viewport = <6>;
904                         bus-range = <0x0 0xff>;
905                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
906                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
907                         msi-parent = <&msi1>, <&msi2>;
908                         #interrupt-cells = <1>;
909                         interrupt-map-mask = <0 0 0 7>;
910                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
911                                         <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
912                                         <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
913                                         <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
914                         status = "disabled";
915                 };
916
917                 can0: can@2a70000 {
918                         compatible = "fsl,ls1021ar2-flexcan";
919                         reg = <0x0 0x2a70000 0x0 0x1000>;
920                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
921                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
922                         clock-names = "ipg", "per";
923                         big-endian;
924                 };
925
926                 can1: can@2a80000 {
927                         compatible = "fsl,ls1021ar2-flexcan";
928                         reg = <0x0 0x2a80000 0x0 0x1000>;
929                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
930                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
931                         clock-names = "ipg", "per";
932                         big-endian;
933                 };
934
935                 can2: can@2a90000 {
936                         compatible = "fsl,ls1021ar2-flexcan";
937                         reg = <0x0 0x2a90000 0x0 0x1000>;
938                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
939                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
940                         clock-names = "ipg", "per";
941                         big-endian;
942                 };
943
944                 can3: can@2aa0000 {
945                         compatible = "fsl,ls1021ar2-flexcan";
946                         reg = <0x0 0x2aa0000 0x0 0x1000>;
947                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
948                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
949                         clock-names = "ipg", "per";
950                         big-endian;
951                 };
952
953                 ocram1: sram@10000000 {
954                         compatible = "mmio-sram";
955                         reg = <0x0 0x10000000 0x0 0x10000>;
956                         #address-cells = <1>;
957                         #size-cells = <1>;
958                         ranges = <0x0 0x0 0x10000000 0x10000>;
959                 };
960
961                 ocram2: sram@10010000 {
962                         compatible = "mmio-sram";
963                         reg = <0x0 0x10010000 0x0 0x10000>;
964                         #address-cells = <1>;
965                         #size-cells = <1>;
966                         ranges = <0x0 0x0 0x10010000 0x10000>;
967                 };
968
969                 qdma: dma-controller@8390000 {
970                         compatible = "fsl,ls1021a-qdma";
971                         reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
972                               <0x0 0x8389000 0x0 0x1000>, /* Status regs */
973                               <0x0 0x838a000 0x0 0x2000>; /* Block regs */
974                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
975                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
976                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
977                         interrupt-names = "qdma-error",
978                                 "qdma-queue0", "qdma-queue1";
979                         dma-channels = <8>;
980                         block-number = <1>;
981                         block-offset = <0x1000>;
982                         fsl,dma-queues = <2>;
983                         status-sizes = <64>;
984                         queue-sizes = <64 64>;
985                         big-endian;
986                 };
987
988         };
989 };