arch/arm/boot/dts/ls1021a.dtsi

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton64.dtsi"
  49 #include <dt-bindings/interrupt-controller/arm-gic.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "fsl,ls1021a";
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 crypto = &crypto;
  58                 ethernet0 = &enet0;
  59                 ethernet1 = &enet1;
  60                 ethernet2 = &enet2;
  61                 serial0 = &lpuart0;
  62                 serial1 = &lpuart1;
  63                 serial2 = &lpuart2;
  64                 serial3 = &lpuart3;
  65                 serial4 = &lpuart4;
  66                 serial5 = &lpuart5;
  67                 sysclk = &sysclk;
  68         };
  69
  70         cpus {
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74                 cpu0: cpu@f00 {
  75                         compatible = "arm,cortex-a7";
  76                         device_type = "cpu";
  77                         reg = <0xf00>;
  78                         clocks = <&cluster1_clk>;
  79                         #cooling-cells = <2>;
  80                 };
  81
  82                 cpu1: cpu@f01 {
  83                         compatible = "arm,cortex-a7";
  84                         device_type = "cpu";
  85                         reg = <0xf01>;
  86                         clocks = <&cluster1_clk>;
  87                 };
  88         };
  89
  90         timer {
  91                 compatible = "arm,armv7-timer";
  92                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  93                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  94                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  95                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  96         };
  97
  98         pmu {
  99                 compatible = "arm,cortex-a7-pmu";
 100                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 101                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 102         };
 103
 104         soc {
 105                 compatible = "simple-bus";
 106                 #address-cells = <2>;
 107                 #size-cells = <2>;
 108                 device_type = "soc";
 109                 interrupt-parent = <&gic>;
 110                 ranges;
 111
 112                 gic: interrupt-controller@1400000 {
 113                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
 114                         #interrupt-cells = <3>;
 115                         interrupt-controller;
 116                         reg = <0x0 0x1401000 0x0 0x1000>,
 117                               <0x0 0x1402000 0x0 0x2000>,
 118                               <0x0 0x1404000 0x0 0x2000>,
 119                               <0x0 0x1406000 0x0 0x2000>;
 120                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 121
 122                 };
 123
 124                 msi1: msi-controller@1570e00 {
 125                         compatible = "fsl,1s1021a-msi";
 126                         reg = <0x0 0x1570e00 0x0 0x8>;
 127                         msi-controller;
 128                         interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 129                 };
 130
 131                 msi2: msi-controller@1570e08 {
 132                         compatible = "fsl,1s1021a-msi";
 133                         reg = <0x0 0x1570e08 0x0 0x8>;
 134                         msi-controller;
 135                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 136                 };
 137
 138                 ifc: ifc@1530000 {
 139                         compatible = "fsl,ifc", "simple-bus";
 140                         reg = <0x0 0x1530000 0x0 0x10000>;
 141                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 142                 };
 143
 144                 dcfg: dcfg@1ee0000 {
 145                         compatible = "fsl,ls1021a-dcfg", "syscon";
 146                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 147                         big-endian;
 148                 };
 149
 150                 esdhc: esdhc@1560000 {
 151                         compatible = "fsl,esdhc";
 152                         reg = <0x0 0x1560000 0x0 0x10000>;
 153                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 154                         clock-frequency = <0>;
 155                         voltage-ranges = <1800 1800 3300 3300>;
 156                         sdhci,auto-cmd12;
 157                         big-endian;
 158                         bus-width = <4>;
 159                         status = "disabled";
 160                 };
 161
 162                 sata: sata@3200000 {
 163                         compatible = "fsl,ls1021a-ahci";
 164                         reg = <0x0 0x3200000 0x0 0x10000>,
 165                               <0x0 0x20220520 0x0 0x4>;
 166                         reg-names = "ahci", "sata-ecc";
 167                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&platform_clk 1>;
 169                         dma-coherent;
 170                         status = "disabled";
 171                 };
 172
 173                 scfg: scfg@1570000 {
 174                         compatible = "fsl,ls1021a-scfg", "syscon";
 175                         reg = <0x0 0x1570000 0x0 0x10000>;
 176                         big-endian;
 177                 };
 178
 179                 crypto: crypto@1700000 {
 180                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 181                         fsl,sec-era = <7>;
 182                         #address-cells = <1>;
 183                         #size-cells = <1>;
 184                         reg              = <0x0 0x1700000 0x0 0x100000>;
 185                         ranges           = <0x0 0x0 0x1700000 0x100000>;
 186                         interrupts       = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 187
 188                         sec_jr0: jr@10000 {
 189                                 compatible = "fsl,sec-v5.0-job-ring",
 190                                      "fsl,sec-v4.0-job-ring";
 191                                 reg = <0x10000 0x10000>;
 192                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 193                         };
 194
 195                         sec_jr1: jr@20000 {
 196                                 compatible = "fsl,sec-v5.0-job-ring",
 197                                      "fsl,sec-v4.0-job-ring";
 198                                 reg = <0x20000 0x10000>;
 199                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 200                         };
 201
 202                         sec_jr2: jr@30000 {
 203                                 compatible = "fsl,sec-v5.0-job-ring",
 204                                      "fsl,sec-v4.0-job-ring";
 205                                 reg = <0x30000 0x10000>;
 206                                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 207                         };
 208
 209                         sec_jr3: jr@40000 {
 210                                 compatible = "fsl,sec-v5.0-job-ring",
 211                                      "fsl,sec-v4.0-job-ring";
 212                                 reg = <0x40000 0x10000>;
 213                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 214                         };
 215
 216                 };
 217
 218                 clockgen: clocking@1ee1000 {
 219                         #address-cells = <1>;
 220                         #size-cells = <1>;
 221                         ranges = <0x0 0x0 0x1ee1000 0x10000>;
 222
 223                         sysclk: sysclk {
 224                                 compatible = "fixed-clock";
 225                                 #clock-cells = <0>;
 226                                 clock-output-names = "sysclk";
 227                         };
 228
 229                         cga_pll1: pll@800 {
 230                                 compatible = "fsl,qoriq-core-pll-2.0";
 231                                 #clock-cells = <1>;
 232                                 reg = <0x800 0x10>;
 233                                 clocks = <&sysclk>;
 234                                 clock-output-names = "cga-pll1", "cga-pll1-div2",
 235                                                      "cga-pll1-div4";
 236                         };
 237
 238                         platform_clk: pll@c00 {
 239                                 compatible = "fsl,qoriq-core-pll-2.0";
 240                                 #clock-cells = <1>;
 241                                 reg = <0xc00 0x10>;
 242                                 clocks = <&sysclk>;
 243                                 clock-output-names = "platform-clk", "platform-clk-div2";
 244                         };
 245
 246                         cluster1_clk: clk0c0@0 {
 247                                 compatible = "fsl,qoriq-core-mux-2.0";
 248                                 #clock-cells = <0>;
 249                                 reg = <0x0 0x10>;
 250                                 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
 251                                 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
 252                                 clock-output-names = "cluster1-clk";
 253                         };
 254                 };
 255
 256                 tmu: tmu@1f00000 {
 257                         compatible = "fsl,qoriq-tmu";
 258                         reg = <0x0 0x1f00000 0x0 0x10000>;
 259                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 260                         fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
 261                         fsl,tmu-calibration = <0x00000000 0x0000000f
 262                                                0x00000001 0x00000017
 263                                                0x00000002 0x0000001e
 264                                                0x00000003 0x00000026
 265                                                0x00000004 0x0000002e
 266                                                0x00000005 0x00000035
 267                                                0x00000006 0x0000003d
 268                                                0x00000007 0x00000044
 269                                                0x00000008 0x0000004c
 270                                                0x00000009 0x00000053
 271                                                0x0000000a 0x0000005b
 272                                                0x0000000b 0x00000064
 273
 274                                                0x00010000 0x00000011
 275                                                0x00010001 0x0000001c
 276                                                0x00010002 0x00000024
 277                                                0x00010003 0x0000002b
 278                                                0x00010004 0x00000034
 279                                                0x00010005 0x00000039
 280                                                0x00010006 0x00000042
 281                                                0x00010007 0x0000004c
 282                                                0x00010008 0x00000051
 283                                                0x00010009 0x0000005a
 284                                                0x0001000a 0x00000063
 285
 286                                                0x00020000 0x00000013
 287                                                0x00020001 0x00000019
 288                                                0x00020002 0x00000024
 289                                                0x00020003 0x0000002c
 290                                                0x00020004 0x00000035
 291                                                0x00020005 0x0000003d
 292                                                0x00020006 0x00000046
 293                                                0x00020007 0x00000050
 294                                                0x00020008 0x00000059
 295
 296                                                0x00030000 0x00000002
 297                                                0x00030001 0x0000000d
 298                                                0x00030002 0x00000019
 299                                                0x00030003 0x00000024>;
 300                         #thermal-sensor-cells = <1>;
 301                 };
 302
 303                 thermal-zones {
 304                         cpu_thermal: cpu-thermal {
 305                                 polling-delay-passive = <1000>;
 306                                 polling-delay = <5000>;
 307
 308                                 thermal-sensors = <&tmu 0>;
 309
 310                                 trips {
 311                                         cpu_alert: cpu-alert {
 312                                                 temperature = <85000>;
 313                                                 hysteresis = <2000>;
 314                                                 type = "passive";
 315                                         };
 316                                         cpu_crit: cpu-crit {
 317                                                 temperature = <95000>;
 318                                                 hysteresis = <2000>;
 319                                                 type = "critical";
 320                                         };
 321                                 };
 322
 323                                 cooling-maps {
 324                                         map0 {
 325                                                 trip = <&cpu_alert>;
 326                                                 cooling-device =
 327                                                         <&cpu0 THERMAL_NO_LIMIT
 328                                                         THERMAL_NO_LIMIT>;
 329                                         };
 330                                 };
 331                         };
 332                 };
 333
 334                 dspi0: dspi@2100000 {
 335                         compatible = "fsl,ls1021a-v1.0-dspi";
 336                         #address-cells = <1>;
 337                         #size-cells = <0>;
 338                         reg = <0x0 0x2100000 0x0 0x10000>;
 339                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 340                         clock-names = "dspi";
 341                         clocks = <&platform_clk 1>;
 342                         spi-num-chipselects = <6>;
 343                         big-endian;
 344                         status = "disabled";
 345                 };
 346
 347                 dspi1: dspi@2110000 {
 348                         compatible = "fsl,ls1021a-v1.0-dspi";
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351                         reg = <0x0 0x2110000 0x0 0x10000>;
 352                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 353                         clock-names = "dspi";
 354                         clocks = <&platform_clk 1>;
 355                         spi-num-chipselects = <6>;
 356                         big-endian;
 357                         status = "disabled";
 358                 };
 359
 360                 i2c0: i2c@2180000 {
 361                         compatible = "fsl,vf610-i2c";
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         reg = <0x0 0x2180000 0x0 0x10000>;
 365                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 366                         clock-names = "i2c";
 367                         clocks = <&platform_clk 1>;
 368                         status = "disabled";
 369                 };
 370
 371                 i2c1: i2c@2190000 {
 372                         compatible = "fsl,vf610-i2c";
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         reg = <0x0 0x2190000 0x0 0x10000>;
 376                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 377                         clock-names = "i2c";
 378                         clocks = <&platform_clk 1>;
 379                         status = "disabled";
 380                 };
 381
 382                 i2c2: i2c@21a0000 {
 383                         compatible = "fsl,vf610-i2c";
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                         reg = <0x0 0x21a0000 0x0 0x10000>;
 387                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 388                         clock-names = "i2c";
 389                         clocks = <&platform_clk 1>;
 390                         status = "disabled";
 391                 };
 392
 393                 uart0: serial@21c0500 {
 394                         compatible = "fsl,16550-FIFO64", "ns16550a";
 395                         reg = <0x0 0x21c0500 0x0 0x100>;
 396                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 397                         clock-frequency = <0>;
 398                         fifo-size = <15>;
 399                         status = "disabled";
 400                 };
 401
 402                 uart1: serial@21c0600 {
 403                         compatible = "fsl,16550-FIFO64", "ns16550a";
 404                         reg = <0x0 0x21c0600 0x0 0x100>;
 405                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 406                         clock-frequency = <0>;
 407                         fifo-size = <15>;
 408                         status = "disabled";
 409                 };
 410
 411                 uart2: serial@21d0500 {
 412                         compatible = "fsl,16550-FIFO64", "ns16550a";
 413                         reg = <0x0 0x21d0500 0x0 0x100>;
 414                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 415                         clock-frequency = <0>;
 416                         fifo-size = <15>;
 417                         status = "disabled";
 418                 };
 419
 420                 uart3: serial@21d0600 {
 421                         compatible = "fsl,16550-FIFO64", "ns16550a";
 422                         reg = <0x0 0x21d0600 0x0 0x100>;
 423                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 424                         clock-frequency = <0>;
 425                         fifo-size = <15>;
 426                         status = "disabled";
 427                 };
 428
 429                 gpio0: gpio@2300000 {
 430                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 431                         reg = <0x0 0x2300000 0x0 0x10000>;
 432                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 433                         gpio-controller;
 434                         #gpio-cells = <2>;
 435                         interrupt-controller;
 436                         #interrupt-cells = <2>;
 437                 };
 438
 439                 gpio1: gpio@2310000 {
 440                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 441                         reg = <0x0 0x2310000 0x0 0x10000>;
 442                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 443                         gpio-controller;
 444                         #gpio-cells = <2>;
 445                         interrupt-controller;
 446                         #interrupt-cells = <2>;
 447                 };
 448
 449                 gpio2: gpio@2320000 {
 450                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 451                         reg = <0x0 0x2320000 0x0 0x10000>;
 452                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 453                         gpio-controller;
 454                         #gpio-cells = <2>;
 455                         interrupt-controller;
 456                         #interrupt-cells = <2>;
 457                 };
 458
 459                 gpio3: gpio@2330000 {
 460                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 461                         reg = <0x0 0x2330000 0x0 0x10000>;
 462                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 463                         gpio-controller;
 464                         #gpio-cells = <2>;
 465                         interrupt-controller;
 466                         #interrupt-cells = <2>;
 467                 };
 468
 469                 lpuart0: serial@2950000 {
 470                         compatible = "fsl,ls1021a-lpuart";
 471                         reg = <0x0 0x2950000 0x0 0x1000>;
 472                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&sysclk>;
 474                         clock-names = "ipg";
 475                         status = "disabled";
 476                 };
 477
 478                 lpuart1: serial@2960000 {
 479                         compatible = "fsl,ls1021a-lpuart";
 480                         reg = <0x0 0x2960000 0x0 0x1000>;
 481                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 482                         clocks = <&platform_clk 1>;
 483                         clock-names = "ipg";
 484                         status = "disabled";
 485                 };
 486
 487                 lpuart2: serial@2970000 {
 488                         compatible = "fsl,ls1021a-lpuart";
 489                         reg = <0x0 0x2970000 0x0 0x1000>;
 490                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 491                         clocks = <&platform_clk 1>;
 492                         clock-names = "ipg";
 493                         status = "disabled";
 494                 };
 495
 496                 lpuart3: serial@2980000 {
 497                         compatible = "fsl,ls1021a-lpuart";
 498                         reg = <0x0 0x2980000 0x0 0x1000>;
 499                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 500                         clocks = <&platform_clk 1>;
 501                         clock-names = "ipg";
 502                         status = "disabled";
 503                 };
 504
 505                 lpuart4: serial@2990000 {
 506                         compatible = "fsl,ls1021a-lpuart";
 507                         reg = <0x0 0x2990000 0x0 0x1000>;
 508                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 509                         clocks = <&platform_clk 1>;
 510                         clock-names = "ipg";
 511                         status = "disabled";
 512                 };
 513
 514                 lpuart5: serial@29a0000 {
 515                         compatible = "fsl,ls1021a-lpuart";
 516                         reg = <0x0 0x29a0000 0x0 0x1000>;
 517                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 518                         clocks = <&platform_clk 1>;
 519                         clock-names = "ipg";
 520                         status = "disabled";
 521                 };
 522
 523                 wdog0: watchdog@2ad0000 {
 524                         compatible = "fsl,imx21-wdt";
 525                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 526                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 527                         clocks = <&platform_clk 1>;
 528                         clock-names = "wdog-en";
 529                         big-endian;
 530                 };
 531
 532                 sai1: sai@2b50000 {
 533                         #sound-dai-cells = <0>;
 534                         compatible = "fsl,vf610-sai";
 535                         reg = <0x0 0x2b50000 0x0 0x10000>;
 536                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 537                         clocks = <&platform_clk 1>, <&platform_clk 1>,
 538                                  <&platform_clk 1>, <&platform_clk 1>;
 539                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 540                         dma-names = "tx", "rx";
 541                         dmas = <&edma0 1 47>,
 542                                <&edma0 1 46>;
 543                         status = "disabled";
 544                 };
 545
 546                 sai2: sai@2b60000 {
 547                         #sound-dai-cells = <0>;
 548                         compatible = "fsl,vf610-sai";
 549                         reg = <0x0 0x2b60000 0x0 0x10000>;
 550                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 551                         clocks = <&platform_clk 1>, <&platform_clk 1>,
 552                                  <&platform_clk 1>, <&platform_clk 1>;
 553                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 554                         dma-names = "tx", "rx";
 555                         dmas = <&edma0 1 45>,
 556                                <&edma0 1 44>;
 557                         status = "disabled";
 558                 };
 559
 560                 edma0: edma@2c00000 {
 561                         #dma-cells = <2>;
 562                         compatible = "fsl,vf610-edma";
 563                         reg = <0x0 0x2c00000 0x0 0x10000>,
 564                               <0x0 0x2c10000 0x0 0x10000>,
 565                               <0x0 0x2c20000 0x0 0x10000>;
 566                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 567                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 568                         interrupt-names = "edma-tx", "edma-err";
 569                         dma-channels = <32>;
 570                         big-endian;
 571                         clock-names = "dmamux0", "dmamux1";
 572                         clocks = <&platform_clk 1>,
 573                                  <&platform_clk 1>;
 574                 };
 575
 576                 dcu: dcu@2ce0000 {
 577                         compatible = "fsl,ls1021a-dcu";
 578                         reg = <0x0 0x2ce0000 0x0 0x10000>;
 579                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 580                         clocks = <&platform_clk 0>,
 581                                 <&platform_clk 0>;
 582                         clock-names = "dcu", "pix";
 583                         big-endian;
 584                         status = "disabled";
 585                 };
 586
 587                 mdio0: mdio@2d24000 {
 588                         compatible = "gianfar";
 589                         device_type = "mdio";
 590                         #address-cells = <1>;
 591                         #size-cells = <0>;
 592                         reg = <0x0 0x2d24000 0x0 0x4000>;
 593                 };
 594
 595                 ptp_clock@2d10e00 {
 596                         compatible = "fsl,etsec-ptp";
 597                         reg = <0x0 0x2d10e00 0x0 0xb0>;
 598                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 599                         fsl,tclk-period = <5>;
 600                         fsl,tmr-prsc    = <2>;
 601                         fsl,tmr-add     = <0xaaaaaaab>;
 602                         fsl,tmr-fiper1  = <999999990>;
 603                         fsl,tmr-fiper2  = <99990>;
 604                         fsl,max-adj     = <499999999>;
 605                 };
 606
 607                 enet0: ethernet@2d10000 {
 608                         compatible = "fsl,etsec2";
 609                         device_type = "network";
 610                         #address-cells = <2>;
 611                         #size-cells = <2>;
 612                         interrupt-parent = <&gic>;
 613                         model = "eTSEC";
 614                         fsl,magic-packet;
 615                         ranges;
 616                         dma-coherent;
 617
 618                         queue-group@2d10000 {
 619                                 #address-cells = <2>;
 620                                 #size-cells = <2>;
 621                                 reg = <0x0 0x2d10000 0x0 0x1000>;
 622                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 623                                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 624                                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 625                         };
 626
 627                         queue-group@2d14000  {
 628                                 #address-cells = <2>;
 629                                 #size-cells = <2>;
 630                                 reg = <0x0 0x2d14000 0x0 0x1000>;
 631                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 632                                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 633                                         <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 634                         };
 635                 };
 636
 637                 enet1: ethernet@2d50000 {
 638                         compatible = "fsl,etsec2";
 639                         device_type = "network";
 640                         #address-cells = <2>;
 641                         #size-cells = <2>;
 642                         interrupt-parent = <&gic>;
 643                         model = "eTSEC";
 644                         ranges;
 645                         dma-coherent;
 646
 647                         queue-group@2d50000  {
 648                                 #address-cells = <2>;
 649                                 #size-cells = <2>;
 650                                 reg = <0x0 0x2d50000 0x0 0x1000>;
 651                                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 652                                         <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 653                                         <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 654                         };
 655
 656                         queue-group@2d54000  {
 657                                 #address-cells = <2>;
 658                                 #size-cells = <2>;
 659                                 reg = <0x0 0x2d54000 0x0 0x1000>;
 660                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 661                                         <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 662                                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 663                         };
 664                 };
 665
 666                 enet2: ethernet@2d90000 {
 667                         compatible = "fsl,etsec2";
 668                         device_type = "network";
 669                         #address-cells = <2>;
 670                         #size-cells = <2>;
 671                         interrupt-parent = <&gic>;
 672                         model = "eTSEC";
 673                         ranges;
 674                         dma-coherent;
 675
 676                         queue-group@2d90000  {
 677                                 #address-cells = <2>;
 678                                 #size-cells = <2>;
 679                                 reg = <0x0 0x2d90000 0x0 0x1000>;
 680                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 681                                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 682                                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 683                         };
 684
 685                         queue-group@2d94000  {
 686                                 #address-cells = <2>;
 687                                 #size-cells = <2>;
 688                                 reg = <0x0 0x2d94000 0x0 0x1000>;
 689                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 690                                         <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 691                                         <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 692                         };
 693                 };
 694
 695                 usb@8600000 {
 696                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 697                         reg = <0x0 0x8600000 0x0 0x1000>;
 698                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 699                         dr_mode = "host";
 700                         phy_type = "ulpi";
 701                 };
 702
 703                 usb3@3100000 {
 704                         compatible = "snps,dwc3";
 705                         reg = <0x0 0x3100000 0x0 0x10000>;
 706                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 707                         dr_mode = "host";
 708                         snps,quirk-frame-length-adjustment = <0x20>;
 709                         snps,dis_rxdet_inp3_quirk;
 710                 };
 711
 712                 pcie@3400000 {
 713                         compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
 714                         reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 715                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 716                         reg-names = "regs", "config";
 717                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 718                         fsl,pcie-scfg = <&scfg 0>;
 719                         #address-cells = <3>;
 720                         #size-cells = <2>;
 721                         device_type = "pci";
 722                         num-lanes = <4>;
 723                         bus-range = <0x0 0xff>;
 724                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 725                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 726                         msi-parent = <&msi1>;
 727                         #interrupt-cells = <1>;
 728                         interrupt-map-mask = <0 0 0 7>;
 729                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
 730                                         <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 731                                         <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 732                                         <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 733                 };
 734
 735                 pcie@3500000 {
 736                         compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
 737                         reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
 738                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 739                         reg-names = "regs", "config";
 740                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 741                         fsl,pcie-scfg = <&scfg 1>;
 742                         #address-cells = <3>;
 743                         #size-cells = <2>;
 744                         device_type = "pci";
 745                         num-lanes = <4>;
 746                         bus-range = <0x0 0xff>;
 747                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 748                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 749                         msi-parent = <&msi2>;
 750                         #interrupt-cells = <1>;
 751                         interrupt-map-mask = <0 0 0 7>;
 752                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
 753                                         <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 754                                         <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 755                                         <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 756                 };
 757         };
 758 };