arch/arm/boot/dts/ls1021a-qds.dts

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  * Copyright 2018 NXP
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of
  13  *     the License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  *     You should have received a copy of the GNU General Public
  21  *     License along with this file; if not, write to the Free
  22  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  23  *     MA 02110-1301 USA
  24  *
  25  * Or, alternatively,
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use,
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  */
  48
  49 /dts-v1/;
  50 #include "ls1021a.dtsi"
  51
  52 / {
  53         model = "LS1021A QDS Board";
  54         compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
  55
  56         aliases {
  57                 enet0_rgmii_phy = &rgmii_phy1;
  58                 enet1_rgmii_phy = &rgmii_phy2;
  59                 enet2_rgmii_phy = &rgmii_phy3;
  60                 enet0_sgmii_phy = &sgmii_phy1c;
  61                 enet1_sgmii_phy = &sgmii_phy1d;
  62         };
  63
  64         sys_mclk: clock-mclk {
  65                 compatible = "fixed-clock";
  66                 #clock-cells = <0>;
  67                 clock-frequency = <24576000>;
  68         };
  69
  70         regulators {
  71                 compatible = "simple-bus";
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74
  75                 reg_3p3v: regulator@0 {
  76                         compatible = "regulator-fixed";
  77                         reg = <0>;
  78                         regulator-name = "3P3V";
  79                         regulator-min-microvolt = <3300000>;
  80                         regulator-max-microvolt = <3300000>;
  81                         regulator-always-on;
  82                 };
  83         };
  84
  85         sound {
  86                 compatible = "simple-audio-card";
  87                 simple-audio-card,format = "i2s";
  88                 simple-audio-card,widgets =
  89                         "Microphone", "Microphone Jack",
  90                         "Headphone", "Headphone Jack",
  91                         "Speaker", "Speaker Ext",
  92                         "Line", "Line In Jack";
  93                 simple-audio-card,routing =
  94                         "MIC_IN", "Microphone Jack",
  95                         "Microphone Jack", "Mic Bias",
  96                         "LINE_IN", "Line In Jack",
  97                         "Headphone Jack", "HP_OUT",
  98                         "Speaker Ext", "LINE_OUT";
  99
 100                 simple-audio-card,cpu {
 101                         sound-dai = <&sai2>;
 102                         frame-master;
 103                         bitclock-master;
 104                 };
 105
 106                 simple-audio-card,codec {
 107                         sound-dai = <&codec>;
 108                         frame-master;
 109                         bitclock-master;
 110                 };
 111         };
 112 };
 113
 114 &dspi0 {
 115         bus-num = <0>;
 116         status = "okay";
 117
 118         dspiflash: at45db021d@0 {
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
 122                 spi-max-frequency = <16000000>;
 123                 spi-cpol;
 124                 spi-cpha;
 125                 reg = <0>;
 126         };
 127 };
 128
 129 &enet0 {
 130         tbi-handle = <&tbi0>;
 131         phy-handle = <&sgmii_phy1c>;
 132         phy-connection-type = "sgmii";
 133         status = "okay";
 134 };
 135
 136 &enet1 {
 137         tbi-handle = <&tbi0>;
 138         phy-handle = <&sgmii_phy1d>;
 139         phy-connection-type = "sgmii";
 140         status = "okay";
 141 };
 142
 143 &enet2 {
 144         phy-handle = <&rgmii_phy3>;
 145         phy-connection-type = "rgmii-id";
 146         status = "okay";
 147 };
 148
 149 &i2c0 {
 150         status = "okay";
 151
 152         pca9547: mux@77 {
 153                 compatible = "nxp,pca9547";
 154                 reg = <0x77>;
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157
 158                 i2c@0 {
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                         reg = <0x0>;
 162
 163                         ds3232: rtc@68 {
 164                                 compatible = "dallas,ds3232";
 165                                 reg = <0x68>;
 166                                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 167                         };
 168                 };
 169
 170                 i2c@2 {
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         reg = <0x2>;
 174
 175                         ina220@40 {
 176                                 compatible = "ti,ina220";
 177                                 reg = <0x40>;
 178                                 shunt-resistor = <1000>;
 179                         };
 180
 181                         ina220@41 {
 182                                 compatible = "ti,ina220";
 183                                 reg = <0x41>;
 184                                 shunt-resistor = <1000>;
 185                         };
 186                 };
 187
 188                 i2c@3 {
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         reg = <0x3>;
 192
 193                         eeprom@56 {
 194                                 compatible = "atmel,24c512";
 195                                 reg = <0x56>;
 196                         };
 197
 198                         eeprom@57 {
 199                                 compatible = "atmel,24c512";
 200                                 reg = <0x57>;
 201                         };
 202
 203                         adt7461a@4c {
 204                                 compatible = "adi,adt7461a";
 205                                 reg = <0x4c>;
 206                         };
 207                 };
 208
 209                 i2c@4 {
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                         reg = <0x4>;
 213
 214                         codec: sgtl5000@2a {
 215                                 #sound-dai-cells = <0>;
 216                                 compatible = "fsl,sgtl5000";
 217                                 reg = <0x2a>;
 218                                 VDDA-supply = <&reg_3p3v>;
 219                                 VDDIO-supply = <&reg_3p3v>;
 220                                 clocks = <&sys_mclk>;
 221                         };
 222                 };
 223         };
 224 };
 225
 226 &ifc {
 227         #address-cells = <2>;
 228         #size-cells = <1>;
 229         /* NOR, NAND Flashes and FPGA on board */
 230         ranges = <0x0 0x0 0x0 0x60000000 0x08000000
 231                   0x2 0x0 0x0 0x7e800000 0x00010000
 232                   0x3 0x0 0x0 0x7fb00000 0x00000100>;
 233         status = "okay";
 234
 235         nor@0,0 {
 236                 #address-cells = <1>;
 237                 #size-cells = <1>;
 238                 compatible = "cfi-flash";
 239                 reg = <0x0 0x0 0x8000000>;
 240                 big-endian;
 241                 bank-width = <2>;
 242                 device-width = <1>;
 243         };
 244
 245         nand@2,0 {
 246                 compatible = "fsl,ifc-nand";
 247                 reg = <0x2 0x0 0x10000>;
 248         };
 249
 250         fpga: board-control@3,0 {
 251                 #address-cells = <1>;
 252                 #size-cells = <1>;
 253                 compatible = "simple-bus";
 254                 reg = <0x3 0x0 0x0000100>;
 255                 bank-width = <1>;
 256                 device-width = <1>;
 257                 ranges = <0 3 0 0x100>;
 258
 259                 mdio-mux-emi1 {
 260                         compatible = "mdio-mux-mmioreg";
 261                         mdio-parent-bus = <&mdio0>;
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                         reg = <0x54 1>; /* BRDCFG4 */
 265                         mux-mask = <0xe0>; /* EMI1[2:0] */
 266
 267                         /* Onboard PHYs */
 268                         ls1021amdio0: mdio@0 {
 269                                 reg = <0>;
 270                                 #address-cells = <1>;
 271                                 #size-cells = <0>;
 272                                 rgmii_phy1: ethernet-phy@1 {
 273                                         reg = <0x1>;
 274                                 };
 275                         };
 276
 277                         ls1021amdio1: mdio@20 {
 278                                 reg = <0x20>;
 279                                 #address-cells = <1>;
 280                                 #size-cells = <0>;
 281                                 rgmii_phy2: ethernet-phy@2 {
 282                                         reg = <0x2>;
 283                                 };
 284                         };
 285
 286                         ls1021amdio2: mdio@40 {
 287                                 reg = <0x40>;
 288                                 #address-cells = <1>;
 289                                 #size-cells = <0>;
 290                                 rgmii_phy3: ethernet-phy@3 {
 291                                         reg = <0x3>;
 292                                 };
 293                         };
 294
 295                         ls1021amdio3: mdio@60 {
 296                                 reg = <0x60>;
 297                                 #address-cells = <1>;
 298                                 #size-cells = <0>;
 299                                 sgmii_phy1c: ethernet-phy@1c {
 300                                         reg = <0x1c>;
 301                                 };
 302                         };
 303
 304                         ls1021amdio4: mdio@80 {
 305                                 reg = <0x80>;
 306                                 #address-cells = <1>;
 307                                 #size-cells = <0>;
 308                                 sgmii_phy1d: ethernet-phy@1d {
 309                                         reg = <0x1d>;
 310                                 };
 311                         };
 312                 };
 313         };
 314 };
 315
 316 &lpuart0 {
 317         status = "okay";
 318 };
 319
 320 &mdio0 {
 321         tbi0: tbi-phy@8 {
 322                 reg = <0x8>;
 323                 device_type = "tbi-phy";
 324         };
 325 };
 326
 327 &sai2 {
 328         status = "okay";
 329 };
 330
 331 &sata {
 332         status = "okay";
 333 };
 334
 335 &uart0 {
 336         status = "okay";
 337 };
 338
 339 &uart1 {
 340         status = "okay";
 341 };
 342
 343 &can0 {
 344         status = "okay";
 345 };
 346
 347 &can1 {
 348         status = "okay";
 349 };
 350
 351 &can2 {
 352         status = "disabled";
 353 };
 354
 355 &can3 {
 356         status = "disabled";
 357 };