arch/arm/boot/dts/ls1021a-qds.dts

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  * Copyright 2018 NXP
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of
  13  *     the License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  *     You should have received a copy of the GNU General Public
  21  *     License along with this file; if not, write to the Free
  22  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  23  *     MA 02110-1301 USA
  24  *
  25  * Or, alternatively,
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use,
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  */
  48
  49 /dts-v1/;
  50 #include "ls1021a.dtsi"
  51
  52 / {
  53         model = "LS1021A QDS Board";
  54
  55         aliases {
  56                 enet0_rgmii_phy = &rgmii_phy1;
  57                 enet1_rgmii_phy = &rgmii_phy2;
  58                 enet2_rgmii_phy = &rgmii_phy3;
  59                 enet0_sgmii_phy = &sgmii_phy1c;
  60                 enet1_sgmii_phy = &sgmii_phy1d;
  61         };
  62
  63         sys_mclk: clock-mclk {
  64                 compatible = "fixed-clock";
  65                 #clock-cells = <0>;
  66                 clock-frequency = <24576000>;
  67         };
  68
  69         regulators {
  70                 compatible = "simple-bus";
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74                 reg_3p3v: regulator@0 {
  75                         compatible = "regulator-fixed";
  76                         reg = <0>;
  77                         regulator-name = "3P3V";
  78                         regulator-min-microvolt = <3300000>;
  79                         regulator-max-microvolt = <3300000>;
  80                         regulator-always-on;
  81                 };
  82         };
  83
  84         sound {
  85                 compatible = "simple-audio-card";
  86                 simple-audio-card,format = "i2s";
  87                 simple-audio-card,widgets =
  88                         "Microphone", "Microphone Jack",
  89                         "Headphone", "Headphone Jack",
  90                         "Speaker", "Speaker Ext",
  91                         "Line", "Line In Jack";
  92                 simple-audio-card,routing =
  93                         "MIC_IN", "Microphone Jack",
  94                         "Microphone Jack", "Mic Bias",
  95                         "LINE_IN", "Line In Jack",
  96                         "Headphone Jack", "HP_OUT",
  97                         "Speaker Ext", "LINE_OUT";
  98
  99                 simple-audio-card,cpu {
 100                         sound-dai = <&sai2>;
 101                         frame-master;
 102                         bitclock-master;
 103                 };
 104
 105                 simple-audio-card,codec {
 106                         sound-dai = <&codec>;
 107                         frame-master;
 108                         bitclock-master;
 109                 };
 110         };
 111 };
 112
 113 &dspi0 {
 114         bus-num = <0>;
 115         status = "okay";
 116
 117         dspiflash: at45db021d@0 {
 118                 #address-cells = <1>;
 119                 #size-cells = <1>;
 120                 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
 121                 spi-max-frequency = <16000000>;
 122                 spi-cpol;
 123                 spi-cpha;
 124                 reg = <0>;
 125         };
 126 };
 127
 128 &enet0 {
 129         tbi-handle = <&tbi0>;
 130         phy-handle = <&sgmii_phy1c>;
 131         phy-connection-type = "sgmii";
 132         status = "okay";
 133 };
 134
 135 &enet1 {
 136         tbi-handle = <&tbi0>;
 137         phy-handle = <&sgmii_phy1d>;
 138         phy-connection-type = "sgmii";
 139         status = "okay";
 140 };
 141
 142 &enet2 {
 143         phy-handle = <&rgmii_phy3>;
 144         phy-connection-type = "rgmii-id";
 145         status = "okay";
 146 };
 147
 148 &i2c0 {
 149         status = "okay";
 150
 151         pca9547: mux@77 {
 152                 compatible = "nxp,pca9547";
 153                 reg = <0x77>;
 154                 #address-cells = <1>;
 155                 #size-cells = <0>;
 156
 157                 i2c@0 {
 158                         #address-cells = <1>;
 159                         #size-cells = <0>;
 160                         reg = <0x0>;
 161
 162                         ds3232: rtc@68 {
 163                                 compatible = "dallas,ds3232";
 164                                 reg = <0x68>;
 165                                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 166                         };
 167                 };
 168
 169                 i2c@2 {
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         reg = <0x2>;
 173
 174                         ina220@40 {
 175                                 compatible = "ti,ina220";
 176                                 reg = <0x40>;
 177                                 shunt-resistor = <1000>;
 178                         };
 179
 180                         ina220@41 {
 181                                 compatible = "ti,ina220";
 182                                 reg = <0x41>;
 183                                 shunt-resistor = <1000>;
 184                         };
 185                 };
 186
 187                 i2c@3 {
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         reg = <0x3>;
 191
 192                         eeprom@56 {
 193                                 compatible = "atmel,24c512";
 194                                 reg = <0x56>;
 195                         };
 196
 197                         eeprom@57 {
 198                                 compatible = "atmel,24c512";
 199                                 reg = <0x57>;
 200                         };
 201
 202                         adt7461a@4c {
 203                                 compatible = "adi,adt7461a";
 204                                 reg = <0x4c>;
 205                         };
 206                 };
 207
 208                 i2c@4 {
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                         reg = <0x4>;
 212
 213                         codec: sgtl5000@2a {
 214                                 #sound-dai-cells = <0>;
 215                                 compatible = "fsl,sgtl5000";
 216                                 reg = <0x2a>;
 217                                 VDDA-supply = <&reg_3p3v>;
 218                                 VDDIO-supply = <&reg_3p3v>;
 219                                 clocks = <&sys_mclk>;
 220                         };
 221                 };
 222         };
 223 };
 224
 225 &ifc {
 226         #address-cells = <2>;
 227         #size-cells = <1>;
 228         /* NOR, NAND Flashes and FPGA on board */
 229         ranges = <0x0 0x0 0x0 0x60000000 0x08000000
 230                   0x2 0x0 0x0 0x7e800000 0x00010000
 231                   0x3 0x0 0x0 0x7fb00000 0x00000100>;
 232         status = "okay";
 233
 234         nor@0,0 {
 235                 #address-cells = <1>;
 236                 #size-cells = <1>;
 237                 compatible = "cfi-flash";
 238                 reg = <0x0 0x0 0x8000000>;
 239                 big-endian;
 240                 bank-width = <2>;
 241                 device-width = <1>;
 242         };
 243
 244         nand@2,0 {
 245                 compatible = "fsl,ifc-nand";
 246                 reg = <0x2 0x0 0x10000>;
 247         };
 248
 249         fpga: board-control@3,0 {
 250                 #address-cells = <1>;
 251                 #size-cells = <1>;
 252                 compatible = "simple-bus";
 253                 reg = <0x3 0x0 0x0000100>;
 254                 bank-width = <1>;
 255                 device-width = <1>;
 256                 ranges = <0 3 0 0x100>;
 257
 258                 mdio-mux-emi1 {
 259                         compatible = "mdio-mux-mmioreg";
 260                         mdio-parent-bus = <&mdio0>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         reg = <0x54 1>; /* BRDCFG4 */
 264                         mux-mask = <0xe0>; /* EMI1[2:0] */
 265
 266                         /* Onboard PHYs */
 267                         ls1021amdio0: mdio@0 {
 268                                 reg = <0>;
 269                                 #address-cells = <1>;
 270                                 #size-cells = <0>;
 271                                 rgmii_phy1: ethernet-phy@1 {
 272                                         reg = <0x1>;
 273                                 };
 274                         };
 275
 276                         ls1021amdio1: mdio@20 {
 277                                 reg = <0x20>;
 278                                 #address-cells = <1>;
 279                                 #size-cells = <0>;
 280                                 rgmii_phy2: ethernet-phy@2 {
 281                                         reg = <0x2>;
 282                                 };
 283                         };
 284
 285                         ls1021amdio2: mdio@40 {
 286                                 reg = <0x40>;
 287                                 #address-cells = <1>;
 288                                 #size-cells = <0>;
 289                                 rgmii_phy3: ethernet-phy@3 {
 290                                         reg = <0x3>;
 291                                 };
 292                         };
 293
 294                         ls1021amdio3: mdio@60 {
 295                                 reg = <0x60>;
 296                                 #address-cells = <1>;
 297                                 #size-cells = <0>;
 298                                 sgmii_phy1c: ethernet-phy@1c {
 299                                         reg = <0x1c>;
 300                                 };
 301                         };
 302
 303                         ls1021amdio4: mdio@80 {
 304                                 reg = <0x80>;
 305                                 #address-cells = <1>;
 306                                 #size-cells = <0>;
 307                                 sgmii_phy1d: ethernet-phy@1d {
 308                                         reg = <0x1d>;
 309                                 };
 310                         };
 311                 };
 312         };
 313 };
 314
 315 &lpuart0 {
 316         status = "okay";
 317 };
 318
 319 &mdio0 {
 320         tbi0: tbi-phy@8 {
 321                 reg = <0x8>;
 322                 device_type = "tbi-phy";
 323         };
 324 };
 325
 326 &sai2 {
 327         status = "okay";
 328 };
 329
 330 &sata {
 331         status = "okay";
 332 };
 333
 334 &uart0 {
 335         status = "okay";
 336 };
 337
 338 &uart1 {
 339         status = "okay";
 340 };
 341
 342 &can0 {
 343         status = "okay";
 344 };
 345
 346 &can1 {
 347         status = "okay";
 348 };
 349
 350 &can2 {
 351         status = "disabled";
 352 };
 353
 354 &can3 {
 355         status = "disabled";
 356 };