arch/arm/boot/dts/lpc32xx.dtsi

   1 /*
   2  * NXP LPC32xx SoC
   3  *
   4  * Copyright 2012 Roland Stigge <stigge@antcom.de>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "skeleton.dtsi"
  15
  16 #include <dt-bindings/clock/lpc32xx-clock.h>
  17 #include <dt-bindings/interrupt-controller/irq.h>
  18
  19 / {
  20         compatible = "nxp,lpc3220";
  21         interrupt-parent = <&mic>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu@0 {
  28                         compatible = "arm,arm926ej-s";
  29                         device_type = "cpu";
  30                         reg = <0x0>;
  31                 };
  32         };
  33
  34         clocks {
  35                 xtal_32k: xtal_32k {
  36                         compatible = "fixed-clock";
  37                         #clock-cells = <0>;
  38                         clock-frequency = <32768>;
  39                         clock-output-names = "xtal_32k";
  40                 };
  41
  42                 xtal: xtal {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <13000000>;
  46                         clock-output-names = "xtal";
  47                 };
  48         };
  49
  50         ahb {
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 compatible = "simple-bus";
  54                 ranges = <0x20000000 0x20000000 0x30000000>,
  55                          <0xe0000000 0xe0000000 0x04000000>;
  56
  57                 /*
  58                  * Enable either SLC or MLC
  59                  */
  60                 slc: flash@20020000 {
  61                         compatible = "nxp,lpc3220-slc";
  62                         reg = <0x20020000 0x1000>;
  63                         clocks = <&clk LPC32XX_CLK_SLC>;
  64                         status = "disabled";
  65                 };
  66
  67                 mlc: flash@200a8000 {
  68                         compatible = "nxp,lpc3220-mlc";
  69                         reg = <0x200a8000 0x11000>;
  70                         interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
  71                         clocks = <&clk LPC32XX_CLK_MLC>;
  72                         status = "disabled";
  73                 };
  74
  75                 dma: dma@31000000 {
  76                         compatible = "arm,pl080", "arm,primecell";
  77                         reg = <0x31000000 0x1000>;
  78                         interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
  79                         clocks = <&clk LPC32XX_CLK_DMA>;
  80                         clock-names = "apb_pclk";
  81                 };
  82
  83                 usb {
  84                         #address-cells = <1>;
  85                         #size-cells = <1>;
  86                         compatible = "simple-bus";
  87                         ranges = <0x0 0x31020000 0x00001000>;
  88
  89                         /*
  90                          * Enable either ohci or usbd (gadget)!
  91                          */
  92                         ohci: ohci@0 {
  93                                 compatible = "nxp,ohci-nxp", "usb-ohci";
  94                                 reg = <0x0 0x300>;
  95                                 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
  96                                 clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
  97                                 status = "disabled";
  98                         };
  99
 100                         usbd: usbd@0 {
 101                                 compatible = "nxp,lpc3220-udc";
 102                                 reg = <0x0 0x300>;
 103                                 interrupts = <61 IRQ_TYPE_LEVEL_HIGH>,
 104                                              <62 IRQ_TYPE_LEVEL_HIGH>,
 105                                              <60 IRQ_TYPE_LEVEL_HIGH>,
 106                                              <58 IRQ_TYPE_LEVEL_LOW>;
 107                                 clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
 108                                 status = "disabled";
 109                         };
 110
 111                         i2cusb: i2c@300 {
 112                                 compatible = "nxp,pnx-i2c";
 113                                 reg = <0x300 0x100>;
 114                                 interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
 115                                 clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
 116                                 #address-cells = <1>;
 117                                 #size-cells = <0>;
 118                                 pnx,timeout = <0x64>;
 119                         };
 120
 121                         usbclk: clock-controller@f00 {
 122                                 compatible = "nxp,lpc3220-usb-clk";
 123                                 reg = <0xf00 0x100>;
 124                                 #clock-cells = <1>;
 125                         };
 126                 };
 127
 128                 clcd: clcd@31040000 {
 129                         compatible = "arm,pl110", "arm,primecell";
 130                         reg = <0x31040000 0x1000>;
 131                         interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
 132                         clocks = <&clk LPC32XX_CLK_LCD>;
 133                         clock-names = "apb_pclk";
 134                         status = "disabled";
 135                 };
 136
 137                 mac: ethernet@31060000 {
 138                         compatible = "nxp,lpc-eth";
 139                         reg = <0x31060000 0x1000>;
 140                         interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
 141                         clocks = <&clk LPC32XX_CLK_MAC>;
 142                 };
 143
 144                 emc: memory-controller@31080000 {
 145                         compatible = "arm,pl175", "arm,primecell";
 146                         reg = <0x31080000 0x1000>;
 147                         clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
 148                         clock-names = "mpmcclk", "apb_pclk";
 149                         #address-cells = <1>;
 150                         #size-cells = <1>;
 151
 152                         ranges = <0 0xe0000000 0x01000000>,
 153                                  <1 0xe1000000 0x01000000>,
 154                                  <2 0xe2000000 0x01000000>,
 155                                  <3 0xe3000000 0x01000000>;
 156                         status = "disabled";
 157                 };
 158
 159                 apb {
 160                         #address-cells = <1>;
 161                         #size-cells = <1>;
 162                         compatible = "simple-bus";
 163                         ranges = <0x20000000 0x20000000 0x30000000>;
 164
 165                         ssp0: ssp@20084000 {
 166                                 compatible = "arm,pl022", "arm,primecell";
 167                                 reg = <0x20084000 0x1000>;
 168                                 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 169                                 clocks = <&clk LPC32XX_CLK_SSP0>;
 170                                 clock-names = "apb_pclk";
 171                         };
 172
 173                         spi1: spi@20088000 {
 174                                 compatible = "nxp,lpc3220-spi";
 175                                 reg = <0x20088000 0x1000>;
 176                         };
 177
 178                         ssp1: ssp@2008c000 {
 179                                 compatible = "arm,pl022", "arm,primecell";
 180                                 reg = <0x2008c000 0x1000>;
 181                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
 182                                 clocks = <&clk LPC32XX_CLK_SSP1>;
 183                                 clock-names = "apb_pclk";
 184                         };
 185
 186                         spi2: spi@20090000 {
 187                                 compatible = "nxp,lpc3220-spi";
 188                                 reg = <0x20090000 0x1000>;
 189                         };
 190
 191                         i2s0: i2s@20094000 {
 192                                 compatible = "nxp,lpc3220-i2s";
 193                                 reg = <0x20094000 0x1000>;
 194                         };
 195
 196                         sd: sd@20098000 {
 197                                 compatible = "arm,pl18x", "arm,primecell";
 198                                 reg = <0x20098000 0x1000>;
 199                                 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
 200                                              <13 IRQ_TYPE_LEVEL_HIGH>;
 201                                 clocks = <&clk LPC32XX_CLK_SD>;
 202                                 clock-names = "apb_pclk";
 203                                 status = "disabled";
 204                         };
 205
 206                         i2s1: i2s@2009C000 {
 207                                 compatible = "nxp,lpc3220-i2s";
 208                                 reg = <0x2009C000 0x1000>;
 209                         };
 210
 211                         /* UART5 first since it is the default console, ttyS0 */
 212                         uart5: serial@40090000 {
 213                                 /* actually, ns16550a w/ 64 byte fifos! */
 214                                 compatible = "nxp,lpc3220-uart";
 215                                 reg = <0x40090000 0x1000>;
 216                                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
 217                                 reg-shift = <2>;
 218                                 clocks = <&clk LPC32XX_CLK_UART5>;
 219                                 status = "disabled";
 220                         };
 221
 222                         uart3: serial@40080000 {
 223                                 compatible = "nxp,lpc3220-uart";
 224                                 reg = <0x40080000 0x1000>;
 225                                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 226                                 reg-shift = <2>;
 227                                 clocks = <&clk LPC32XX_CLK_UART3>;
 228                                 status = "disabled";
 229                         };
 230
 231                         uart4: serial@40088000 {
 232                                 compatible = "nxp,lpc3220-uart";
 233                                 reg = <0x40088000 0x1000>;
 234                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 235                                 reg-shift = <2>;
 236                                 clocks = <&clk LPC32XX_CLK_UART4>;
 237                                 status = "disabled";
 238                         };
 239
 240                         uart6: serial@40098000 {
 241                                 compatible = "nxp,lpc3220-uart";
 242                                 reg = <0x40098000 0x1000>;
 243                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
 244                                 reg-shift = <2>;
 245                                 clocks = <&clk LPC32XX_CLK_UART6>;
 246                                 status = "disabled";
 247                         };
 248
 249                         i2c1: i2c@400A0000 {
 250                                 compatible = "nxp,pnx-i2c";
 251                                 reg = <0x400A0000 0x100>;
 252                                 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
 253                                 #address-cells = <1>;
 254                                 #size-cells = <0>;
 255                                 pnx,timeout = <0x64>;
 256                                 clocks = <&clk LPC32XX_CLK_I2C1>;
 257                         };
 258
 259                         i2c2: i2c@400A8000 {
 260                                 compatible = "nxp,pnx-i2c";
 261                                 reg = <0x400A8000 0x100>;
 262                                 interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
 263                                 #address-cells = <1>;
 264                                 #size-cells = <0>;
 265                                 pnx,timeout = <0x64>;
 266                                 clocks = <&clk LPC32XX_CLK_I2C2>;
 267                         };
 268
 269                         mpwm: mpwm@400E8000 {
 270                                 compatible = "nxp,lpc3220-motor-pwm";
 271                                 reg = <0x400E8000 0x78>;
 272                                 status = "disabled";
 273                                 #pwm-cells = <2>;
 274                         };
 275                 };
 276
 277                 fab {
 278                         #address-cells = <1>;
 279                         #size-cells = <1>;
 280                         compatible = "simple-bus";
 281                         ranges = <0x20000000 0x20000000 0x30000000>;
 282
 283                         /* System Control Block */
 284                         scb {
 285                                 compatible = "simple-bus";
 286                                 ranges = <0x0 0x040004000 0x00001000>;
 287                                 #address-cells = <1>;
 288                                 #size-cells = <1>;
 289
 290                                 clk: clock-controller@0 {
 291                                         compatible = "nxp,lpc3220-clk";
 292                                         reg = <0x00 0x114>;
 293                                         #clock-cells = <1>;
 294
 295                                         clocks = <&xtal_32k>, <&xtal>;
 296                                         clock-names = "xtal_32k", "xtal";
 297                                 };
 298                         };
 299
 300                         /*
 301                          * MIC Interrupt controller includes:
 302                          *   MIC @40008000
 303                          *   SIC1 @4000C000
 304                          *   SIC2 @40010000
 305                          */
 306                         mic: interrupt-controller@40008000 {
 307                                 compatible = "nxp,lpc3220-mic";
 308                                 interrupt-controller;
 309                                 reg = <0x40008000 0xC000>;
 310                                 #interrupt-cells = <2>;
 311                         };
 312
 313                         uart1: serial@40014000 {
 314                                 compatible = "nxp,lpc3220-hsuart";
 315                                 reg = <0x40014000 0x1000>;
 316                                 interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
 317                                 status = "disabled";
 318                         };
 319
 320                         uart2: serial@40018000 {
 321                                 compatible = "nxp,lpc3220-hsuart";
 322                                 reg = <0x40018000 0x1000>;
 323                                 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
 324                                 status = "disabled";
 325                         };
 326
 327                         uart7: serial@4001c000 {
 328                                 compatible = "nxp,lpc3220-hsuart";
 329                                 reg = <0x4001c000 0x1000>;
 330                                 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
 331                                 status = "disabled";
 332                         };
 333
 334                         rtc: rtc@40024000 {
 335                                 compatible = "nxp,lpc3220-rtc";
 336                                 reg = <0x40024000 0x1000>;
 337                                 interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
 338                                 clocks = <&clk LPC32XX_CLK_RTC>;
 339                         };
 340
 341                         gpio: gpio@40028000 {
 342                                 compatible = "nxp,lpc3220-gpio";
 343                                 reg = <0x40028000 0x1000>;
 344                                 gpio-controller;
 345                                 #gpio-cells = <3>; /* bank, pin, flags */
 346                         };
 347
 348                         timer4: timer@4002C000 {
 349                                 compatible = "nxp,lpc3220-timer";
 350                                 reg = <0x4002C000 0x1000>;
 351                                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 352                                 clocks = <&clk LPC32XX_CLK_TIMER4>;
 353                                 clock-names = "timerclk";
 354                                 status = "disabled";
 355                         };
 356
 357                         timer5: timer@40030000 {
 358                                 compatible = "nxp,lpc3220-timer";
 359                                 reg = <0x40030000 0x1000>;
 360                                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 361                                 clocks = <&clk LPC32XX_CLK_TIMER5>;
 362                                 clock-names = "timerclk";
 363                                 status = "disabled";
 364                         };
 365
 366                         watchdog: watchdog@4003C000 {
 367                                 compatible = "nxp,pnx4008-wdt";
 368                                 reg = <0x4003C000 0x1000>;
 369                                 clocks = <&clk LPC32XX_CLK_WDOG>;
 370                         };
 371
 372                         timer0: timer@40044000 {
 373                                 compatible = "nxp,lpc3220-timer";
 374                                 reg = <0x40044000 0x1000>;
 375                                 clocks = <&clk LPC32XX_CLK_TIMER0>;
 376                                 clock-names = "timerclk";
 377                                 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
 378                         };
 379
 380                         /*
 381                          * TSC vs. ADC: Since those two share the same
 382                          * hardware, you need to choose from one of the
 383                          * following two and do 'status = "okay";' for one of
 384                          * them
 385                          */
 386
 387                         adc: adc@40048000 {
 388                                 compatible = "nxp,lpc3220-adc";
 389                                 reg = <0x40048000 0x1000>;
 390                                 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
 391                                 clocks = <&clk LPC32XX_CLK_ADC>;
 392                                 status = "disabled";
 393                         };
 394
 395                         tsc: tsc@40048000 {
 396                                 compatible = "nxp,lpc3220-tsc";
 397                                 reg = <0x40048000 0x1000>;
 398                                 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
 399                                 clocks = <&clk LPC32XX_CLK_ADC>;
 400                                 status = "disabled";
 401                         };
 402
 403                         timer1: timer@4004C000 {
 404                                 compatible = "nxp,lpc3220-timer";
 405                                 reg = <0x4004C000 0x1000>;
 406                                 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
 407                                 clocks = <&clk LPC32XX_CLK_TIMER1>;
 408                                 clock-names = "timerclk";
 409                         };
 410
 411                         key: key@40050000 {
 412                                 compatible = "nxp,lpc3220-key";
 413                                 reg = <0x40050000 0x1000>;
 414                                 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
 415                                 status = "disabled";
 416                         };
 417
 418                         timer2: timer@40058000 {
 419                                 compatible = "nxp,lpc3220-timer";
 420                                 reg = <0x40058000 0x1000>;
 421                                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 422                                 clocks = <&clk LPC32XX_CLK_TIMER2>;
 423                                 clock-names = "timerclk";
 424                                 status = "disabled";
 425                         };
 426
 427                         pwm1: pwm@4005C000 {
 428                                 compatible = "nxp,lpc3220-pwm";
 429                                 reg = <0x4005C000 0x4>;
 430                                 clocks = <&clk LPC32XX_CLK_PWM1>;
 431                                 status = "disabled";
 432                         };
 433
 434                         pwm2: pwm@4005C004 {
 435                                 compatible = "nxp,lpc3220-pwm";
 436                                 reg = <0x4005C004 0x4>;
 437                                 clocks = <&clk LPC32XX_CLK_PWM2>;
 438                                 status = "disabled";
 439                         };
 440
 441                         timer3: timer@40060000 {
 442                                 compatible = "nxp,lpc3220-timer";
 443                                 reg = <0x40060000 0x1000>;
 444                                 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 445                                 clocks = <&clk LPC32XX_CLK_TIMER3>;
 446                                 clock-names = "timerclk";
 447                                 status = "disabled";
 448                         };
 449                 };
 450         };
 451 };