arch/arm/boot/dts/lpc18xx.dtsi

   1 /*
   2  * Common base for NXP LPC18xx and LPC43xx devices.
   3  *
   4  * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
   5  *
   6  * This code is released using a dual license strategy: BSD/GPL
   7  * You can choose the licence that better fits your requirements.
   8  *
   9  * Released under the terms of 3-clause BSD License
  10  * Released under the terms of GNU General Public License Version 2.0
  11  *
  12  */
  13
  14 #include "armv7-m.dtsi"
  15
  16 #include "dt-bindings/clock/lpc18xx-cgu.h"
  17 #include "dt-bindings/clock/lpc18xx-ccu.h"
  18
  19 #define LPC_PIN(port, pin)      (0x##port * 32 + pin)
  20 #define LPC_GPIO(port, pin)     (port * 32 + pin)
  21
  22 / {
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu@0 {
  28                         compatible = "arm,cortex-m3";
  29                         device_type = "cpu";
  30                         reg = <0x0>;
  31                         clocks = <&ccu1 CLK_CPU_CORE>;
  32                 };
  33         };
  34
  35         clocks {
  36                 xtal: xtal {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <12000000>;
  40                 };
  41
  42                 xtal32: xtal32 {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <32768>;
  46                 };
  47
  48                 enet_rx_clk: enet_rx_clk {
  49                         compatible = "fixed-clock";
  50                         #clock-cells = <0>;
  51                         clock-frequency = <0>;
  52                         clock-output-names = "enet_rx_clk";
  53                 };
  54
  55                 enet_tx_clk: enet_tx_clk {
  56                         compatible = "fixed-clock";
  57                         #clock-cells = <0>;
  58                         clock-frequency = <0>;
  59                         clock-output-names = "enet_tx_clk";
  60                 };
  61
  62                 gp_clkin: gp_clkin {
  63                         compatible = "fixed-clock";
  64                         #clock-cells = <0>;
  65                         clock-frequency = <0>;
  66                         clock-output-names = "gp_clkin";
  67                 };
  68         };
  69
  70         soc {
  71                 mmcsd: mmcsd@40004000 {
  72                         compatible = "snps,dw-mshc";
  73                         reg = <0x40004000 0x1000>;
  74                         interrupts = <6>;
  75                         num-slots = <1>;
  76                         clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
  77                         clock-names = "ciu", "biu";
  78                         status = "disabled";
  79                 };
  80
  81                 usb0: ehci@40006100 {
  82                         compatible = "nxp,lpc1850-ehci", "generic-ehci";
  83                         reg = <0x40006100 0x100>;
  84                         interrupts = <8>;
  85                         clocks = <&ccu1 CLK_CPU_USB0>;
  86                         phys = <&usb0_otg_phy>;
  87                         phy-names = "usb";
  88                         has-transaction-translator;
  89                         status = "disabled";
  90                 };
  91
  92                 usb1: ehci@40007100 {
  93                         compatible = "nxp,lpc1850-ehci", "generic-ehci";
  94                         reg = <0x40007100 0x100>;
  95                         interrupts = <9>;
  96                         clocks = <&ccu1 CLK_CPU_USB1>;
  97                         status = "disabled";
  98                 };
  99
 100                 emc: memory-controller@40005000 {
 101                         compatible = "arm,pl172", "arm,primecell";
 102                         reg = <0x40005000 0x1000>;
 103                         clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
 104                         clock-names = "mpmcclk", "apb_pclk";
 105                         #address-cells = <2>;
 106                         #size-cells = <1>;
 107                         ranges = <0 0 0x1c000000 0x1000000
 108                                   1 0 0x1d000000 0x1000000
 109                                   2 0 0x1e000000 0x1000000
 110                                   3 0 0x1f000000 0x1000000>;
 111                         status = "disabled";
 112                 };
 113
 114                 lcdc: lcd-controller@40008000 {
 115                         compatible = "arm,pl111", "arm,primecell";
 116                         reg = <0x40008000 0x1000>;
 117                         interrupts = <7>;
 118                         interrupt-names = "combined";
 119                         clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
 120                         clock-names = "clcdclk", "apb_pclk";
 121                         status = "disabled";
 122                 };
 123
 124                 mac: ethernet@40010000 {
 125                         compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
 126                         reg = <0x40010000 0x2000>;
 127                         interrupts = <5>;
 128                         interrupt-names = "macirq";
 129                         clocks = <&ccu1 CLK_CPU_ETHERNET>;
 130                         clock-names = "stmmaceth";
 131                         status = "disabled";
 132                 };
 133
 134                 creg: syscon@40043000 {
 135                         compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
 136                         reg = <0x40043000 0x1000>;
 137                         clocks = <&ccu1 CLK_CPU_CREG>;
 138
 139                         usb0_otg_phy: phy@004 {
 140                                 compatible = "nxp,lpc1850-usb-otg-phy";
 141                                 clocks = <&ccu1 CLK_USB0>;
 142                                 #phy-cells = <0>;
 143                         };
 144                 };
 145
 146                 cgu: clock-controller@40050000 {
 147                         compatible = "nxp,lpc1850-cgu";
 148                         reg = <0x40050000 0x1000>;
 149                         #clock-cells = <1>;
 150                         clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
 151                 };
 152
 153                 ccu1: clock-controller@40051000 {
 154                         compatible = "nxp,lpc1850-ccu";
 155                         reg = <0x40051000 0x1000>;
 156                         #clock-cells = <1>;
 157                         clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
 158                                  <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
 159                                  <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
 160                                  <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
 161                         clock-names = "base_apb3_clk",   "base_apb1_clk",
 162                                       "base_spifi_clk",  "base_cpu_clk",
 163                                       "base_periph_clk", "base_usb0_clk",
 164                                       "base_usb1_clk",   "base_spi_clk";
 165                 };
 166
 167                 ccu2: clock-controller@40052000 {
 168                         compatible = "nxp,lpc1850-ccu";
 169                         reg = <0x40052000 0x1000>;
 170                         #clock-cells = <1>;
 171                         clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
 172                                  <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
 173                                  <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
 174                                  <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
 175                         clock-names = "base_audio_clk", "base_uart3_clk",
 176                                       "base_uart2_clk", "base_uart1_clk",
 177                                       "base_uart0_clk", "base_ssp1_clk",
 178                                       "base_ssp0_clk",  "base_sdio_clk";
 179                 };
 180
 181                 uart0: serial@40081000 {
 182                         compatible = "nxp,lpc1850-uart", "ns16550a";
 183                         reg = <0x40081000 0x1000>;
 184                         reg-shift = <2>;
 185                         interrupts = <24>;
 186                         clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
 187                         clock-names = "uartclk", "reg";
 188                         status = "disabled";
 189                 };
 190
 191                 uart1: serial@40082000 {
 192                         compatible = "nxp,lpc1850-uart", "ns16550a";
 193                         reg = <0x40082000 0x1000>;
 194                         reg-shift = <2>;
 195                         interrupts = <25>;
 196                         clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
 197                         clock-names = "uartclk", "reg";
 198                         status = "disabled";
 199                 };
 200
 201                 ssp0: spi@40083000 {
 202                         compatible = "arm,pl022", "arm,primecell";
 203                         reg = <0x40083000 0x1000>;
 204                         interrupts = <22>;
 205                         clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
 206                         clock-names = "sspclk", "apb_pclk";
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         status = "disabled";
 210                 };
 211
 212                 timer0: timer@40084000 {
 213                         compatible = "nxp,lpc3220-timer";
 214                         reg = <0x40084000 0x1000>;
 215                         interrupts = <12>;
 216                         clocks = <&ccu1 CLK_CPU_TIMER0>;
 217                         clock-names = "timerclk";
 218                 };
 219
 220                 timer1: timer@40085000 {
 221                         compatible = "nxp,lpc3220-timer";
 222                         reg = <0x40085000 0x1000>;
 223                         interrupts = <13>;
 224                         clocks = <&ccu1 CLK_CPU_TIMER1>;
 225                         clock-names = "timerclk";
 226                 };
 227
 228                 pinctrl: pinctrl@40086000 {
 229                         compatible = "nxp,lpc1850-scu";
 230                         reg = <0x40086000 0x1000>;
 231                         clocks = <&ccu1 CLK_CPU_SCU>;
 232                 };
 233
 234                 can1: can@400a4000 {
 235                         compatible = "bosch,c_can";
 236                         reg = <0x400a4000 0x1000>;
 237                         interrupts = <43>;
 238                         clocks = <&ccu1 CLK_APB1_CAN1>;
 239                         status = "disabled";
 240                 };
 241
 242                 uart2: serial@400c1000 {
 243                         compatible = "nxp,lpc1850-uart", "ns16550a";
 244                         reg = <0x400c1000 0x1000>;
 245                         reg-shift = <2>;
 246                         interrupts = <26>;
 247                         clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
 248                         clock-names = "uartclk", "reg";
 249                         status = "disabled";
 250                 };
 251
 252                 uart3: serial@400c2000 {
 253                         compatible = "nxp,lpc1850-uart", "ns16550a";
 254                         reg = <0x400c2000 0x1000>;
 255                         reg-shift = <2>;
 256                         interrupts = <27>;
 257                         clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
 258                         clock-names = "uartclk", "reg";
 259                         status = "disabled";
 260                 };
 261
 262                 timer2: timer@400c3000 {
 263                         compatible = "nxp,lpc3220-timer";
 264                         reg = <0x400c3000 0x1000>;
 265                         interrupts = <14>;
 266                         clocks = <&ccu1 CLK_CPU_TIMER2>;
 267                         clock-names = "timerclk";
 268                 };
 269
 270                 timer3: timer@400c4000 {
 271                         compatible = "nxp,lpc3220-timer";
 272                         reg = <0x400c4000 0x1000>;
 273                         interrupts = <15>;
 274                         clocks = <&ccu1 CLK_CPU_TIMER3>;
 275                         clock-names = "timerclk";
 276                 };
 277
 278                 ssp1: spi@400c5000 {
 279                         compatible = "arm,pl022", "arm,primecell";
 280                         reg = <0x400c5000 0x1000>;
 281                         interrupts = <23>;
 282                         clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
 283                         clock-names = "sspclk", "apb_pclk";
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                         status = "disabled";
 287                 };
 288
 289                 can0: can@400e2000 {
 290                         compatible = "bosch,c_can";
 291                         reg = <0x400e2000 0x1000>;
 292                         interrupts = <51>;
 293                         clocks = <&ccu1 CLK_APB3_CAN0>;
 294                         status = "disabled";
 295                 };
 296
 297                 gpio: gpio@400f4000 {
 298                         compatible = "nxp,lpc1850-gpio";
 299                         reg = <0x400f4000 0x4000>;
 300                         clocks = <&ccu1 CLK_CPU_GPIO>;
 301                         gpio-controller;
 302                         #gpio-cells = <2>;
 303                         gpio-ranges =   <&pinctrl LPC_GPIO(0,0)  LPC_PIN(0,0)  2>,
 304                                         <&pinctrl LPC_GPIO(0,4)  LPC_PIN(1,0)  1>,
 305                                         <&pinctrl LPC_GPIO(0,8)  LPC_PIN(1,1)  4>,
 306                                         <&pinctrl LPC_GPIO(1,8)  LPC_PIN(1,5)  2>,
 307                                         <&pinctrl LPC_GPIO(1,0)  LPC_PIN(1,7)  8>,
 308                                         <&pinctrl LPC_GPIO(0,2)  LPC_PIN(1,15) 2>,
 309                                         <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
 310                                         <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
 311                                         <&pinctrl LPC_GPIO(5,0)  LPC_PIN(2,0)  7>,
 312                                         <&pinctrl LPC_GPIO(0,7)  LPC_PIN(2,7)  1>,
 313                                         <&pinctrl LPC_GPIO(5,7)  LPC_PIN(2,8)  1>,
 314                                         <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9)  1>,
 315                                         <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
 316                                         <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
 317                                         <&pinctrl LPC_GPIO(5,8)  LPC_PIN(3,1)  2>,
 318                                         <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4)  2>,
 319                                         <&pinctrl LPC_GPIO(0,6)  LPC_PIN(3,6)  1>,
 320                                         <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7)  2>,
 321                                         <&pinctrl LPC_GPIO(2,0)  LPC_PIN(4,0)  7>,
 322                                         <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8)  3>,
 323                                         <&pinctrl LPC_GPIO(2,9)  LPC_PIN(5,0)  7>,
 324                                         <&pinctrl LPC_GPIO(2,7)  LPC_PIN(5,7)  1>,
 325                                         <&pinctrl LPC_GPIO(3,0)  LPC_PIN(6,1)  5>,
 326                                         <&pinctrl LPC_GPIO(0,5)  LPC_PIN(6,6)  1>,
 327                                         <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7)  2>,
 328                                         <&pinctrl LPC_GPIO(3,5)  LPC_PIN(6,9)  3>,
 329                                         <&pinctrl LPC_GPIO(2,8)  LPC_PIN(6,12) 1>,
 330                                         <&pinctrl LPC_GPIO(3,8)  LPC_PIN(7,0)  8>,
 331                                         <&pinctrl LPC_GPIO(4,0)  LPC_PIN(8,0)  8>,
 332                                         <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0)  4>,
 333                                         <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4)  2>,
 334                                         <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6)  1>,
 335                                         <&pinctrl LPC_GPIO(4,8)  LPC_PIN(a,1)  3>,
 336                                         <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4)  1>,
 337                                         <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0)  7>,
 338                                         <&pinctrl LPC_GPIO(6,0)  LPC_PIN(c,1) 14>,
 339                                         <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
 340                                         <&pinctrl LPC_GPIO(7,0)  LPC_PIN(e,0) 16>,
 341                                         <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1)  3>,
 342                                         <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5)  7>;
 343                 };
 344         };
 345 };