arch/arm/boot/dts/logicpd-torpedo-som.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #include <dt-bindings/input/input.h>
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart1;
  12         };
  13
  14         cpus {
  15                 cpu@0 {
  16                         cpu0-supply = <&vcc>;
  17                 };
  18         };
  19
  20         memory@80000000 {
  21                 device_type = "memory";
  22                 reg = <0x80000000 0>;
  23         };
  24
  25         leds {
  26                 compatible = "gpio-leds";
  27                 user0 {
  28                         label = "user0";
  29                         gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
  30                         linux,default-trigger = "none";
  31                 };
  32         };
  33 };
  34
  35 &gpmc {
  36         ranges = <0 0 0x30000000 0x1000000>;    /* CS0: 16MB for NAND */
  37
  38         nand@0,0 {
  39                 compatible = "ti,omap2-nand";
  40                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  41                 interrupt-parent = <&gpmc>;
  42                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  43                              <1 IRQ_TYPE_NONE>; /* termcount */
  44                 linux,mtd-name = "micron,mt29f4g16abbda3w";
  45                 nand-bus-width = <16>;
  46                 ti,nand-ecc-opt = "bch8";
  47                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  48                 gpmc,sync-clk-ps = <0>;
  49                 gpmc,cs-on-ns = <0>;
  50                 gpmc,cs-rd-off-ns = <44>;
  51                 gpmc,cs-wr-off-ns = <44>;
  52                 gpmc,adv-on-ns = <6>;
  53                 gpmc,adv-rd-off-ns = <34>;
  54                 gpmc,adv-wr-off-ns = <44>;
  55                 gpmc,we-off-ns = <40>;
  56                 gpmc,oe-off-ns = <54>;
  57                 gpmc,access-ns = <64>;
  58                 gpmc,rd-cycle-ns = <82>;
  59                 gpmc,wr-cycle-ns = <82>;
  60                 gpmc,wr-access-ns = <40>;
  61                 gpmc,wr-data-mux-bus-ns = <0>;
  62                 gpmc,device-width = <2>;
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65         };
  66 };
  67
  68 &i2c1 {
  69         clock-frequency = <2600000>;
  70
  71         twl: twl@48 {
  72                 reg = <0x48>;
  73                 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  74                 interrupt-parent = <&intc>;
  75                 twl_audio: audio {
  76                         compatible = "ti,twl4030-audio";
  77                         codec {
  78                         };
  79                 };
  80         };
  81 };
  82
  83 &i2c2 {
  84         clock-frequency = <400000>;
  85 };
  86
  87 &i2c3 {
  88         clock-frequency = <400000>;
  89         at24@50 {
  90                 compatible = "atmel,24c64";
  91                 readonly;
  92                 reg = <0x50>;
  93         };
  94 };
  95
  96 &omap3_pmx_core {
  97         mcbsp2_pins: pinmux_mcbsp2_pins {
  98                 pinctrl-single,pins = <
  99                         OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
 100                         OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx */
 101                         OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr */
 102                         OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx */
 103                 >;
 104         };
 105         uart2_pins: pinmux_uart2_pins {
 106                 pinctrl-single,pins = <
 107                         OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)        /* uart2_cts.uart2_cts */
 108                         OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)       /* uart2_rts .uart2_rts*/
 109                         OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)       /* uart2_tx.uart2_tx */
 110                         OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)        /* uart2_rx.uart2_rx */
 111                         OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)       /* GPIO_162,BT_EN */
 112                 >;
 113         };
 114         mcspi1_pins: pinmux_mcspi1_pins {
 115                 pinctrl-single,pins = <
 116                         OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
 117                         OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
 118                         OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
 119                         OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
 120                 >;
 121         };
 122         hsusb_otg_pins: pinmux_hsusb_otg_pins {
 123                 pinctrl-single,pins = <
 124                         OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)        /* hsusb0_clk.hsusb0_clk */
 125                         OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)       /* hsusb0_stp.hsusb0_stp */
 126                         OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)        /* hsusb0_dir.hsusb0_dir */
 127                         OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)        /* hsusb0_nxt.hsusb0_nxt */
 128
 129                         OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)        /* hsusb0_data0.hsusb0_data0 */
 130                         OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)        /* hsusb0_data1.hsusb0_data1 */
 131                         OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)        /* hsusb0_data2.hsusb0_data2 */
 132                         OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)        /* hsusb0_data3.hsusb0_data3 */
 133                         OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)        /* hsusb0_data4.hsusb0_data4 */
 134                         OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)        /* hsusb0_data5.hsusb0_data5 */
 135                         OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)        /* hsusb0_data6.hsusb0_data6 */
 136                         OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)        /* hsusb0_data7.hsusb0_data7 */
 137                 >;
 138         };
 139 };
 140
 141 &uart2 {
 142         interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&uart2_pins>;
 145 };
 146
 147 &mcspi1 {
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&mcspi1_pins>;
 150 };
 151
 152 #include "twl4030.dtsi"
 153 #include "twl4030_omap3.dtsi"
 154
 155 &twl {
 156         twl_power: power {
 157                 compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
 158                 ti,use_poweroff;
 159         };
 160 };
 161
 162 &twl_gpio {
 163         ti,use-leds;
 164 };