arch/arm/boot/dts/keystone-k2l.dtsi

   1 /*
   2  * Copyright 2014 Texas Instruments, Inc.
   3  *
   4  * Keystone 2 Lamarr SoC specific device tree
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 / {
  12         compatible = "ti,k2l", "ti,keystone";
  13         model = "Texas Instruments Keystone 2 Lamarr SoC";
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 interrupt-parent = <&gic>;
  20
  21                 cpu@0 {
  22                         compatible = "arm,cortex-a15";
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                 };
  26
  27                 cpu@1 {
  28                         compatible = "arm,cortex-a15";
  29                         device_type = "cpu";
  30                         reg = <1>;
  31                 };
  32         };
  33
  34         soc {
  35                 /include/ "keystone-k2l-clocks.dtsi"
  36
  37                 uart2: serial@02348400 {
  38                         compatible = "ns16550a";
  39                         current-speed = <115200>;
  40                         reg-shift = <2>;
  41                         reg-io-width = <4>;
  42                         reg = <0x02348400 0x100>;
  43                         clocks  = <&clkuart2>;
  44                         interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
  45                 };
  46
  47                 uart3:  serial@02348800 {
  48                         compatible = "ns16550a";
  49                         current-speed = <115200>;
  50                         reg-shift = <2>;
  51                         reg-io-width = <4>;
  52                         reg = <0x02348800 0x100>;
  53                         clocks  = <&clkuart3>;
  54                         interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
  55                 };
  56
  57                 k2l_pmx: pinmux@02620690 {
  58                         compatible = "pinctrl-single";
  59                         reg = <0x02620690 0xc>;
  60                         #address-cells = <1>;
  61                         #size-cells = <0>;
  62                         #pinctrl-cells = <2>;
  63                         pinctrl-single,bit-per-mux;
  64                         pinctrl-single,register-width = <32>;
  65                         pinctrl-single,function-mask = <0x1>;
  66                         status = "disabled";
  67
  68                         uart3_emifa_pins: pinmux_uart3_emifa_pins {
  69                                 pinctrl-single,bits = <
  70                                         /* UART3_EMIFA_SEL */
  71                                         0x0 0x0  0xc0
  72                                 >;
  73                         };
  74
  75                         uart2_emifa_pins: pinmux_uart2_emifa_pins {
  76                         pinctrl-single,bits = <
  77                                         /* UART2_EMIFA_SEL */
  78                                         0x0 0x0  0x30
  79                                 >;
  80                         };
  81
  82                         uart01_spi2_pins: pinmux_uart01_spi2_pins {
  83                                 pinctrl-single,bits = <
  84                                         /* UART01_SPI2_SEL */
  85                                         0x0 0x0 0x4
  86                                 >;
  87                         };
  88
  89                         dfesync_rp1_pins: pinmux_dfesync_rp1_pins{
  90                                 pinctrl-single,bits = <
  91                                         /* DFESYNC_RP1_SEL */
  92                                         0x0 0x0 0x2
  93                                 >;
  94                         };
  95
  96                         avsif_pins: pinmux_avsif_pins {
  97                                 pinctrl-single,bits = <
  98                                         /* AVSIF_SEL */
  99                                         0x0 0x0 0x1
 100                                 >;
 101                         };
 102
 103                         gpio_emu_pins: pinmux_gpio_emu_pins {
 104                                 pinctrl-single,bits = <
 105                                 /*
 106                                  * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33
 107                                  * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32
 108                                  * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31
 109                                  * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30
 110                                  * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29
 111                                  * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28
 112                                  * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27
 113                                  * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26
 114                                  * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25
 115                                  * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24
 116                                  * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23
 117                                  * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22
 118                                  * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21
 119                                  * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20
 120                                  * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19
 121                                  */
 122                                         0x4 0x0000 0xFFFE0000
 123                                 >;
 124                         };
 125
 126                         gpio_timio_pins: pinmux_gpio_timio_pins {
 127                                 pinctrl-single,bits = <
 128                                 /*
 129                                  * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7
 130                                  * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6
 131                                  * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5
 132                                  * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4
 133                                  * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3
 134                                  * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2
 135                                  * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7
 136                                  * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6
 137                                  * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5
 138                                  * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4
 139                                  * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3
 140                                  * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2
 141                                  */
 142                                         0x4 0x0 0xFFF0
 143                                 >;
 144                         };
 145
 146                         gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins {
 147                                 pinctrl-single,bits = <
 148                                 /*
 149                                  * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4
 150                                  * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3
 151                                  * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2
 152                                  * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1
 153                                  */
 154                                         0x4 0x0 0xF
 155                                 >;
 156                         };
 157
 158                         gpio_dfeio_pins: pinmux_gpio_dfeio_pins {
 159                                 pinctrl-single,bits = <
 160                                 /*
 161                                  * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63
 162                                  * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62
 163                                  * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61
 164                                  * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60
 165                                  * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59
 166                                  * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58
 167                                  * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57
 168                                  * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56
 169                                  * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55
 170                                  * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54
 171                                  * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53
 172                                  * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52
 173                                  * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51
 174                                  * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50
 175                                  * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49
 176                                  * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48
 177                                  */
 178                                         0x8 0x0 0xFFFF0000
 179                                 >;
 180                         };
 181
 182                         gpio_emifa_pins: pinmux_gpio_emifa_pins {
 183                                 pinctrl-single,bits = <
 184                                 /*
 185                                  * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47
 186                                  * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46
 187                                  * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45
 188                                  * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44
 189                                  * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43
 190                                  * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42
 191                                  * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41
 192                                  * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40
 193                                  * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39
 194                                  * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38
 195                                  * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37
 196                                  * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36
 197                                  * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35
 198                                  * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34
 199                                  * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33
 200                                  * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32
 201                                  */
 202                                         0x8 0x0 0xFFFF
 203                                 >;
 204                         };
 205                 };
 206
 207                 dspgpio0: keystone_dsp_gpio@02620240 {
 208                         compatible = "ti,keystone-dsp-gpio";
 209                         gpio-controller;
 210                         #gpio-cells = <2>;
 211                         gpio,syscon-dev = <&devctrl 0x240>;
 212                 };
 213
 214                 dspgpio1: keystone_dsp_gpio@2620244 {
 215                         compatible = "ti,keystone-dsp-gpio";
 216                         gpio-controller;
 217                         #gpio-cells = <2>;
 218                         gpio,syscon-dev = <&devctrl 0x244>;
 219                 };
 220
 221                 dspgpio2: keystone_dsp_gpio@2620248 {
 222                         compatible = "ti,keystone-dsp-gpio";
 223                         gpio-controller;
 224                         #gpio-cells = <2>;
 225                         gpio,syscon-dev = <&devctrl 0x248>;
 226                 };
 227
 228                 dspgpio3: keystone_dsp_gpio@262024c {
 229                         compatible = "ti,keystone-dsp-gpio";
 230                         gpio-controller;
 231                         #gpio-cells = <2>;
 232                         gpio,syscon-dev = <&devctrl 0x24c>;
 233                 };
 234
 235                 mdio: mdio@26200f00 {
 236                         compatible      = "ti,keystone_mdio", "ti,davinci_mdio";
 237                         #address-cells = <1>;
 238                         #size-cells = <0>;
 239                         reg = <0x26200f00 0x100>;
 240                         status = "disabled";
 241                         clocks = <&clkcpgmac>;
 242                         clock-names = "fck";
 243                         bus_freq        = <2500000>;
 244                 };
 245                 /include/ "keystone-k2l-netcp.dtsi"
 246         };
 247 };
 248
 249 &spi0 {
 250        ti,davinci-spi-num-cs = <5>;
 251 };
 252
 253 &spi1 {
 254        ti,davinci-spi-num-cs = <3>;
 255 };
 256
 257 &spi2 {
 258        ti,davinci-spi-num-cs = <5>;
 259        /* Pin muxed. Enabled and configured by Bootloader */
 260        status = "disabled";
 261 };