arch/arm/boot/dts/keystone-k2l-clocks.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Keystone 2 lamarr SoC clock nodes
   4  *
   5  * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 clocks {
   9         armpllclk: armpllclk@2620370 {
  10                 #clock-cells = <0>;
  11                 compatible = "ti,keystone,pll-clock";
  12                 clocks = <&refclksys>;
  13                 clock-output-names = "arm-pll-clk";
  14                 reg = <0x02620370 4>;
  15                 reg-names = "control";
  16         };
  17
  18         mainpllclk: mainpllclk@2310110 {
  19                 #clock-cells = <0>;
  20                 compatible = "ti,keystone,main-pll-clock";
  21                 clocks = <&refclksys>;
  22                 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
  23                 reg-names = "control", "multiplier", "post-divider";
  24         };
  25
  26         papllclk: papllclk@2620358 {
  27                 #clock-cells = <0>;
  28                 compatible = "ti,keystone,pll-clock";
  29                 clocks = <&refclksys>;
  30                 clock-output-names = "papllclk";
  31                 reg = <0x02620358 4>;
  32                 reg-names = "control";
  33         };
  34
  35         ddr3apllclk: ddr3apllclk@2620360 {
  36                 #clock-cells = <0>;
  37                 compatible = "ti,keystone,pll-clock";
  38                 clocks = <&refclksys>;
  39                 clock-output-names = "ddr-3a-pll-clk";
  40                 reg = <0x02620360 4>;
  41                 reg-names = "control";
  42         };
  43
  44         clkdfeiqnsys: clkdfeiqnsys@2350004 {
  45                 #clock-cells = <0>;
  46                 compatible = "ti,keystone,psc-clock";
  47                 clocks = <&chipclk12>;
  48                 clock-output-names = "dfe";
  49                 reg-names = "control", "domain";
  50                 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
  51                 domain-id = <0>;
  52         };
  53
  54         clkpcie1: clkpcie1@235002c {
  55                 #clock-cells = <0>;
  56                 compatible = "ti,keystone,psc-clock";
  57                 clocks = <&chipclk12>;
  58                 clock-output-names = "pcie";
  59                 reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
  60                 reg-names = "control", "domain";
  61                 domain-id = <4>;
  62         };
  63
  64         clkgem1: clkgem1@2350040 {
  65                 #clock-cells = <0>;
  66                 compatible = "ti,keystone,psc-clock";
  67                 clocks = <&chipclk1>;
  68                 clock-output-names = "gem1";
  69                 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
  70                 reg-names = "control", "domain";
  71                 domain-id = <9>;
  72         };
  73
  74         clkgem2: clkgem2@2350044 {
  75                 #clock-cells = <0>;
  76                 compatible = "ti,keystone,psc-clock";
  77                 clocks = <&chipclk1>;
  78                 clock-output-names = "gem2";
  79                 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
  80                 reg-names = "control", "domain";
  81                 domain-id = <10>;
  82         };
  83
  84         clkgem3: clkgem3@2350048 {
  85                 #clock-cells = <0>;
  86                 compatible = "ti,keystone,psc-clock";
  87                 clocks = <&chipclk1>;
  88                 clock-output-names = "gem3";
  89                 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
  90                 reg-names = "control", "domain";
  91                 domain-id = <11>;
  92         };
  93
  94         clktac: clktac@2350064 {
  95                 #clock-cells = <0>;
  96                 compatible = "ti,keystone,psc-clock";
  97                 clocks = <&chipclk13>;
  98                 clock-output-names = "tac";
  99                 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
 100                 reg-names = "control", "domain";
 101                 domain-id = <17>;
 102         };
 103
 104         clkrac: clkrac@2350068 {
 105                 #clock-cells = <0>;
 106                 compatible = "ti,keystone,psc-clock";
 107                 clocks = <&chipclk13>;
 108                 clock-output-names = "rac";
 109                 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
 110                 reg-names = "control", "domain";
 111                 domain-id = <17>;
 112         };
 113
 114         clkdfepd0: clkdfepd0@235006c {
 115                 #clock-cells = <0>;
 116                 compatible = "ti,keystone,psc-clock";
 117                 clocks = <&chipclk13>;
 118                 clock-output-names = "dfe-pd0";
 119                 reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
 120                 reg-names = "control", "domain";
 121                 domain-id = <18>;
 122         };
 123
 124         clkfftc0: clkfftc0@2350070 {
 125                 #clock-cells = <0>;
 126                 compatible = "ti,keystone,psc-clock";
 127                 clocks = <&chipclk13>;
 128                 clock-output-names = "fftc-0";
 129                 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
 130                 reg-names = "control", "domain";
 131                 domain-id = <19>;
 132         };
 133
 134         clkosr: clkosr@2350088 {
 135                 #clock-cells = <0>;
 136                 compatible = "ti,keystone,psc-clock";
 137                 clocks = <&chipclk13>;
 138                 clock-output-names = "osr";
 139                 reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
 140                 reg-names = "control", "domain";
 141                 domain-id = <21>;
 142         };
 143
 144         clktcp3d0: clktcp3d0@235008c {
 145                 #clock-cells = <0>;
 146                 compatible = "ti,keystone,psc-clock";
 147                 clocks = <&chipclk13>;
 148                 clock-output-names = "tcp3d-0";
 149                 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
 150                 reg-names = "control", "domain";
 151                 domain-id = <22>;
 152         };
 153
 154         clktcp3d1: clktcp3d1@2350094 {
 155                 #clock-cells = <0>;
 156                 compatible = "ti,keystone,psc-clock";
 157                 clocks = <&chipclk13>;
 158                 clock-output-names = "tcp3d-1";
 159                 reg = <0x02350094 0xb00>, <0x02350058 0x400>;
 160                 reg-names = "control", "domain";
 161                 domain-id = <23>;
 162         };
 163
 164         clkvcp0: clkvcp0@235009c {
 165                 #clock-cells = <0>;
 166                 compatible = "ti,keystone,psc-clock";
 167                 clocks = <&chipclk13>;
 168                 clock-output-names = "vcp-0";
 169                 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
 170                 reg-names = "control", "domain";
 171                 domain-id = <24>;
 172         };
 173
 174         clkvcp1: clkvcp1@23500a0 {
 175                 #clock-cells = <0>;
 176                 compatible = "ti,keystone,psc-clock";
 177                 clocks = <&chipclk13>;
 178                 clock-output-names = "vcp-1";
 179                 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
 180                 reg-names = "control", "domain";
 181                 domain-id = <24>;
 182         };
 183
 184         clkvcp2: clkvcp2@23500a4 {
 185                 #clock-cells = <0>;
 186                 compatible = "ti,keystone,psc-clock";
 187                 clocks = <&chipclk13>;
 188                 clock-output-names = "vcp-2";
 189                 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
 190                 reg-names = "control", "domain";
 191                 domain-id = <24>;
 192         };
 193
 194         clkvcp3: clkvcp3@23500a8 {
 195                 #clock-cells = <0>;
 196                 compatible = "ti,keystone,psc-clock";
 197                 clocks = <&chipclk13>;
 198                 clock-output-names = "vcp-3";
 199                 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
 200                 reg-names = "control", "domain";
 201                 domain-id = <24>;
 202         };
 203
 204         clkbcp: clkbcp@23500bc {
 205                 #clock-cells = <0>;
 206                 compatible = "ti,keystone,psc-clock";
 207                 clocks = <&chipclk13>;
 208                 clock-output-names = "bcp";
 209                 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
 210                 reg-names = "control", "domain";
 211                 domain-id = <26>;
 212         };
 213
 214         clkdfepd1: clkdfepd1@23500c0 {
 215                 #clock-cells = <0>;
 216                 compatible = "ti,keystone,psc-clock";
 217                 clocks = <&chipclk13>;
 218                 clock-output-names = "dfe-pd1";
 219                 reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
 220                 reg-names = "control", "domain";
 221                 domain-id = <27>;
 222         };
 223
 224         clkfftc1: clkfftc1@23500c4 {
 225                 #clock-cells = <0>;
 226                 compatible = "ti,keystone,psc-clock";
 227                 clocks = <&chipclk13>;
 228                 clock-output-names = "fftc-1";
 229                 reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
 230                 reg-names = "control", "domain";
 231                 domain-id = <28>;
 232         };
 233
 234         clkiqnail: clkiqnail@23500c8 {
 235                 #clock-cells = <0>;
 236                 compatible = "ti,keystone,psc-clock";
 237                 clocks = <&chipclk13>;
 238                 clock-output-names = "iqn-ail";
 239                 reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
 240                 reg-names = "control", "domain";
 241                 domain-id = <29>;
 242         };
 243
 244         clkuart2: clkuart2@2350000 {
 245                 #clock-cells = <0>;
 246                 compatible = "ti,keystone,psc-clock";
 247                 clocks = <&clkmodrst0>;
 248                 clock-output-names = "uart2";
 249                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 250                 reg-names = "control", "domain";
 251                 domain-id = <0>;
 252         };
 253
 254         clkuart3: clkuart3@2350000 {
 255                 #clock-cells = <0>;
 256                 compatible = "ti,keystone,psc-clock";
 257                 clocks = <&clkmodrst0>;
 258                 clock-output-names = "uart3";
 259                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 260                 reg-names = "control", "domain";
 261                 domain-id = <0>;
 262         };
 263 };