arch/arm/boot/dts/keystone-k2g-evm.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for K2G EVM
   4  *
   5  * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7 /dts-v1/;
   8
   9 #include "keystone-k2g.dtsi"
  10
  11 / {
  12         compatible =  "ti,k2g-evm", "ti,k2g", "ti,keystone";
  13         model = "Texas Instruments K2G General Purpose EVM";
  14
  15         memory@800000000 {
  16                 device_type = "memory";
  17                 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
  18         };
  19
  20         reserved-memory {
  21                 #address-cells = <2>;
  22                 #size-cells = <2>;
  23                 ranges;
  24
  25                 dsp_common_memory: dsp-common-memory@81f800000 {
  26                         compatible = "shared-dma-pool";
  27                         reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
  28                         reusable;
  29                         status = "okay";
  30                 };
  31         };
  32
  33         vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "mmc0_fixed";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 regulator-always-on;
  39         };
  40 };
  41
  42 &k2g_pinctrl {
  43         uart0_pins: pinmux_uart0_pins {
  44                 pinctrl-single,pins = <
  45                         K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* uart0_rxd.uart0_rxd */
  46                         K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)      /* uart0_txd.uart0_txd */
  47                 >;
  48         };
  49
  50         mmc0_pins: pinmux_mmc0_pins {
  51                 pinctrl-single,pins = <
  52                         K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat3.mmc0_dat3 */
  53                         K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat2.mmc0_dat2 */
  54                         K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat1.mmc0_dat1 */
  55                         K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat0.mmc0_dat0 */
  56                         K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_clk.mmc0_clk */
  57                         K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_cmd.mmc0_cmd */
  58                         K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)        /* mmc0_sdcd.gpio1_12 */
  59                 >;
  60         };
  61
  62         mmc1_pins: pinmux_mmc1_pins {
  63                 pinctrl-single,pins = <
  64                         K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat7.mmc1_dat7 */
  65                         K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat6.mmc1_dat6 */
  66                         K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat5.mmc1_dat5 */
  67                         K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat4.mmc1_dat4 */
  68                         K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat3.mmc1_dat3 */
  69                         K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat2.mmc1_dat2 */
  70                         K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat1.mmc1_dat1 */
  71                         K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat0.mmc1_dat0 */
  72                         K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_clk.mmc1_clk */
  73                         K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_cmd.mmc1_cmd */
  74                 >;
  75         };
  76
  77         i2c0_pins: pinmux_i2c0_pins {
  78                 pinctrl-single,pins = <
  79                         K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* i2c0_scl.i2c0_scl */
  80                         K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* i2c0_sda.i2c0_sda */
  81                 >;
  82         };
  83
  84         ecap0_pins: ecap0_pins {
  85                 pinctrl-single,pins = <
  86                         K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4)     /* pr1_mdio_data.ecap0_in_apwm0_out */
  87                 >;
  88         };
  89
  90         spi1_pins: pinmux_spi1_pins {
  91                 pinctrl-single,pins = <
  92                         K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_scs0.spi1_scs0 */
  93                         K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_clk.spi1_clk */
  94                         K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_miso.spi1_miso */
  95                         K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_mosi.spi1_mosi */
  96                 >;
  97         };
  98
  99         qspi_pins: pinmux_qspi_pins {
 100                 pinctrl-single,pins = <
 101                         K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
 102                         K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
 103                         K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
 104                         K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
 105                         K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
 106                         K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
 107                         K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
 108                 >;
 109         };
 110
 111         uart2_pins: pinmux_uart2_pins {
 112                 pinctrl-single,pins = <
 113                         K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* uart2_rxd.uart2_rxd */
 114                         K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)      /* uart2_txd.uart2_txd */
 115                 >;
 116         };
 117
 118         dcan0_pins: pinmux_dcan0_pins {
 119                 pinctrl-single,pins = <
 120                         K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE  | MUX_MODE0)     /* dcan0tx.dcan0tx */
 121                         K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN  | MUX_MODE0)     /* dcan0rx.dcan0rx */
 122                 >;
 123         };
 124
 125         dcan1_pins: pinmux_dcan1_pins {
 126                 pinctrl-single,pins = <
 127                         K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE  | MUX_MODE1)     /* qspicsn2.dcan1tx */
 128                         K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN  | MUX_MODE1)     /* qspicsn3.dcan1rx */
 129                 >;
 130         };
 131 };
 132
 133 &uart0 {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&uart0_pins>;
 136         status = "okay";
 137 };
 138
 139 &gpio1 {
 140         status = "okay";
 141 };
 142
 143 &mmc0 {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&mmc0_pins>;
 146         vmmc-supply = <&vcc3v3_dcin_reg>;
 147         cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
 148         status = "okay";
 149 };
 150
 151 &mmc1 {
 152         pinctrl-names = "default";
 153         pinctrl-0 = <&mmc1_pins>;
 154         vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
 155         ti,non-removable;
 156         status = "okay";
 157 };
 158
 159 &dsp0 {
 160         memory-region = <&dsp_common_memory>;
 161         status = "okay";
 162 };
 163
 164 &i2c0 {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&i2c0_pins>;
 167         status = "okay";
 168
 169         eeprom@50 {
 170                 compatible = "atmel,24c1024";
 171                 reg = <0x50>;
 172         };
 173 };
 174
 175 &keystone_usb0 {
 176         status = "okay";
 177 };
 178
 179 &usb0_phy {
 180         status = "okay";
 181 };
 182
 183 &usb0 {
 184         dr_mode = "host";
 185         status = "okay";
 186 };
 187
 188 &keystone_usb1 {
 189         status = "okay";
 190 };
 191
 192 &usb1_phy {
 193         status = "okay";
 194 };
 195
 196 &usb1 {
 197         dr_mode = "peripheral";
 198         status = "okay";
 199 };
 200
 201 &ecap0 {
 202         status = "okay";
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&ecap0_pins>;
 205 };
 206
 207 &spi1 {
 208         pinctrl-names = "default";
 209         pinctrl-0 = <&spi1_pins>;
 210         status = "okay";
 211
 212         spi_nor: flash@0 {
 213                 #address-cells = <1>;
 214                 #size-cells = <1>;
 215                 compatible = "jedec,spi-nor";
 216                 spi-max-frequency = <5000000>;
 217                 m25p,fast-read;
 218                 reg = <0>;
 219
 220                 partition@0 {
 221                         label = "u-boot-spl";
 222                         reg = <0x0 0x100000>;
 223                         read-only;
 224                 };
 225
 226                 partition@1 {
 227                         label = "misc";
 228                         reg = <0x100000 0xf00000>;
 229                 };
 230         };
 231 };
 232
 233 &qspi {
 234         status = "okay";
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&qspi_pins>;
 237         cdns,rclk-en;
 238
 239         flash0: m25p80@0 {
 240                 compatible = "s25fl512s", "jedec,spi-nor";
 241                 reg = <0>;
 242                 spi-tx-bus-width = <1>;
 243                 spi-rx-bus-width = <4>;
 244                 spi-max-frequency = <96000000>;
 245                 #address-cells = <1>;
 246                 #size-cells = <1>;
 247                 cdns,read-delay = <5>;
 248                 cdns,tshsl-ns = <500>;
 249                 cdns,tsd2d-ns = <500>;
 250                 cdns,tchsh-ns = <119>;
 251                 cdns,tslch-ns = <119>;
 252
 253                 partition@0 {
 254                         label = "QSPI.u-boot-spl-os";
 255                         reg = <0x00000000 0x00100000>;
 256                 };
 257                 partition@1 {
 258                         label = "QSPI.u-boot-env";
 259                         reg = <0x00100000 0x00040000>;
 260                 };
 261                 partition@2 {
 262                         label = "QSPI.skern";
 263                         reg = <0x00140000 0x0040000>;
 264                 };
 265                 partition@3 {
 266                         label = "QSPI.pmmc-firmware";
 267                         reg = <0x00180000 0x0040000>;
 268                 };
 269                 partition@4 {
 270                         label = "QSPI.kernel";
 271                         reg = <0x001C0000 0x0800000>;
 272                 };
 273                 partition@5 {
 274                         label = "QSPI.file-system";
 275                         reg = <0x009C0000 0x3640000>;
 276                 };
 277         };
 278 };
 279
 280 &uart2 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&uart2_pins>;
 283         status = "okay";
 284 };
 285
 286 &dcan0 {
 287         pinctrl-names = "default";
 288         pinctrl-0 = <&dcan0_pins>;
 289         status = "okay";
 290 };
 291
 292 &dcan1 {
 293         pinctrl-names = "default";
 294         pinctrl-0 = <&dcan1_pins>;
 295         status = "okay";
 296 };