1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
40 compatible = "arm,cortex-a7";
46 intc: interrupt-controller@40021000 {
47 compatible = "arm,cortex-a7-gic";
48 #interrupt-cells = <3>;
50 reg = <0x40021000 0x1000>,
55 compatible = "fixed-clock";
56 clock-frequency = <32768>;
57 clock-output-names = "rosc";
62 compatible = "fixed-clock";
63 clock-frequency = <24000000>;
64 clock-output-names = "sosc";
69 compatible = "fixed-clock";
70 clock-frequency = <16000000>;
71 clock-output-names = "sirc";
76 compatible = "fixed-clock";
77 clock-frequency = <48000000>;
78 clock-output-names = "firc";
83 compatible = "fixed-clock";
84 clock-frequency = <480000000>;
85 clock-output-names = "upll";
90 compatible = "fixed-clock";
91 clock-frequency = <480000000>;
92 clock-output-names = "mpll";
96 ahbbridge0: bus@40000000 {
97 compatible = "simple-bus";
100 reg = <0x40000000 0x800000>;
103 crypto: crypto@40240000 {
104 compatible = "fsl,sec-v4.0";
105 #address-cells = <1>;
107 reg = <0x40240000 0x10000>;
108 ranges = <0 0x40240000 0x10000>;
109 clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
110 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
111 clock-names = "aclk", "ipg";
114 compatible = "fsl,sec-v4.0-job-ring";
115 reg = <0x1000 0x1000>;
116 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
120 compatible = "fsl,sec-v4.0-job-ring";
121 reg = <0x2000 0x1000>;
122 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
126 lpuart4: serial@402d0000 {
127 compatible = "fsl,imx7ulp-lpuart";
128 reg = <0x402d0000 0x1000>;
129 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
132 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
133 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
134 assigned-clock-rates = <24000000>;
138 lpuart5: serial@402e0000 {
139 compatible = "fsl,imx7ulp-lpuart";
140 reg = <0x402e0000 0x1000>;
141 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
144 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
145 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
146 assigned-clock-rates = <48000000>;
151 compatible = "fsl,imx7ulp-tpm";
152 reg = <0x40260000 0x1000>;
153 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
155 <&pcc2 IMX7ULP_CLK_LPTPM5>;
156 clock-names = "ipg", "per";
159 usdhc0: mmc@40370000 {
160 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
161 reg = <0x40370000 0x10000>;
162 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
164 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
165 <&pcc2 IMX7ULP_CLK_USDHC0>;
166 clock-names ="ipg", "ahb", "per";
167 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
168 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
170 fsl,tuning-start-tap = <20>;
171 fsl,tuning-step= <2>;
175 usdhc1: mmc@40380000 {
176 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
177 reg = <0x40380000 0x10000>;
178 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
180 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
181 <&pcc2 IMX7ULP_CLK_USDHC1>;
182 clock-names ="ipg", "ahb", "per";
183 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
184 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
186 fsl,tuning-start-tap = <20>;
187 fsl,tuning-step= <2>;
191 scg1: clock-controller@403e0000 {
192 compatible = "fsl,imx7ulp-scg1";
193 reg = <0x403e0000 0x10000>;
194 clocks = <&rosc>, <&sosc>, <&sirc>,
195 <&firc>, <&upll>, <&mpll>;
196 clock-names = "rosc", "sosc", "sirc",
197 "firc", "upll", "mpll";
201 pcc2: clock-controller@403f0000 {
202 compatible = "fsl,imx7ulp-pcc2";
203 reg = <0x403f0000 0x10000>;
205 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
206 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
207 <&scg1 IMX7ULP_CLK_DDR_DIV>,
208 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
209 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
210 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
211 <&scg1 IMX7ULP_CLK_UPLL>,
212 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
213 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
214 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
215 <&scg1 IMX7ULP_CLK_ROSC>,
216 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
217 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
218 "apll_pfd2", "apll_pfd1", "apll_pfd0",
219 "upll", "sosc_bus_clk", "mpll",
220 "firc_bus_clk", "rosc", "spll_bus_clk";
221 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
222 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
225 smc1: clock-controller@40410000 {
226 compatible = "fsl,imx7ulp-smc1";
227 reg = <0x40410000 0x1000>;
229 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
230 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
231 clock-names = "divcore", "hsrun_divcore";
234 pcc3: clock-controller@40b30000 {
235 compatible = "fsl,imx7ulp-pcc3";
236 reg = <0x40b30000 0x10000>;
238 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
239 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
240 <&scg1 IMX7ULP_CLK_DDR_DIV>,
241 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
242 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
243 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
244 <&scg1 IMX7ULP_CLK_UPLL>,
245 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
246 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
247 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
248 <&scg1 IMX7ULP_CLK_ROSC>,
249 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
250 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
251 "apll_pfd2", "apll_pfd1", "apll_pfd0",
252 "upll", "sosc_bus_clk", "mpll",
253 "firc_bus_clk", "rosc", "spll_bus_clk";
257 ahbbridge1: bus@40800000 {
258 compatible = "simple-bus";
259 #address-cells = <1>;
261 reg = <0x40800000 0x800000>;
264 lpi2c6: i2c@40a40000 {
265 compatible = "fsl,imx7ulp-lpi2c";
266 reg = <0x40a40000 0x10000>;
267 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
270 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
271 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
272 assigned-clock-rates = <48000000>;
276 lpi2c7: i2c@40a50000 {
277 compatible = "fsl,imx7ulp-lpi2c";
278 reg = <0x40a50000 0x10000>;
279 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
282 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
283 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
284 assigned-clock-rates = <48000000>;
288 lpuart6: serial@40a60000 {
289 compatible = "fsl,imx7ulp-lpuart";
290 reg = <0x40a60000 0x1000>;
291 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
294 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
295 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
296 assigned-clock-rates = <48000000>;
300 lpuart7: serial@40a70000 {
301 compatible = "fsl,imx7ulp-lpuart";
302 reg = <0x40a70000 0x1000>;
303 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
306 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
307 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
308 assigned-clock-rates = <48000000>;
312 memory-controller@40ab0000 {
313 compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
314 reg = <0x40ab0000 0x1000>;
315 clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
318 iomuxc1: pinctrl@40ac0000 {
319 compatible = "fsl,imx7ulp-iomuxc1";
320 reg = <0x40ac0000 0x1000>;
323 gpio_ptc: gpio@40ae0000 {
324 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
325 reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
328 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
332 <&pcc3 IMX7ULP_CLK_PCTLC>;
333 clock-names = "gpio", "port";
334 gpio-ranges = <&iomuxc1 0 0 32>;
337 gpio_ptd: gpio@40af0000 {
338 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
339 reg = <0x40af0000 0x1000 0x400f0040 0x40>;
342 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
346 <&pcc3 IMX7ULP_CLK_PCTLD>;
347 clock-names = "gpio", "port";
348 gpio-ranges = <&iomuxc1 0 32 32>;
351 gpio_pte: gpio@40b00000 {
352 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
353 reg = <0x40b00000 0x1000 0x400f0080 0x40>;
356 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
359 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
360 <&pcc3 IMX7ULP_CLK_PCTLE>;
361 clock-names = "gpio", "port";
362 gpio-ranges = <&iomuxc1 0 64 32>;
365 gpio_ptf: gpio@40b10000 {
366 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
367 reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
370 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
374 <&pcc3 IMX7ULP_CLK_PCTLF>;
375 clock-names = "gpio", "port";
376 gpio-ranges = <&iomuxc1 0 96 32>;
380 m4aips1: bus@41080000 {
381 compatible = "simple-bus";
382 #address-cells = <1>;
384 reg = <0x41080000 0x80000>;
388 compatible = "fsl,imx7ulp-sim", "syscon";
389 reg = <0x410a3000 0x1000>;
392 ocotp: ocotp-ctrl@410a6000 {
393 compatible = "fsl,imx7ulp-ocotp", "syscon";
394 reg = <0x410a6000 0x4000>;
395 clocks = <&scg1 IMX7ULP_CLK_DUMMY>;