1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
40 compatible = "arm,cortex-a7";
46 intc: interrupt-controller@40021000 {
47 compatible = "arm,cortex-a7-gic";
48 #interrupt-cells = <3>;
50 reg = <0x40021000 0x1000>,
55 compatible = "fixed-clock";
56 clock-frequency = <32768>;
57 clock-output-names = "rosc";
62 compatible = "fixed-clock";
63 clock-frequency = <24000000>;
64 clock-output-names = "sosc";
69 compatible = "fixed-clock";
70 clock-frequency = <16000000>;
71 clock-output-names = "sirc";
76 compatible = "fixed-clock";
77 clock-frequency = <48000000>;
78 clock-output-names = "firc";
83 compatible = "fixed-clock";
84 clock-frequency = <480000000>;
85 clock-output-names = "upll";
90 compatible = "fixed-clock";
91 clock-frequency = <480000000>;
92 clock-output-names = "mpll";
96 ahbbridge0: bus@40000000 {
97 compatible = "simple-bus";
100 reg = <0x40000000 0x800000>;
103 lpuart4: serial@402d0000 {
104 compatible = "fsl,imx7ulp-lpuart";
105 reg = <0x402d0000 0x1000>;
106 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
109 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
110 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
111 assigned-clock-rates = <24000000>;
115 lpuart5: serial@402e0000 {
116 compatible = "fsl,imx7ulp-lpuart";
117 reg = <0x402e0000 0x1000>;
118 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
121 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
122 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
123 assigned-clock-rates = <48000000>;
128 compatible = "fsl,imx7ulp-tpm";
129 reg = <0x40260000 0x1000>;
130 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
132 <&pcc2 IMX7ULP_CLK_LPTPM5>;
133 clock-names = "ipg", "per";
136 usdhc0: mmc@40370000 {
137 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
138 reg = <0x40370000 0x10000>;
139 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
141 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
142 <&pcc2 IMX7ULP_CLK_USDHC0>;
143 clock-names ="ipg", "ahb", "per";
144 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
145 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
147 fsl,tuning-start-tap = <20>;
148 fsl,tuning-step= <2>;
152 usdhc1: mmc@40380000 {
153 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
154 reg = <0x40380000 0x10000>;
155 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
157 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
158 <&pcc2 IMX7ULP_CLK_USDHC1>;
159 clock-names ="ipg", "ahb", "per";
160 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
161 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
163 fsl,tuning-start-tap = <20>;
164 fsl,tuning-step= <2>;
168 scg1: clock-controller@403e0000 {
169 compatible = "fsl,imx7ulp-scg1";
170 reg = <0x403e0000 0x10000>;
171 clocks = <&rosc>, <&sosc>, <&sirc>,
172 <&firc>, <&upll>, <&mpll>;
173 clock-names = "rosc", "sosc", "sirc",
174 "firc", "upll", "mpll";
178 pcc2: clock-controller@403f0000 {
179 compatible = "fsl,imx7ulp-pcc2";
180 reg = <0x403f0000 0x10000>;
182 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
183 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
184 <&scg1 IMX7ULP_CLK_DDR_DIV>,
185 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
186 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
187 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
188 <&scg1 IMX7ULP_CLK_UPLL>,
189 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
190 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
191 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
192 <&scg1 IMX7ULP_CLK_ROSC>,
193 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
194 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
195 "apll_pfd2", "apll_pfd1", "apll_pfd0",
196 "upll", "sosc_bus_clk", "mpll",
197 "firc_bus_clk", "rosc", "spll_bus_clk";
198 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
199 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
202 smc1: smc1@40410000 {
203 compatible = "fsl,imx7ulp-smc1";
204 reg = <0x40410000 0x1000>;
207 pcc3: clock-controller@40b30000 {
208 compatible = "fsl,imx7ulp-pcc3";
209 reg = <0x40b30000 0x10000>;
211 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
212 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
213 <&scg1 IMX7ULP_CLK_DDR_DIV>,
214 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
215 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
216 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
217 <&scg1 IMX7ULP_CLK_UPLL>,
218 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
219 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
220 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
221 <&scg1 IMX7ULP_CLK_ROSC>,
222 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
223 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
224 "apll_pfd2", "apll_pfd1", "apll_pfd0",
225 "upll", "sosc_bus_clk", "mpll",
226 "firc_bus_clk", "rosc", "spll_bus_clk";
230 ahbbridge1: bus@40800000 {
231 compatible = "simple-bus";
232 #address-cells = <1>;
234 reg = <0x40800000 0x800000>;
237 lpi2c6: i2c@40a40000 {
238 compatible = "fsl,imx7ulp-lpi2c";
239 reg = <0x40a40000 0x10000>;
240 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
243 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
244 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
245 assigned-clock-rates = <48000000>;
249 lpi2c7: i2c@40a50000 {
250 compatible = "fsl,imx7ulp-lpi2c";
251 reg = <0x40a50000 0x10000>;
252 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
255 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
256 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
257 assigned-clock-rates = <48000000>;
261 lpuart6: serial@40a60000 {
262 compatible = "fsl,imx7ulp-lpuart";
263 reg = <0x40a60000 0x1000>;
264 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
267 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
268 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
269 assigned-clock-rates = <48000000>;
273 lpuart7: serial@40a70000 {
274 compatible = "fsl,imx7ulp-lpuart";
275 reg = <0x40a70000 0x1000>;
276 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
279 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
280 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
281 assigned-clock-rates = <48000000>;
285 iomuxc1: pinctrl@40ac0000 {
286 compatible = "fsl,imx7ulp-iomuxc1";
287 reg = <0x40ac0000 0x1000>;
290 gpio_ptc: gpio@40ae0000 {
291 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
292 reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
295 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
299 <&pcc3 IMX7ULP_CLK_PCTLC>;
300 clock-names = "gpio", "port";
301 gpio-ranges = <&iomuxc1 0 0 32>;
304 gpio_ptd: gpio@40af0000 {
305 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
306 reg = <0x40af0000 0x1000 0x400f0040 0x40>;
309 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
313 <&pcc3 IMX7ULP_CLK_PCTLD>;
314 clock-names = "gpio", "port";
315 gpio-ranges = <&iomuxc1 0 32 32>;
318 gpio_pte: gpio@40b00000 {
319 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
320 reg = <0x40b00000 0x1000 0x400f0080 0x40>;
323 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
326 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
327 <&pcc3 IMX7ULP_CLK_PCTLE>;
328 clock-names = "gpio", "port";
329 gpio-ranges = <&iomuxc1 0 64 32>;
332 gpio_ptf: gpio@40b10000 {
333 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
334 reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
337 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
340 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
341 <&pcc3 IMX7ULP_CLK_PCTLF>;
342 clock-names = "gpio", "port";
343 gpio-ranges = <&iomuxc1 0 96 32>;