arch/arm/boot/dts/imx7ulp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017-2018 NXP
   5  *   Dong Aisheng <aisheng.dong@nxp.com>
   6  */
   7
   8 #include <dt-bindings/clock/imx7ulp-clock.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 #include "imx7ulp-pinfunc.h"
  13
  14 / {
  15         interrupt-parent = <&intc>;
  16
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 gpio0 = &gpio_ptc;
  22                 gpio1 = &gpio_ptd;
  23                 gpio2 = &gpio_pte;
  24                 gpio3 = &gpio_ptf;
  25                 i2c0 = &lpi2c6;
  26                 i2c1 = &lpi2c7;
  27                 mmc0 = &usdhc0;
  28                 mmc1 = &usdhc1;
  29                 serial0 = &lpuart4;
  30                 serial1 = &lpuart5;
  31                 serial2 = &lpuart6;
  32                 serial3 = &lpuart7;
  33                 usbphy0 = &usbphy1;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu0: cpu@0 {
  41                         compatible = "arm,cortex-a7";
  42                         device_type = "cpu";
  43                         reg = <0>;
  44                 };
  45         };
  46
  47         intc: interrupt-controller@40021000 {
  48                 compatible = "arm,cortex-a7-gic";
  49                 #interrupt-cells = <3>;
  50                 interrupt-controller;
  51                 reg = <0x40021000 0x1000>,
  52                       <0x40022000 0x1000>;
  53         };
  54
  55         rosc: clock-rosc {
  56                 compatible = "fixed-clock";
  57                 clock-frequency = <32768>;
  58                 clock-output-names = "rosc";
  59                 #clock-cells = <0>;
  60         };
  61
  62         sosc: clock-sosc {
  63                 compatible = "fixed-clock";
  64                 clock-frequency = <24000000>;
  65                 clock-output-names = "sosc";
  66                 #clock-cells = <0>;
  67         };
  68
  69         sirc: clock-sirc {
  70                 compatible = "fixed-clock";
  71                 clock-frequency = <16000000>;
  72                 clock-output-names = "sirc";
  73                 #clock-cells = <0>;
  74         };
  75
  76         firc: clock-firc {
  77                 compatible = "fixed-clock";
  78                 clock-frequency = <48000000>;
  79                 clock-output-names = "firc";
  80                 #clock-cells = <0>;
  81         };
  82
  83         upll: clock-upll {
  84                 compatible = "fixed-clock";
  85                 clock-frequency = <480000000>;
  86                 clock-output-names = "upll";
  87                 #clock-cells = <0>;
  88         };
  89
  90         mpll: clock-mpll {
  91                 compatible = "fixed-clock";
  92                 clock-frequency = <480000000>;
  93                 clock-output-names = "mpll";
  94                 #clock-cells = <0>;
  95         };
  96
  97         ahbbridge0: bus@40000000 {
  98                 compatible = "simple-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 reg = <0x40000000 0x800000>;
 102                 ranges;
 103
 104                 edma1: dma-controller@40080000 {
 105                         #dma-cells = <2>;
 106                         compatible = "fsl,imx7ulp-edma";
 107                         reg = <0x40080000 0x2000>,
 108                                 <0x40210000 0x1000>;
 109                         dma-channels = <32>;
 110                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 111                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 112                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 113                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 114                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 115                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 116                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 117                                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 118                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 119                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 120                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 121                                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 122                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 123                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 124                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 125                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 126                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 127                         clock-names = "dma", "dmamux0";
 128                         clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
 129                                  <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
 130                 };
 131
 132                 crypto: crypto@40240000 {
 133                         compatible = "fsl,sec-v4.0";
 134                         #address-cells = <1>;
 135                         #size-cells = <1>;
 136                         reg = <0x40240000 0x10000>;
 137                         ranges = <0 0x40240000 0x10000>;
 138                         clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
 139                                  <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
 140                         clock-names = "aclk", "ipg";
 141
 142                         sec_jr0: jr0@1000 {
 143                                 compatible = "fsl,sec-v4.0-job-ring";
 144                                 reg = <0x1000 0x1000>;
 145                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 146                         };
 147
 148                         sec_jr1: jr1@2000 {
 149                                 compatible = "fsl,sec-v4.0-job-ring";
 150                                 reg = <0x2000 0x1000>;
 151                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 152                         };
 153                 };
 154
 155                 lpuart4: serial@402d0000 {
 156                         compatible = "fsl,imx7ulp-lpuart";
 157                         reg = <0x402d0000 0x1000>;
 158                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
 160                         clock-names = "ipg";
 161                         assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
 162                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
 163                         assigned-clock-rates = <24000000>;
 164                         status = "disabled";
 165                 };
 166
 167                 lpuart5: serial@402e0000 {
 168                         compatible = "fsl,imx7ulp-lpuart";
 169                         reg = <0x402e0000 0x1000>;
 170                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 171                         clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
 172                         clock-names = "ipg";
 173                         assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
 174                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
 175                         assigned-clock-rates = <48000000>;
 176                         status = "disabled";
 177                 };
 178
 179                 tpm4: pwm@40250000 {
 180                         compatible = "fsl,imx7ulp-pwm";
 181                         reg = <0x40250000 0x1000>;
 182                         assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
 183                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
 184                         clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
 185                         #pwm-cells = <3>;
 186                         status = "disabled";
 187                 };
 188
 189                 tpm5: tpm@40260000 {
 190                         compatible = "fsl,imx7ulp-tpm";
 191                         reg = <0x40260000 0x1000>;
 192                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 193                         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 194                                  <&pcc2 IMX7ULP_CLK_LPTPM5>;
 195                         clock-names = "ipg", "per";
 196                 };
 197
 198                 usbotg1: usb@40330000 {
 199                         compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
 200                         reg = <0x40330000 0x200>;
 201                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&pcc2 IMX7ULP_CLK_USB0>;
 203                         phys = <&usbphy1>;
 204                         fsl,usbmisc = <&usbmisc1 0>;
 205                         ahb-burst-config = <0x0>;
 206                         tx-burst-size-dword = <0x8>;
 207                         rx-burst-size-dword = <0x8>;
 208                         status = "disabled";
 209                 };
 210
 211                 usbmisc1: usbmisc@40330200 {
 212                         compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
 213                         #index-cells = <1>;
 214                         reg = <0x40330200 0x200>;
 215                 };
 216
 217                 usbphy1: usb-phy@40350000 {
 218                         compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
 219                         reg = <0x40350000 0x1000>;
 220                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 221                         clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
 222                         #phy-cells = <0>;
 223                 };
 224
 225                 usdhc0: mmc@40370000 {
 226                         compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
 227                         reg = <0x40370000 0x10000>;
 228                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 229                         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 230                                  <&scg1 IMX7ULP_CLK_NIC1_DIV>,
 231                                  <&pcc2 IMX7ULP_CLK_USDHC0>;
 232                         clock-names = "ipg", "ahb", "per";
 233                         assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
 234                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
 235                         bus-width = <4>;
 236                         fsl,tuning-start-tap = <20>;
 237                         fsl,tuning-step = <2>;
 238                         status = "disabled";
 239                 };
 240
 241                 usdhc1: mmc@40380000 {
 242                         compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
 243                         reg = <0x40380000 0x10000>;
 244                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 246                                  <&scg1 IMX7ULP_CLK_NIC1_DIV>,
 247                                  <&pcc2 IMX7ULP_CLK_USDHC1>;
 248                         clock-names = "ipg", "ahb", "per";
 249                         assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
 250                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
 251                         bus-width = <4>;
 252                         fsl,tuning-start-tap = <20>;
 253                         fsl,tuning-step = <2>;
 254                         status = "disabled";
 255                 };
 256
 257                 scg1: clock-controller@403e0000 {
 258                         compatible = "fsl,imx7ulp-scg1";
 259                         reg = <0x403e0000 0x10000>;
 260                         clocks = <&rosc>, <&sosc>, <&sirc>,
 261                                  <&firc>, <&upll>, <&mpll>;
 262                         clock-names = "rosc", "sosc", "sirc",
 263                                       "firc", "upll", "mpll";
 264                         #clock-cells = <1>;
 265                 };
 266
 267                 pcc2: clock-controller@403f0000 {
 268                         compatible = "fsl,imx7ulp-pcc2";
 269                         reg = <0x403f0000 0x10000>;
 270                         #clock-cells = <1>;
 271                         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 272                                  <&scg1 IMX7ULP_CLK_NIC1_DIV>,
 273                                  <&scg1 IMX7ULP_CLK_DDR_DIV>,
 274                                  <&scg1 IMX7ULP_CLK_APLL_PFD2>,
 275                                  <&scg1 IMX7ULP_CLK_APLL_PFD1>,
 276                                  <&scg1 IMX7ULP_CLK_APLL_PFD0>,
 277                                  <&scg1 IMX7ULP_CLK_UPLL>,
 278                                  <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
 279                                  <&scg1 IMX7ULP_CLK_MIPI_PLL>,
 280                                  <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
 281                                  <&scg1 IMX7ULP_CLK_ROSC>,
 282                                  <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
 283                         clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
 284                                       "apll_pfd2", "apll_pfd1", "apll_pfd0",
 285                                       "upll", "sosc_bus_clk", "mpll",
 286                                       "firc_bus_clk", "rosc", "spll_bus_clk";
 287                         assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
 288                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
 289                 };
 290
 291                 smc1: clock-controller@40410000 {
 292                         compatible = "fsl,imx7ulp-smc1";
 293                         reg = <0x40410000 0x1000>;
 294                         #clock-cells = <1>;
 295                         clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
 296                                  <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
 297                         clock-names = "divcore", "hsrun_divcore";
 298                 };
 299
 300                 pcc3: clock-controller@40b30000 {
 301                         compatible = "fsl,imx7ulp-pcc3";
 302                         reg = <0x40b30000 0x10000>;
 303                         #clock-cells = <1>;
 304                         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 305                                  <&scg1 IMX7ULP_CLK_NIC1_DIV>,
 306                                  <&scg1 IMX7ULP_CLK_DDR_DIV>,
 307                                  <&scg1 IMX7ULP_CLK_APLL_PFD2>,
 308                                  <&scg1 IMX7ULP_CLK_APLL_PFD1>,
 309                                  <&scg1 IMX7ULP_CLK_APLL_PFD0>,
 310                                  <&scg1 IMX7ULP_CLK_UPLL>,
 311                                  <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
 312                                  <&scg1 IMX7ULP_CLK_MIPI_PLL>,
 313                                  <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
 314                                  <&scg1 IMX7ULP_CLK_ROSC>,
 315                                  <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
 316                         clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
 317                                       "apll_pfd2", "apll_pfd1", "apll_pfd0",
 318                                       "upll", "sosc_bus_clk", "mpll",
 319                                       "firc_bus_clk", "rosc", "spll_bus_clk";
 320                 };
 321         };
 322
 323         ahbbridge1: bus@40800000 {
 324                 compatible = "simple-bus";
 325                 #address-cells = <1>;
 326                 #size-cells = <1>;
 327                 reg = <0x40800000 0x800000>;
 328                 ranges;
 329
 330                 lpi2c6: i2c@40a40000 {
 331                         compatible = "fsl,imx7ulp-lpi2c";
 332                         reg = <0x40a40000 0x10000>;
 333                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
 335                         clock-names = "ipg";
 336                         assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
 337                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
 338                         assigned-clock-rates = <48000000>;
 339                         status = "disabled";
 340                 };
 341
 342                 lpi2c7: i2c@40a50000 {
 343                         compatible = "fsl,imx7ulp-lpi2c";
 344                         reg = <0x40a50000 0x10000>;
 345                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
 347                         clock-names = "ipg";
 348                         assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
 349                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
 350                         assigned-clock-rates = <48000000>;
 351                         status = "disabled";
 352                 };
 353
 354                 lpuart6: serial@40a60000 {
 355                         compatible = "fsl,imx7ulp-lpuart";
 356                         reg = <0x40a60000 0x1000>;
 357                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 358                         clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
 359                         clock-names = "ipg";
 360                         assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
 361                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
 362                         assigned-clock-rates = <48000000>;
 363                         status = "disabled";
 364                 };
 365
 366                 lpuart7: serial@40a70000 {
 367                         compatible = "fsl,imx7ulp-lpuart";
 368                         reg = <0x40a70000 0x1000>;
 369                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
 371                         clock-names = "ipg";
 372                         assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
 373                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
 374                         assigned-clock-rates = <48000000>;
 375                         status = "disabled";
 376                 };
 377
 378                 memory-controller@40ab0000 {
 379                         compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
 380                         reg = <0x40ab0000 0x1000>;
 381                         clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
 382                 };
 383
 384                 iomuxc1: pinctrl@40ac0000 {
 385                         compatible = "fsl,imx7ulp-iomuxc1";
 386                         reg = <0x40ac0000 0x1000>;
 387                 };
 388
 389                 gpio_ptc: gpio@40ae0000 {
 390                         compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
 391                         reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
 392                         gpio-controller;
 393                         #gpio-cells = <2>;
 394                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 395                         interrupt-controller;
 396                         #interrupt-cells = <2>;
 397                         clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
 398                                  <&pcc3 IMX7ULP_CLK_PCTLC>;
 399                         clock-names = "gpio", "port";
 400                         gpio-ranges = <&iomuxc1 0 0 32>;
 401                 };
 402
 403                 gpio_ptd: gpio@40af0000 {
 404                         compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
 405                         reg = <0x40af0000 0x1000 0x400f0040 0x40>;
 406                         gpio-controller;
 407                         #gpio-cells = <2>;
 408                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 409                         interrupt-controller;
 410                         #interrupt-cells = <2>;
 411                         clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
 412                                  <&pcc3 IMX7ULP_CLK_PCTLD>;
 413                         clock-names = "gpio", "port";
 414                         gpio-ranges = <&iomuxc1 0 32 32>;
 415                 };
 416
 417                 gpio_pte: gpio@40b00000 {
 418                         compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
 419                         reg = <0x40b00000 0x1000 0x400f0080 0x40>;
 420                         gpio-controller;
 421                         #gpio-cells = <2>;
 422                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 423                         interrupt-controller;
 424                         #interrupt-cells = <2>;
 425                         clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
 426                                  <&pcc3 IMX7ULP_CLK_PCTLE>;
 427                         clock-names = "gpio", "port";
 428                         gpio-ranges = <&iomuxc1 0 64 32>;
 429                 };
 430
 431                 gpio_ptf: gpio@40b10000 {
 432                         compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
 433                         reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
 434                         gpio-controller;
 435                         #gpio-cells = <2>;
 436                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 437                         interrupt-controller;
 438                         #interrupt-cells = <2>;
 439                         clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
 440                                  <&pcc3 IMX7ULP_CLK_PCTLF>;
 441                         clock-names = "gpio", "port";
 442                         gpio-ranges = <&iomuxc1 0 96 32>;
 443                 };
 444         };
 445
 446         m4aips1: bus@41080000 {
 447                 compatible = "simple-bus";
 448                 #address-cells = <1>;
 449                 #size-cells = <1>;
 450                 reg = <0x41080000 0x80000>;
 451                 ranges;
 452
 453                 sim: sim@410a3000 {
 454                         compatible = "fsl,imx7ulp-sim", "syscon";
 455                         reg = <0x410a3000 0x1000>;
 456                 };
 457
 458                 ocotp: ocotp-ctrl@410a6000 {
 459                         compatible = "fsl,imx7ulp-ocotp", "syscon";
 460                         reg = <0x410a6000 0x4000>;
 461                         clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
 462                 };
 463         };
 464 };