arch/arm/boot/dts/imx7s.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  * Copyright 2016 Toradex AG
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/clock/imx7d-clock.h>
  45 #include <dt-bindings/power/imx7-power.h>
  46 #include <dt-bindings/gpio/gpio.h>
  47 #include <dt-bindings/input/input.h>
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49 #include "imx7d-pinfunc.h"
  50
  51 / {
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54         /*
  55          * The decompressor and also some bootloaders rely on a
  56          * pre-existing /chosen node to be available to insert the
  57          * command line and merge other ATAGS info.
  58          * Also for U-Boot there must be a pre-existing /memory node.
  59          */
  60         chosen {};
  61         memory { device_type = "memory"; reg = <0 0>; };
  62
  63         aliases {
  64                 gpio0 = &gpio1;
  65                 gpio1 = &gpio2;
  66                 gpio2 = &gpio3;
  67                 gpio3 = &gpio4;
  68                 gpio4 = &gpio5;
  69                 gpio5 = &gpio6;
  70                 gpio6 = &gpio7;
  71                 i2c0 = &i2c1;
  72                 i2c1 = &i2c2;
  73                 i2c2 = &i2c3;
  74                 i2c3 = &i2c4;
  75                 mmc0 = &usdhc1;
  76                 mmc1 = &usdhc2;
  77                 mmc2 = &usdhc3;
  78                 serial0 = &uart1;
  79                 serial1 = &uart2;
  80                 serial2 = &uart3;
  81                 serial3 = &uart4;
  82                 serial4 = &uart5;
  83                 serial5 = &uart6;
  84                 serial6 = &uart7;
  85                 spi0 = &ecspi1;
  86                 spi1 = &ecspi2;
  87                 spi2 = &ecspi3;
  88                 spi3 = &ecspi4;
  89         };
  90
  91         cpus {
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94
  95                 cpu0: cpu@0 {
  96                         compatible = "arm,cortex-a7";
  97                         device_type = "cpu";
  98                         reg = <0>;
  99                         clock-frequency = <792000000>;
 100                         clock-latency = <61036>; /* two CLK32 periods */
 101                         clocks = <&clks IMX7D_CLK_ARM>;
 102                 };
 103         };
 104
 105         ckil: clock-cki {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <32768>;
 109                 clock-output-names = "ckil";
 110         };
 111
 112         osc: clock-osc {
 113                 compatible = "fixed-clock";
 114                 #clock-cells = <0>;
 115                 clock-frequency = <24000000>;
 116                 clock-output-names = "osc";
 117         };
 118
 119         soc {
 120                 #address-cells = <1>;
 121                 #size-cells = <1>;
 122                 compatible = "simple-bus";
 123                 interrupt-parent = <&gpc>;
 124                 ranges;
 125
 126                 funnel@30041000 {
 127                         compatible = "arm,coresight-funnel", "arm,primecell";
 128                         reg = <0x30041000 0x1000>;
 129                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 130                         clock-names = "apb_pclk";
 131
 132                         ca_funnel_ports: ports {
 133                                 #address-cells = <1>;
 134                                 #size-cells = <0>;
 135
 136                                 /* funnel input ports */
 137                                 port@0 {
 138                                         reg = <0>;
 139                                         ca_funnel_in_port0: endpoint {
 140                                                 slave-mode;
 141                                                 remote-endpoint = <&etm0_out_port>;
 142                                         };
 143                                 };
 144
 145                                 /* funnel output port */
 146                                 port@2 {
 147                                         reg = <0>;
 148                                         ca_funnel_out_port0: endpoint {
 149                                                 remote-endpoint = <&hugo_funnel_in_port0>;
 150                                         };
 151                                 };
 152
 153                                 /* the other input ports are not connect to anything */
 154                         };
 155                 };
 156
 157                 etm@3007c000 {
 158                         compatible = "arm,coresight-etm3x", "arm,primecell";
 159                         reg = <0x3007c000 0x1000>;
 160                         cpu = <&cpu0>;
 161                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 162                         clock-names = "apb_pclk";
 163
 164                         port {
 165                                 etm0_out_port: endpoint {
 166                                         remote-endpoint = <&ca_funnel_in_port0>;
 167                                 };
 168                         };
 169                 };
 170
 171                 funnel@30083000 {
 172                         compatible = "arm,coresight-funnel", "arm,primecell";
 173                         reg = <0x30083000 0x1000>;
 174                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 175                         clock-names = "apb_pclk";
 176
 177                         ports {
 178                                 #address-cells = <1>;
 179                                 #size-cells = <0>;
 180
 181                                 /* funnel input ports */
 182                                 port@0 {
 183                                         reg = <0>;
 184                                         hugo_funnel_in_port0: endpoint {
 185                                                 slave-mode;
 186                                                 remote-endpoint = <&ca_funnel_out_port0>;
 187                                         };
 188                                 };
 189
 190                                 port@1 {
 191                                         reg = <1>;
 192                                         hugo_funnel_in_port1: endpoint {
 193                                                 slave-mode; /* M4 input */
 194                                         };
 195                                 };
 196
 197                                 port@2 {
 198                                         reg = <0>;
 199                                         hugo_funnel_out_port0: endpoint {
 200                                                 remote-endpoint = <&etf_in_port>;
 201                                         };
 202                                 };
 203
 204                                 /* the other input ports are not connect to anything */
 205                         };
 206                 };
 207
 208                 etf@30084000 {
 209                         compatible = "arm,coresight-tmc", "arm,primecell";
 210                         reg = <0x30084000 0x1000>;
 211                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 212                         clock-names = "apb_pclk";
 213
 214                         ports {
 215                                 #address-cells = <1>;
 216                                 #size-cells = <0>;
 217
 218                                 port@0 {
 219                                         reg = <0>;
 220                                         etf_in_port: endpoint {
 221                                                 slave-mode;
 222                                                 remote-endpoint = <&hugo_funnel_out_port0>;
 223                                         };
 224                                 };
 225
 226                                 port@1 {
 227                                         reg = <0>;
 228                                         etf_out_port: endpoint {
 229                                                 remote-endpoint = <&replicator_in_port0>;
 230                                         };
 231                                 };
 232                         };
 233                 };
 234
 235                 etr@30086000 {
 236                         compatible = "arm,coresight-tmc", "arm,primecell";
 237                         reg = <0x30086000 0x1000>;
 238                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 239                         clock-names = "apb_pclk";
 240
 241                         port {
 242                                 etr_in_port: endpoint {
 243                                         slave-mode;
 244                                         remote-endpoint = <&replicator_out_port1>;
 245                                 };
 246                         };
 247                 };
 248
 249                 tpiu@30087000 {
 250                         compatible = "arm,coresight-tpiu", "arm,primecell";
 251                         reg = <0x30087000 0x1000>;
 252                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 253                         clock-names = "apb_pclk";
 254
 255                         port {
 256                                 tpiu_in_port: endpoint {
 257                                         slave-mode;
 258                                         remote-endpoint = <&replicator_out_port1>;
 259                                 };
 260                         };
 261                 };
 262
 263                 replicator {
 264                         /*
 265                          * non-configurable replicators don't show up on the
 266                          * AMBA bus.  As such no need to add "arm,primecell"
 267                          */
 268                         compatible = "arm,coresight-replicator";
 269
 270                         ports {
 271                                 #address-cells = <1>;
 272                                 #size-cells = <0>;
 273
 274                                 /* replicator output ports */
 275                                 port@0 {
 276                                         reg = <0>;
 277                                         replicator_out_port0: endpoint {
 278                                                 remote-endpoint = <&tpiu_in_port>;
 279                                         };
 280                                 };
 281
 282                                 port@1 {
 283                                         reg = <1>;
 284                                         replicator_out_port1: endpoint {
 285                                                 remote-endpoint = <&etr_in_port>;
 286                                         };
 287                                 };
 288
 289                                 /* replicator input port */
 290                                 port@2 {
 291                                         reg = <0>;
 292                                         replicator_in_port0: endpoint {
 293                                                 slave-mode;
 294                                                 remote-endpoint = <&etf_out_port>;
 295                                         };
 296                                 };
 297                         };
 298                 };
 299
 300                 intc: interrupt-controller@31001000 {
 301                         compatible = "arm,cortex-a7-gic";
 302                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 303                         #interrupt-cells = <3>;
 304                         interrupt-controller;
 305                         interrupt-parent = <&intc>;
 306                         reg = <0x31001000 0x1000>,
 307                               <0x31002000 0x2000>,
 308                               <0x31004000 0x2000>,
 309                               <0x31006000 0x2000>;
 310                 };
 311
 312                 timer {
 313                         compatible = "arm,armv7-timer";
 314                         interrupt-parent = <&intc>;
 315                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 316                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 317                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 318                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 319                 };
 320
 321                 aips1: aips-bus@30000000 {
 322                         compatible = "fsl,aips-bus", "simple-bus";
 323                         #address-cells = <1>;
 324                         #size-cells = <1>;
 325                         reg = <0x30000000 0x400000>;
 326                         ranges;
 327
 328                         gpio1: gpio@30200000 {
 329                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 330                                 reg = <0x30200000 0x10000>;
 331                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
 332                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
 333                                 gpio-controller;
 334                                 #gpio-cells = <2>;
 335                                 interrupt-controller;
 336                                 #interrupt-cells = <2>;
 337                                 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
 338                         };
 339
 340                         gpio2: gpio@30210000 {
 341                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 342                                 reg = <0x30210000 0x10000>;
 343                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 344                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 345                                 gpio-controller;
 346                                 #gpio-cells = <2>;
 347                                 interrupt-controller;
 348                                 #interrupt-cells = <2>;
 349                                 gpio-ranges = <&iomuxc 0 13 32>;
 350                         };
 351
 352                         gpio3: gpio@30220000 {
 353                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 354                                 reg = <0x30220000 0x10000>;
 355                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 356                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 357                                 gpio-controller;
 358                                 #gpio-cells = <2>;
 359                                 interrupt-controller;
 360                                 #interrupt-cells = <2>;
 361                                 gpio-ranges = <&iomuxc 0 45 29>;
 362                         };
 363
 364                         gpio4: gpio@30230000 {
 365                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 366                                 reg = <0x30230000 0x10000>;
 367                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 368                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 369                                 gpio-controller;
 370                                 #gpio-cells = <2>;
 371                                 interrupt-controller;
 372                                 #interrupt-cells = <2>;
 373                                 gpio-ranges = <&iomuxc 0 74 24>;
 374                         };
 375
 376                         gpio5: gpio@30240000 {
 377                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 378                                 reg = <0x30240000 0x10000>;
 379                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 380                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 381                                 gpio-controller;
 382                                 #gpio-cells = <2>;
 383                                 interrupt-controller;
 384                                 #interrupt-cells = <2>;
 385                                 gpio-ranges = <&iomuxc 0 98 18>;
 386                         };
 387
 388                         gpio6: gpio@30250000 {
 389                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 390                                 reg = <0x30250000 0x10000>;
 391                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 392                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 393                                 gpio-controller;
 394                                 #gpio-cells = <2>;
 395                                 interrupt-controller;
 396                                 #interrupt-cells = <2>;
 397                                 gpio-ranges = <&iomuxc 0 116 23>;
 398                         };
 399
 400                         gpio7: gpio@30260000 {
 401                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 402                                 reg = <0x30260000 0x10000>;
 403                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 404                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 405                                 gpio-controller;
 406                                 #gpio-cells = <2>;
 407                                 interrupt-controller;
 408                                 #interrupt-cells = <2>;
 409                                 gpio-ranges = <&iomuxc 0 139 16>;
 410                         };
 411
 412                         wdog1: wdog@30280000 {
 413                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 414                                 reg = <0x30280000 0x10000>;
 415                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 416                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
 417                         };
 418
 419                         wdog2: wdog@30290000 {
 420                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 421                                 reg = <0x30290000 0x10000>;
 422                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 423                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
 424                                 status = "disabled";
 425                         };
 426
 427                         wdog3: wdog@302a0000 {
 428                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 429                                 reg = <0x302a0000 0x10000>;
 430                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 431                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
 432                                 status = "disabled";
 433                         };
 434
 435                         wdog4: wdog@302b0000 {
 436                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 437                                 reg = <0x302b0000 0x10000>;
 438                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 439                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
 440                                 status = "disabled";
 441                         };
 442
 443                         iomuxc_lpsr: iomuxc-lpsr@302c0000 {
 444                                 compatible = "fsl,imx7d-iomuxc-lpsr";
 445                                 reg = <0x302c0000 0x10000>;
 446                                 fsl,input-sel = <&iomuxc>;
 447                         };
 448
 449                         gpt1: gpt@302d0000 {
 450                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 451                                 reg = <0x302d0000 0x10000>;
 452                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 453                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 454                                          <&clks IMX7D_GPT1_ROOT_CLK>;
 455                                 clock-names = "ipg", "per";
 456                         };
 457
 458                         gpt2: gpt@302e0000 {
 459                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 460                                 reg = <0x302e0000 0x10000>;
 461                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 462                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 463                                          <&clks IMX7D_GPT2_ROOT_CLK>;
 464                                 clock-names = "ipg", "per";
 465                                 status = "disabled";
 466                         };
 467
 468                         gpt3: gpt@302f0000 {
 469                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 470                                 reg = <0x302f0000 0x10000>;
 471                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 472                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 473                                          <&clks IMX7D_GPT3_ROOT_CLK>;
 474                                 clock-names = "ipg", "per";
 475                                 status = "disabled";
 476                         };
 477
 478                         gpt4: gpt@30300000 {
 479                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 480                                 reg = <0x30300000 0x10000>;
 481                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 482                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 483                                          <&clks IMX7D_GPT4_ROOT_CLK>;
 484                                 clock-names = "ipg", "per";
 485                                 status = "disabled";
 486                         };
 487
 488                         iomuxc: iomuxc@30330000 {
 489                                 compatible = "fsl,imx7d-iomuxc";
 490                                 reg = <0x30330000 0x10000>;
 491                         };
 492
 493                         gpr: iomuxc-gpr@30340000 {
 494                                 compatible = "fsl,imx7d-iomuxc-gpr",
 495                                         "fsl,imx6q-iomuxc-gpr", "syscon";
 496                                 reg = <0x30340000 0x10000>;
 497                         };
 498
 499                         ocotp: ocotp-ctrl@30350000 {
 500                                 compatible = "fsl,imx7d-ocotp", "syscon";
 501                                 reg = <0x30350000 0x10000>;
 502                                 clocks = <&clks IMX7D_OCOTP_CLK>;
 503                         };
 504
 505                         anatop: anatop@30360000 {
 506                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
 507                                         "syscon", "simple-bus";
 508                                 reg = <0x30360000 0x10000>;
 509                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 510                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 511
 512                                 reg_1p0d: regulator-vdd1p0d {
 513                                         compatible = "fsl,anatop-regulator";
 514                                         regulator-name = "vdd1p0d";
 515                                         regulator-min-microvolt = <800000>;
 516                                         regulator-max-microvolt = <1200000>;
 517                                         anatop-reg-offset = <0x210>;
 518                                         anatop-vol-bit-shift = <8>;
 519                                         anatop-vol-bit-width = <5>;
 520                                         anatop-min-bit-val = <8>;
 521                                         anatop-min-voltage = <800000>;
 522                                         anatop-max-voltage = <1200000>;
 523                                         anatop-enable-bit = <0>;
 524                                 };
 525                         };
 526
 527                         snvs: snvs@30370000 {
 528                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 529                                 reg = <0x30370000 0x10000>;
 530
 531                                 snvs_rtc: snvs-rtc-lp {
 532                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 533                                         regmap = <&snvs>;
 534                                         offset = <0x34>;
 535                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 536                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 537                                 };
 538
 539                                 snvs_poweroff: snvs-poweroff {
 540                                         compatible = "syscon-poweroff";
 541                                         regmap = <&snvs>;
 542                                         offset = <0x38>;
 543                                         value = <0x60>;
 544                                         mask = <0x60>;
 545                                 };
 546
 547                                 snvs_pwrkey: snvs-powerkey {
 548                                         compatible = "fsl,sec-v4.0-pwrkey";
 549                                         regmap = <&snvs>;
 550                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 551                                         linux,keycode = <KEY_POWER>;
 552                                         wakeup-source;
 553                                 };
 554                         };
 555
 556                         clks: ccm@30380000 {
 557                                 compatible = "fsl,imx7d-ccm";
 558                                 reg = <0x30380000 0x10000>;
 559                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 560                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 561                                 #clock-cells = <1>;
 562                                 clocks = <&ckil>, <&osc>;
 563                                 clock-names = "ckil", "osc";
 564                         };
 565
 566                         src: src@30390000 {
 567                                 compatible = "fsl,imx7d-src", "syscon";
 568                                 reg = <0x30390000 0x10000>;
 569                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 570                                 #reset-cells = <1>;
 571                         };
 572
 573                         gpc: gpc@303a0000 {
 574                                 compatible = "fsl,imx7d-gpc";
 575                                 reg = <0x303a0000 0x10000>;
 576                                 interrupt-controller;
 577                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 578                                 #interrupt-cells = <3>;
 579                                 interrupt-parent = <&intc>;
 580                                 #power-domain-cells = <1>;
 581
 582                                 pgc {
 583                                         #address-cells = <1>;
 584                                         #size-cells = <0>;
 585
 586                                         pgc_pcie_phy: pgc-power-domain@IMX7_POWER_DOMAIN_PCIE_PHY {
 587                                                 #power-domain-cells = <0>;
 588                                                 reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
 589                                                 power-supply = <&reg_1p0d>;
 590                                         };
 591                                 };
 592                         };
 593                 };
 594
 595                 aips2: aips-bus@30400000 {
 596                         compatible = "fsl,aips-bus", "simple-bus";
 597                         #address-cells = <1>;
 598                         #size-cells = <1>;
 599                         reg = <0x30400000 0x400000>;
 600                         ranges;
 601
 602                         adc1: adc@30610000 {
 603                                 compatible = "fsl,imx7d-adc";
 604                                 reg = <0x30610000 0x10000>;
 605                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 606                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 607                                 clock-names = "adc";
 608                                 status = "disabled";
 609                         };
 610
 611                         adc2: adc@30620000 {
 612                                 compatible = "fsl,imx7d-adc";
 613                                 reg = <0x30620000 0x10000>;
 614                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 615                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 616                                 clock-names = "adc";
 617                                 status = "disabled";
 618                         };
 619
 620                         ecspi4: ecspi@30630000 {
 621                                 #address-cells = <1>;
 622                                 #size-cells = <0>;
 623                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 624                                 reg = <0x30630000 0x10000>;
 625                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 626                                 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
 627                                         <&clks IMX7D_ECSPI4_ROOT_CLK>;
 628                                 clock-names = "ipg", "per";
 629                                 status = "disabled";
 630                         };
 631
 632                         pwm1: pwm@30660000 {
 633                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 634                                 reg = <0x30660000 0x10000>;
 635                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 636                                 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
 637                                          <&clks IMX7D_PWM1_ROOT_CLK>;
 638                                 clock-names = "ipg", "per";
 639                                 #pwm-cells = <3>;
 640                                 status = "disabled";
 641                         };
 642
 643                         pwm2: pwm@30670000 {
 644                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 645                                 reg = <0x30670000 0x10000>;
 646                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 647                                 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
 648                                          <&clks IMX7D_PWM2_ROOT_CLK>;
 649                                 clock-names = "ipg", "per";
 650                                 #pwm-cells = <3>;
 651                                 status = "disabled";
 652                         };
 653
 654                         pwm3: pwm@30680000 {
 655                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 656                                 reg = <0x30680000 0x10000>;
 657                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 658                                 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
 659                                          <&clks IMX7D_PWM3_ROOT_CLK>;
 660                                 clock-names = "ipg", "per";
 661                                 #pwm-cells = <3>;
 662                                 status = "disabled";
 663                         };
 664
 665                         pwm4: pwm@30690000 {
 666                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 667                                 reg = <0x30690000 0x10000>;
 668                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 669                                 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
 670                                          <&clks IMX7D_PWM4_ROOT_CLK>;
 671                                 clock-names = "ipg", "per";
 672                                 #pwm-cells = <3>;
 673                                 status = "disabled";
 674                         };
 675
 676                         lcdif: lcdif@30730000 {
 677                                 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
 678                                 reg = <0x30730000 0x10000>;
 679                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 680                                 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
 681                                         <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
 682                                 clock-names = "pix", "axi";
 683                                 status = "disabled";
 684                         };
 685                 };
 686
 687                 aips3: aips-bus@30800000 {
 688                         compatible = "fsl,aips-bus", "simple-bus";
 689                         #address-cells = <1>;
 690                         #size-cells = <1>;
 691                         reg = <0x30800000 0x400000>;
 692                         ranges;
 693
 694                         ecspi1: ecspi@30820000 {
 695                                 #address-cells = <1>;
 696                                 #size-cells = <0>;
 697                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 698                                 reg = <0x30820000 0x10000>;
 699                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 700                                 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
 701                                         <&clks IMX7D_ECSPI1_ROOT_CLK>;
 702                                 clock-names = "ipg", "per";
 703                                 status = "disabled";
 704                         };
 705
 706                         ecspi2: ecspi@30830000 {
 707                                 #address-cells = <1>;
 708                                 #size-cells = <0>;
 709                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 710                                 reg = <0x30830000 0x10000>;
 711                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 712                                 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
 713                                         <&clks IMX7D_ECSPI2_ROOT_CLK>;
 714                                 clock-names = "ipg", "per";
 715                                 status = "disabled";
 716                         };
 717
 718                         ecspi3: ecspi@30840000 {
 719                                 #address-cells = <1>;
 720                                 #size-cells = <0>;
 721                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 722                                 reg = <0x30840000 0x10000>;
 723                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 724                                 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
 725                                         <&clks IMX7D_ECSPI3_ROOT_CLK>;
 726                                 clock-names = "ipg", "per";
 727                                 status = "disabled";
 728                         };
 729
 730                         uart1: serial@30860000 {
 731                                 compatible = "fsl,imx7d-uart",
 732                                              "fsl,imx6q-uart";
 733                                 reg = <0x30860000 0x10000>;
 734                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 735                                 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
 736                                         <&clks IMX7D_UART1_ROOT_CLK>;
 737                                 clock-names = "ipg", "per";
 738                                 status = "disabled";
 739                         };
 740
 741                         uart2: serial@30890000 {
 742                                 compatible = "fsl,imx7d-uart",
 743                                              "fsl,imx6q-uart";
 744                                 reg = <0x30890000 0x10000>;
 745                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 746                                 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
 747                                         <&clks IMX7D_UART2_ROOT_CLK>;
 748                                 clock-names = "ipg", "per";
 749                                 status = "disabled";
 750                         };
 751
 752                         uart3: serial@30880000 {
 753                                 compatible = "fsl,imx7d-uart",
 754                                              "fsl,imx6q-uart";
 755                                 reg = <0x30880000 0x10000>;
 756                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 757                                 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
 758                                         <&clks IMX7D_UART3_ROOT_CLK>;
 759                                 clock-names = "ipg", "per";
 760                                 status = "disabled";
 761                         };
 762
 763                         sai1: sai@308a0000 {
 764                                 #sound-dai-cells = <0>;
 765                                 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 766                                 reg = <0x308a0000 0x10000>;
 767                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 768                                 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
 769                                          <&clks IMX7D_SAI1_ROOT_CLK>,
 770                                          <&clks IMX7D_CLK_DUMMY>,
 771                                          <&clks IMX7D_CLK_DUMMY>;
 772                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 773                                 dma-names = "rx", "tx";
 774                                 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
 775                                 status = "disabled";
 776                         };
 777
 778                         sai2: sai@308b0000 {
 779                                 #sound-dai-cells = <0>;
 780                                 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 781                                 reg = <0x308b0000 0x10000>;
 782                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 783                                 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
 784                                          <&clks IMX7D_SAI2_ROOT_CLK>,
 785                                          <&clks IMX7D_CLK_DUMMY>,
 786                                          <&clks IMX7D_CLK_DUMMY>;
 787                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 788                                 dma-names = "rx", "tx";
 789                                 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
 790                                 status = "disabled";
 791                         };
 792
 793                         sai3: sai@308c0000 {
 794                                 #sound-dai-cells = <0>;
 795                                 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 796                                 reg = <0x308c0000 0x10000>;
 797                                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 798                                 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
 799                                          <&clks IMX7D_SAI3_ROOT_CLK>,
 800                                          <&clks IMX7D_CLK_DUMMY>,
 801                                          <&clks IMX7D_CLK_DUMMY>;
 802                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 803                                 dma-names = "rx", "tx";
 804                                 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
 805                                 status = "disabled";
 806                         };
 807
 808                         flexcan1: can@30a00000 {
 809                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 810                                 reg = <0x30a00000 0x10000>;
 811                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 812                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 813                                         <&clks IMX7D_CAN1_ROOT_CLK>;
 814                                 clock-names = "ipg", "per";
 815                                 status = "disabled";
 816                         };
 817
 818                         flexcan2: can@30a10000 {
 819                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 820                                 reg = <0x30a10000 0x10000>;
 821                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 822                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 823                                         <&clks IMX7D_CAN2_ROOT_CLK>;
 824                                 clock-names = "ipg", "per";
 825                                 status = "disabled";
 826                         };
 827
 828                         i2c1: i2c@30a20000 {
 829                                 #address-cells = <1>;
 830                                 #size-cells = <0>;
 831                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 832                                 reg = <0x30a20000 0x10000>;
 833                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 834                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
 835                                 status = "disabled";
 836                         };
 837
 838                         i2c2: i2c@30a30000 {
 839                                 #address-cells = <1>;
 840                                 #size-cells = <0>;
 841                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 842                                 reg = <0x30a30000 0x10000>;
 843                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 844                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
 845                                 status = "disabled";
 846                         };
 847
 848                         i2c3: i2c@30a40000 {
 849                                 #address-cells = <1>;
 850                                 #size-cells = <0>;
 851                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 852                                 reg = <0x30a40000 0x10000>;
 853                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 854                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
 855                                 status = "disabled";
 856                         };
 857
 858                         i2c4: i2c@30a50000 {
 859                                 #address-cells = <1>;
 860                                 #size-cells = <0>;
 861                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 862                                 reg = <0x30a50000 0x10000>;
 863                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 864                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
 865                                 status = "disabled";
 866                         };
 867
 868                         uart4: serial@30a60000 {
 869                                 compatible = "fsl,imx7d-uart",
 870                                              "fsl,imx6q-uart";
 871                                 reg = <0x30a60000 0x10000>;
 872                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 873                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
 874                                         <&clks IMX7D_UART4_ROOT_CLK>;
 875                                 clock-names = "ipg", "per";
 876                                 status = "disabled";
 877                         };
 878
 879                         uart5: serial@30a70000 {
 880                                 compatible = "fsl,imx7d-uart",
 881                                              "fsl,imx6q-uart";
 882                                 reg = <0x30a70000 0x10000>;
 883                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 884                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
 885                                         <&clks IMX7D_UART5_ROOT_CLK>;
 886                                 clock-names = "ipg", "per";
 887                                 status = "disabled";
 888                         };
 889
 890                         uart6: serial@30a80000 {
 891                                 compatible = "fsl,imx7d-uart",
 892                                              "fsl,imx6q-uart";
 893                                 reg = <0x30a80000 0x10000>;
 894                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 895                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
 896                                         <&clks IMX7D_UART6_ROOT_CLK>;
 897                                 clock-names = "ipg", "per";
 898                                 status = "disabled";
 899                         };
 900
 901                         uart7: serial@30a90000 {
 902                                 compatible = "fsl,imx7d-uart",
 903                                              "fsl,imx6q-uart";
 904                                 reg = <0x30a90000 0x10000>;
 905                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 906                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
 907                                         <&clks IMX7D_UART7_ROOT_CLK>;
 908                                 clock-names = "ipg", "per";
 909                                 status = "disabled";
 910                         };
 911
 912                         usbotg1: usb@30b10000 {
 913                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 914                                 reg = <0x30b10000 0x200>;
 915                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 916                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 917                                 fsl,usbphy = <&usbphynop1>;
 918                                 fsl,usbmisc = <&usbmisc1 0>;
 919                                 phy-clkgate-delay-us = <400>;
 920                                 status = "disabled";
 921                         };
 922
 923                         usbh: usb@30b30000 {
 924                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 925                                 reg = <0x30b30000 0x200>;
 926                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 927                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 928                                 fsl,usbphy = <&usbphynop3>;
 929                                 fsl,usbmisc = <&usbmisc3 0>;
 930                                 phy_type = "hsic";
 931                                 dr_mode = "host";
 932                                 phy-clkgate-delay-us = <400>;
 933                                 status = "disabled";
 934                         };
 935
 936                         usbmisc1: usbmisc@30b10200 {
 937                                 #index-cells = <1>;
 938                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 939                                 reg = <0x30b10200 0x200>;
 940                         };
 941
 942                         usbmisc3: usbmisc@30b30200 {
 943                                 #index-cells = <1>;
 944                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 945                                 reg = <0x30b30200 0x200>;
 946                         };
 947
 948                         usbphynop1: usbphynop1 {
 949                                 compatible = "usb-nop-xceiv";
 950                                 clocks = <&clks IMX7D_USB_PHY1_CLK>;
 951                                 clock-names = "main_clk";
 952                         };
 953
 954                         usbphynop3: usbphynop3 {
 955                                 compatible = "usb-nop-xceiv";
 956                                 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
 957                                 clock-names = "main_clk";
 958                         };
 959
 960                         usdhc1: usdhc@30b40000 {
 961                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 962                                 reg = <0x30b40000 0x10000>;
 963                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 964                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
 965                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
 966                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
 967                                 clock-names = "ipg", "ahb", "per";
 968                                 bus-width = <4>;
 969                                 status = "disabled";
 970                         };
 971
 972                         usdhc2: usdhc@30b50000 {
 973                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 974                                 reg = <0x30b50000 0x10000>;
 975                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 976                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
 977                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
 978                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
 979                                 clock-names = "ipg", "ahb", "per";
 980                                 bus-width = <4>;
 981                                 status = "disabled";
 982                         };
 983
 984                         usdhc3: usdhc@30b60000 {
 985                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 986                                 reg = <0x30b60000 0x10000>;
 987                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 988                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
 989                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
 990                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
 991                                 clock-names = "ipg", "ahb", "per";
 992                                 bus-width = <4>;
 993                                 status = "disabled";
 994                         };
 995
 996                         sdma: sdma@30bd0000 {
 997                                 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
 998                                 reg = <0x30bd0000 0x10000>;
 999                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1000                                 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
1001                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1002                                 clock-names = "ipg", "ahb";
1003                                 #dma-cells = <3>;
1004                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1005                         };
1006
1007                         fec1: ethernet@30be0000 {
1008                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1009                                 reg = <0x30be0000 0x10000>;
1010                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1011                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1012                                         <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1013                                 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1014                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1015                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1016                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1017                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1018                                 clock-names = "ipg", "ahb", "ptp",
1019                                         "enet_clk_ref", "enet_out";
1020                                 fsl,num-tx-queues=<3>;
1021                                 fsl,num-rx-queues=<3>;
1022                                 status = "disabled";
1023                         };
1024                 };
1025
1026                 dma_apbh: dma-apbh@33000000 {
1027                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1028                         reg = <0x33000000 0x2000>;
1029                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1030                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1031                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1032                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1033                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1034                         #dma-cells = <1>;
1035                         dma-channels = <4>;
1036                         clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1037                 };
1038
1039                 gpmi: gpmi-nand@33002000{
1040                         compatible = "fsl,imx7d-gpmi-nand";
1041                         #address-cells = <1>;
1042                         #size-cells = <1>;
1043                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1044                         reg-names = "gpmi-nand", "bch";
1045                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1046                         interrupt-names = "bch";
1047                         clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1048                                 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1049                         clock-names = "gpmi_io", "gpmi_bch_apb";
1050                         dmas = <&dma_apbh 0>;
1051                         dma-names = "rx-tx";
1052                         status = "disabled";
1053                         assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1054                         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1055                 };
1056         };
1057 };