arch/arm/boot/dts/imx7s.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  * Copyright 2016 Toradex AG
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/clock/imx7d-clock.h>
  45 #include <dt-bindings/power/imx7-power.h>
  46 #include <dt-bindings/gpio/gpio.h>
  47 #include <dt-bindings/input/input.h>
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49 #include "imx7d-pinfunc.h"
  50
  51 / {
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54         /*
  55          * The decompressor and also some bootloaders rely on a
  56          * pre-existing /chosen node to be available to insert the
  57          * command line and merge other ATAGS info.
  58          * Also for U-Boot there must be a pre-existing /memory node.
  59          */
  60         chosen {};
  61         memory { device_type = "memory"; reg = <0 0>; };
  62
  63         aliases {
  64                 gpio0 = &gpio1;
  65                 gpio1 = &gpio2;
  66                 gpio2 = &gpio3;
  67                 gpio3 = &gpio4;
  68                 gpio4 = &gpio5;
  69                 gpio5 = &gpio6;
  70                 gpio6 = &gpio7;
  71                 i2c0 = &i2c1;
  72                 i2c1 = &i2c2;
  73                 i2c2 = &i2c3;
  74                 i2c3 = &i2c4;
  75                 mmc0 = &usdhc1;
  76                 mmc1 = &usdhc2;
  77                 mmc2 = &usdhc3;
  78                 serial0 = &uart1;
  79                 serial1 = &uart2;
  80                 serial2 = &uart3;
  81                 serial3 = &uart4;
  82                 serial4 = &uart5;
  83                 serial5 = &uart6;
  84                 serial6 = &uart7;
  85                 spi0 = &ecspi1;
  86                 spi1 = &ecspi2;
  87                 spi2 = &ecspi3;
  88                 spi3 = &ecspi4;
  89         };
  90
  91         cpus {
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94
  95                 cpu0: cpu@0 {
  96                         compatible = "arm,cortex-a7";
  97                         device_type = "cpu";
  98                         reg = <0>;
  99                         clock-frequency = <792000000>;
 100                         clock-latency = <61036>; /* two CLK32 periods */
 101                         clocks = <&clks IMX7D_CLK_ARM>;
 102                 };
 103         };
 104
 105         ckil: clock-cki {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <32768>;
 109                 clock-output-names = "ckil";
 110         };
 111
 112         osc: clock-osc {
 113                 compatible = "fixed-clock";
 114                 #clock-cells = <0>;
 115                 clock-frequency = <24000000>;
 116                 clock-output-names = "osc";
 117         };
 118
 119         soc {
 120                 #address-cells = <1>;
 121                 #size-cells = <1>;
 122                 compatible = "simple-bus";
 123                 interrupt-parent = <&gpc>;
 124                 ranges;
 125
 126                 funnel@30041000 {
 127                         compatible = "arm,coresight-funnel", "arm,primecell";
 128                         reg = <0x30041000 0x1000>;
 129                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 130                         clock-names = "apb_pclk";
 131
 132                         ca_funnel_ports: ports {
 133                                 #address-cells = <1>;
 134                                 #size-cells = <0>;
 135
 136                                 /* funnel input ports */
 137                                 port@0 {
 138                                         reg = <0>;
 139                                         ca_funnel_in_port0: endpoint {
 140                                                 slave-mode;
 141                                                 remote-endpoint = <&etm0_out_port>;
 142                                         };
 143                                 };
 144
 145                                 /* funnel output port */
 146                                 port@2 {
 147                                         reg = <0>;
 148                                         ca_funnel_out_port0: endpoint {
 149                                                 remote-endpoint = <&hugo_funnel_in_port0>;
 150                                         };
 151                                 };
 152
 153                                 /* the other input ports are not connect to anything */
 154                         };
 155                 };
 156
 157                 etm@3007c000 {
 158                         compatible = "arm,coresight-etm3x", "arm,primecell";
 159                         reg = <0x3007c000 0x1000>;
 160                         cpu = <&cpu0>;
 161                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 162                         clock-names = "apb_pclk";
 163
 164                         port {
 165                                 etm0_out_port: endpoint {
 166                                         remote-endpoint = <&ca_funnel_in_port0>;
 167                                 };
 168                         };
 169                 };
 170
 171                 funnel@30083000 {
 172                         compatible = "arm,coresight-funnel", "arm,primecell";
 173                         reg = <0x30083000 0x1000>;
 174                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 175                         clock-names = "apb_pclk";
 176
 177                         ports {
 178                                 #address-cells = <1>;
 179                                 #size-cells = <0>;
 180
 181                                 /* funnel input ports */
 182                                 port@0 {
 183                                         reg = <0>;
 184                                         hugo_funnel_in_port0: endpoint {
 185                                                 slave-mode;
 186                                                 remote-endpoint = <&ca_funnel_out_port0>;
 187                                         };
 188                                 };
 189
 190                                 port@1 {
 191                                         reg = <1>;
 192                                         hugo_funnel_in_port1: endpoint {
 193                                                 slave-mode; /* M4 input */
 194                                         };
 195                                 };
 196
 197                                 port@2 {
 198                                         reg = <0>;
 199                                         hugo_funnel_out_port0: endpoint {
 200                                                 remote-endpoint = <&etf_in_port>;
 201                                         };
 202                                 };
 203
 204                                 /* the other input ports are not connect to anything */
 205                         };
 206                 };
 207
 208                 etf@30084000 {
 209                         compatible = "arm,coresight-tmc", "arm,primecell";
 210                         reg = <0x30084000 0x1000>;
 211                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 212                         clock-names = "apb_pclk";
 213
 214                         ports {
 215                                 #address-cells = <1>;
 216                                 #size-cells = <0>;
 217
 218                                 port@0 {
 219                                         reg = <0>;
 220                                         etf_in_port: endpoint {
 221                                                 slave-mode;
 222                                                 remote-endpoint = <&hugo_funnel_out_port0>;
 223                                         };
 224                                 };
 225
 226                                 port@1 {
 227                                         reg = <0>;
 228                                         etf_out_port: endpoint {
 229                                                 remote-endpoint = <&replicator_in_port0>;
 230                                         };
 231                                 };
 232                         };
 233                 };
 234
 235                 etr@30086000 {
 236                         compatible = "arm,coresight-tmc", "arm,primecell";
 237                         reg = <0x30086000 0x1000>;
 238                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 239                         clock-names = "apb_pclk";
 240
 241                         port {
 242                                 etr_in_port: endpoint {
 243                                         slave-mode;
 244                                         remote-endpoint = <&replicator_out_port1>;
 245                                 };
 246                         };
 247                 };
 248
 249                 tpiu@30087000 {
 250                         compatible = "arm,coresight-tpiu", "arm,primecell";
 251                         reg = <0x30087000 0x1000>;
 252                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 253                         clock-names = "apb_pclk";
 254
 255                         port {
 256                                 tpiu_in_port: endpoint {
 257                                         slave-mode;
 258                                         remote-endpoint = <&replicator_out_port1>;
 259                                 };
 260                         };
 261                 };
 262
 263                 replicator {
 264                         /*
 265                          * non-configurable replicators don't show up on the
 266                          * AMBA bus.  As such no need to add "arm,primecell"
 267                          */
 268                         compatible = "arm,coresight-replicator";
 269
 270                         ports {
 271                                 #address-cells = <1>;
 272                                 #size-cells = <0>;
 273
 274                                 /* replicator output ports */
 275                                 port@0 {
 276                                         reg = <0>;
 277                                         replicator_out_port0: endpoint {
 278                                                 remote-endpoint = <&tpiu_in_port>;
 279                                         };
 280                                 };
 281
 282                                 port@1 {
 283                                         reg = <1>;
 284                                         replicator_out_port1: endpoint {
 285                                                 remote-endpoint = <&etr_in_port>;
 286                                         };
 287                                 };
 288
 289                                 /* replicator input port */
 290                                 port@2 {
 291                                         reg = <0>;
 292                                         replicator_in_port0: endpoint {
 293                                                 slave-mode;
 294                                                 remote-endpoint = <&etf_out_port>;
 295                                         };
 296                                 };
 297                         };
 298                 };
 299
 300                 intc: interrupt-controller@31001000 {
 301                         compatible = "arm,cortex-a7-gic";
 302                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 303                         #interrupt-cells = <3>;
 304                         interrupt-controller;
 305                         interrupt-parent = <&intc>;
 306                         reg = <0x31001000 0x1000>,
 307                               <0x31002000 0x2000>,
 308                               <0x31004000 0x2000>,
 309                               <0x31006000 0x2000>;
 310                 };
 311
 312                 timer {
 313                         compatible = "arm,armv7-timer";
 314                         interrupt-parent = <&intc>;
 315                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 316                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 317                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 318                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 319                 };
 320
 321                 aips1: aips-bus@30000000 {
 322                         compatible = "fsl,aips-bus", "simple-bus";
 323                         #address-cells = <1>;
 324                         #size-cells = <1>;
 325                         reg = <0x30000000 0x400000>;
 326                         ranges;
 327
 328                         gpio1: gpio@30200000 {
 329                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 330                                 reg = <0x30200000 0x10000>;
 331                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
 332                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
 333                                 gpio-controller;
 334                                 #gpio-cells = <2>;
 335                                 interrupt-controller;
 336                                 #interrupt-cells = <2>;
 337                                 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
 338                         };
 339
 340                         gpio2: gpio@30210000 {
 341                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 342                                 reg = <0x30210000 0x10000>;
 343                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 344                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 345                                 gpio-controller;
 346                                 #gpio-cells = <2>;
 347                                 interrupt-controller;
 348                                 #interrupt-cells = <2>;
 349                                 gpio-ranges = <&iomuxc 0 13 32>;
 350                         };
 351
 352                         gpio3: gpio@30220000 {
 353                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 354                                 reg = <0x30220000 0x10000>;
 355                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 356                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 357                                 gpio-controller;
 358                                 #gpio-cells = <2>;
 359                                 interrupt-controller;
 360                                 #interrupt-cells = <2>;
 361                                 gpio-ranges = <&iomuxc 0 45 29>;
 362                         };
 363
 364                         gpio4: gpio@30230000 {
 365                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 366                                 reg = <0x30230000 0x10000>;
 367                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 368                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 369                                 gpio-controller;
 370                                 #gpio-cells = <2>;
 371                                 interrupt-controller;
 372                                 #interrupt-cells = <2>;
 373                                 gpio-ranges = <&iomuxc 0 74 24>;
 374                         };
 375
 376                         gpio5: gpio@30240000 {
 377                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 378                                 reg = <0x30240000 0x10000>;
 379                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 380                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 381                                 gpio-controller;
 382                                 #gpio-cells = <2>;
 383                                 interrupt-controller;
 384                                 #interrupt-cells = <2>;
 385                                 gpio-ranges = <&iomuxc 0 98 18>;
 386                         };
 387
 388                         gpio6: gpio@30250000 {
 389                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 390                                 reg = <0x30250000 0x10000>;
 391                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 392                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 393                                 gpio-controller;
 394                                 #gpio-cells = <2>;
 395                                 interrupt-controller;
 396                                 #interrupt-cells = <2>;
 397                                 gpio-ranges = <&iomuxc 0 116 23>;
 398                         };
 399
 400                         gpio7: gpio@30260000 {
 401                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 402                                 reg = <0x30260000 0x10000>;
 403                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 404                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 405                                 gpio-controller;
 406                                 #gpio-cells = <2>;
 407                                 interrupt-controller;
 408                                 #interrupt-cells = <2>;
 409                                 gpio-ranges = <&iomuxc 0 139 16>;
 410                         };
 411
 412                         wdog1: wdog@30280000 {
 413                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 414                                 reg = <0x30280000 0x10000>;
 415                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 416                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
 417                         };
 418
 419                         wdog2: wdog@30290000 {
 420                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 421                                 reg = <0x30290000 0x10000>;
 422                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 423                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
 424                                 status = "disabled";
 425                         };
 426
 427                         wdog3: wdog@302a0000 {
 428                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 429                                 reg = <0x302a0000 0x10000>;
 430                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 431                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
 432                                 status = "disabled";
 433                         };
 434
 435                         wdog4: wdog@302b0000 {
 436                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 437                                 reg = <0x302b0000 0x10000>;
 438                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 439                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
 440                                 status = "disabled";
 441                         };
 442
 443                         iomuxc_lpsr: iomuxc-lpsr@302c0000 {
 444                                 compatible = "fsl,imx7d-iomuxc-lpsr";
 445                                 reg = <0x302c0000 0x10000>;
 446                                 fsl,input-sel = <&iomuxc>;
 447                         };
 448
 449                         gpt1: gpt@302d0000 {
 450                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 451                                 reg = <0x302d0000 0x10000>;
 452                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 453                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 454                                          <&clks IMX7D_GPT1_ROOT_CLK>;
 455                                 clock-names = "ipg", "per";
 456                         };
 457
 458                         gpt2: gpt@302e0000 {
 459                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 460                                 reg = <0x302e0000 0x10000>;
 461                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 462                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 463                                          <&clks IMX7D_GPT2_ROOT_CLK>;
 464                                 clock-names = "ipg", "per";
 465                                 status = "disabled";
 466                         };
 467
 468                         gpt3: gpt@302f0000 {
 469                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 470                                 reg = <0x302f0000 0x10000>;
 471                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 472                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 473                                          <&clks IMX7D_GPT3_ROOT_CLK>;
 474                                 clock-names = "ipg", "per";
 475                                 status = "disabled";
 476                         };
 477
 478                         gpt4: gpt@30300000 {
 479                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 480                                 reg = <0x30300000 0x10000>;
 481                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 482                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 483                                          <&clks IMX7D_GPT4_ROOT_CLK>;
 484                                 clock-names = "ipg", "per";
 485                                 status = "disabled";
 486                         };
 487
 488                         iomuxc: iomuxc@30330000 {
 489                                 compatible = "fsl,imx7d-iomuxc";
 490                                 reg = <0x30330000 0x10000>;
 491                         };
 492
 493                         gpr: iomuxc-gpr@30340000 {
 494                                 compatible = "fsl,imx7d-iomuxc-gpr",
 495                                         "fsl,imx6q-iomuxc-gpr", "syscon";
 496                                 reg = <0x30340000 0x10000>;
 497                         };
 498
 499                         ocotp: ocotp-ctrl@30350000 {
 500                                 compatible = "fsl,imx7d-ocotp", "syscon";
 501                                 reg = <0x30350000 0x10000>;
 502                                 clocks = <&clks IMX7D_OCOTP_CLK>;
 503                         };
 504
 505                         anatop: anatop@30360000 {
 506                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
 507                                         "syscon", "simple-bus";
 508                                 reg = <0x30360000 0x10000>;
 509                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 510                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 511
 512                                 reg_1p0d: regulator-vdd1p0d {
 513                                         compatible = "fsl,anatop-regulator";
 514                                         regulator-name = "vdd1p0d";
 515                                         regulator-min-microvolt = <800000>;
 516                                         regulator-max-microvolt = <1200000>;
 517                                         anatop-reg-offset = <0x210>;
 518                                         anatop-vol-bit-shift = <8>;
 519                                         anatop-vol-bit-width = <5>;
 520                                         anatop-min-bit-val = <8>;
 521                                         anatop-min-voltage = <800000>;
 522                                         anatop-max-voltage = <1200000>;
 523                                         anatop-enable-bit = <0>;
 524                                 };
 525                         };
 526
 527                         snvs: snvs@30370000 {
 528                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 529                                 reg = <0x30370000 0x10000>;
 530
 531                                 snvs_rtc: snvs-rtc-lp {
 532                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 533                                         regmap = <&snvs>;
 534                                         offset = <0x34>;
 535                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 536                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 537                                 };
 538
 539                                 snvs_poweroff: snvs-poweroff {
 540                                         compatible = "syscon-poweroff";
 541                                         regmap = <&snvs>;
 542                                         offset = <0x38>;
 543                                         mask = <0x60>;
 544                                 };
 545
 546                                 snvs_pwrkey: snvs-powerkey {
 547                                         compatible = "fsl,sec-v4.0-pwrkey";
 548                                         regmap = <&snvs>;
 549                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 550                                         linux,keycode = <KEY_POWER>;
 551                                         wakeup-source;
 552                                 };
 553                         };
 554
 555                         clks: ccm@30380000 {
 556                                 compatible = "fsl,imx7d-ccm";
 557                                 reg = <0x30380000 0x10000>;
 558                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 559                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 560                                 #clock-cells = <1>;
 561                                 clocks = <&ckil>, <&osc>;
 562                                 clock-names = "ckil", "osc";
 563                         };
 564
 565                         src: src@30390000 {
 566                                 compatible = "fsl,imx7d-src", "syscon";
 567                                 reg = <0x30390000 0x10000>;
 568                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 569                                 #reset-cells = <1>;
 570                         };
 571
 572                         gpc: gpc@303a0000 {
 573                                 compatible = "fsl,imx7d-gpc";
 574                                 reg = <0x303a0000 0x10000>;
 575                                 interrupt-controller;
 576                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 577                                 #interrupt-cells = <3>;
 578                                 interrupt-parent = <&intc>;
 579                                 #power-domain-cells = <1>;
 580
 581                                 pgc {
 582                                         #address-cells = <1>;
 583                                         #size-cells = <0>;
 584
 585                                         pgc_pcie_phy: pgc-power-domain@IMX7_POWER_DOMAIN_PCIE_PHY {
 586                                                 #power-domain-cells = <0>;
 587                                                 reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
 588                                                 power-supply = <&reg_1p0d>;
 589                                         };
 590                                 };
 591                         };
 592                 };
 593
 594                 aips2: aips-bus@30400000 {
 595                         compatible = "fsl,aips-bus", "simple-bus";
 596                         #address-cells = <1>;
 597                         #size-cells = <1>;
 598                         reg = <0x30400000 0x400000>;
 599                         ranges;
 600
 601                         adc1: adc@30610000 {
 602                                 compatible = "fsl,imx7d-adc";
 603                                 reg = <0x30610000 0x10000>;
 604                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 605                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 606                                 clock-names = "adc";
 607                                 status = "disabled";
 608                         };
 609
 610                         adc2: adc@30620000 {
 611                                 compatible = "fsl,imx7d-adc";
 612                                 reg = <0x30620000 0x10000>;
 613                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 614                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 615                                 clock-names = "adc";
 616                                 status = "disabled";
 617                         };
 618
 619                         ecspi4: ecspi@30630000 {
 620                                 #address-cells = <1>;
 621                                 #size-cells = <0>;
 622                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 623                                 reg = <0x30630000 0x10000>;
 624                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 625                                 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
 626                                         <&clks IMX7D_ECSPI4_ROOT_CLK>;
 627                                 clock-names = "ipg", "per";
 628                                 status = "disabled";
 629                         };
 630
 631                         pwm1: pwm@30660000 {
 632                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 633                                 reg = <0x30660000 0x10000>;
 634                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 635                                 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
 636                                          <&clks IMX7D_PWM1_ROOT_CLK>;
 637                                 clock-names = "ipg", "per";
 638                                 #pwm-cells = <3>;
 639                                 status = "disabled";
 640                         };
 641
 642                         pwm2: pwm@30670000 {
 643                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 644                                 reg = <0x30670000 0x10000>;
 645                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 646                                 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
 647                                          <&clks IMX7D_PWM2_ROOT_CLK>;
 648                                 clock-names = "ipg", "per";
 649                                 #pwm-cells = <3>;
 650                                 status = "disabled";
 651                         };
 652
 653                         pwm3: pwm@30680000 {
 654                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 655                                 reg = <0x30680000 0x10000>;
 656                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 657                                 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
 658                                          <&clks IMX7D_PWM3_ROOT_CLK>;
 659                                 clock-names = "ipg", "per";
 660                                 #pwm-cells = <3>;
 661                                 status = "disabled";
 662                         };
 663
 664                         pwm4: pwm@30690000 {
 665                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 666                                 reg = <0x30690000 0x10000>;
 667                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 668                                 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
 669                                          <&clks IMX7D_PWM4_ROOT_CLK>;
 670                                 clock-names = "ipg", "per";
 671                                 #pwm-cells = <3>;
 672                                 status = "disabled";
 673                         };
 674
 675                         lcdif: lcdif@30730000 {
 676                                 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
 677                                 reg = <0x30730000 0x10000>;
 678                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 679                                 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
 680                                         <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
 681                                 clock-names = "pix", "axi";
 682                                 status = "disabled";
 683                         };
 684                 };
 685
 686                 aips3: aips-bus@30800000 {
 687                         compatible = "fsl,aips-bus", "simple-bus";
 688                         #address-cells = <1>;
 689                         #size-cells = <1>;
 690                         reg = <0x30800000 0x400000>;
 691                         ranges;
 692
 693                         ecspi1: ecspi@30820000 {
 694                                 #address-cells = <1>;
 695                                 #size-cells = <0>;
 696                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 697                                 reg = <0x30820000 0x10000>;
 698                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 699                                 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
 700                                         <&clks IMX7D_ECSPI1_ROOT_CLK>;
 701                                 clock-names = "ipg", "per";
 702                                 status = "disabled";
 703                         };
 704
 705                         ecspi2: ecspi@30830000 {
 706                                 #address-cells = <1>;
 707                                 #size-cells = <0>;
 708                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 709                                 reg = <0x30830000 0x10000>;
 710                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 711                                 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
 712                                         <&clks IMX7D_ECSPI2_ROOT_CLK>;
 713                                 clock-names = "ipg", "per";
 714                                 status = "disabled";
 715                         };
 716
 717                         ecspi3: ecspi@30840000 {
 718                                 #address-cells = <1>;
 719                                 #size-cells = <0>;
 720                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 721                                 reg = <0x30840000 0x10000>;
 722                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 723                                 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
 724                                         <&clks IMX7D_ECSPI3_ROOT_CLK>;
 725                                 clock-names = "ipg", "per";
 726                                 status = "disabled";
 727                         };
 728
 729                         uart1: serial@30860000 {
 730                                 compatible = "fsl,imx7d-uart",
 731                                              "fsl,imx6q-uart";
 732                                 reg = <0x30860000 0x10000>;
 733                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 734                                 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
 735                                         <&clks IMX7D_UART1_ROOT_CLK>;
 736                                 clock-names = "ipg", "per";
 737                                 status = "disabled";
 738                         };
 739
 740                         uart2: serial@30890000 {
 741                                 compatible = "fsl,imx7d-uart",
 742                                              "fsl,imx6q-uart";
 743                                 reg = <0x30890000 0x10000>;
 744                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 745                                 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
 746                                         <&clks IMX7D_UART2_ROOT_CLK>;
 747                                 clock-names = "ipg", "per";
 748                                 status = "disabled";
 749                         };
 750
 751                         uart3: serial@30880000 {
 752                                 compatible = "fsl,imx7d-uart",
 753                                              "fsl,imx6q-uart";
 754                                 reg = <0x30880000 0x10000>;
 755                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 756                                 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
 757                                         <&clks IMX7D_UART3_ROOT_CLK>;
 758                                 clock-names = "ipg", "per";
 759                                 status = "disabled";
 760                         };
 761
 762                         sai1: sai@308a0000 {
 763                                 #sound-dai-cells = <0>;
 764                                 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 765                                 reg = <0x308a0000 0x10000>;
 766                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 767                                 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
 768                                          <&clks IMX7D_SAI1_ROOT_CLK>,
 769                                          <&clks IMX7D_CLK_DUMMY>,
 770                                          <&clks IMX7D_CLK_DUMMY>;
 771                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 772                                 dma-names = "rx", "tx";
 773                                 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
 774                                 status = "disabled";
 775                         };
 776
 777                         sai2: sai@308b0000 {
 778                                 #sound-dai-cells = <0>;
 779                                 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 780                                 reg = <0x308b0000 0x10000>;
 781                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 782                                 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
 783                                          <&clks IMX7D_SAI2_ROOT_CLK>,
 784                                          <&clks IMX7D_CLK_DUMMY>,
 785                                          <&clks IMX7D_CLK_DUMMY>;
 786                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 787                                 dma-names = "rx", "tx";
 788                                 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
 789                                 status = "disabled";
 790                         };
 791
 792                         sai3: sai@308c0000 {
 793                                 #sound-dai-cells = <0>;
 794                                 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 795                                 reg = <0x308c0000 0x10000>;
 796                                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 797                                 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
 798                                          <&clks IMX7D_SAI3_ROOT_CLK>,
 799                                          <&clks IMX7D_CLK_DUMMY>,
 800                                          <&clks IMX7D_CLK_DUMMY>;
 801                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 802                                 dma-names = "rx", "tx";
 803                                 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
 804                                 status = "disabled";
 805                         };
 806
 807                         flexcan1: can@30a00000 {
 808                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 809                                 reg = <0x30a00000 0x10000>;
 810                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 811                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 812                                         <&clks IMX7D_CAN1_ROOT_CLK>;
 813                                 clock-names = "ipg", "per";
 814                                 status = "disabled";
 815                         };
 816
 817                         flexcan2: can@30a10000 {
 818                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 819                                 reg = <0x30a10000 0x10000>;
 820                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 821                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 822                                         <&clks IMX7D_CAN2_ROOT_CLK>;
 823                                 clock-names = "ipg", "per";
 824                                 status = "disabled";
 825                         };
 826
 827                         i2c1: i2c@30a20000 {
 828                                 #address-cells = <1>;
 829                                 #size-cells = <0>;
 830                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 831                                 reg = <0x30a20000 0x10000>;
 832                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 833                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
 834                                 status = "disabled";
 835                         };
 836
 837                         i2c2: i2c@30a30000 {
 838                                 #address-cells = <1>;
 839                                 #size-cells = <0>;
 840                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 841                                 reg = <0x30a30000 0x10000>;
 842                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 843                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
 844                                 status = "disabled";
 845                         };
 846
 847                         i2c3: i2c@30a40000 {
 848                                 #address-cells = <1>;
 849                                 #size-cells = <0>;
 850                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 851                                 reg = <0x30a40000 0x10000>;
 852                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 853                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
 854                                 status = "disabled";
 855                         };
 856
 857                         i2c4: i2c@30a50000 {
 858                                 #address-cells = <1>;
 859                                 #size-cells = <0>;
 860                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 861                                 reg = <0x30a50000 0x10000>;
 862                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 863                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
 864                                 status = "disabled";
 865                         };
 866
 867                         uart4: serial@30a60000 {
 868                                 compatible = "fsl,imx7d-uart",
 869                                              "fsl,imx6q-uart";
 870                                 reg = <0x30a60000 0x10000>;
 871                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 872                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
 873                                         <&clks IMX7D_UART4_ROOT_CLK>;
 874                                 clock-names = "ipg", "per";
 875                                 status = "disabled";
 876                         };
 877
 878                         uart5: serial@30a70000 {
 879                                 compatible = "fsl,imx7d-uart",
 880                                              "fsl,imx6q-uart";
 881                                 reg = <0x30a70000 0x10000>;
 882                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 883                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
 884                                         <&clks IMX7D_UART5_ROOT_CLK>;
 885                                 clock-names = "ipg", "per";
 886                                 status = "disabled";
 887                         };
 888
 889                         uart6: serial@30a80000 {
 890                                 compatible = "fsl,imx7d-uart",
 891                                              "fsl,imx6q-uart";
 892                                 reg = <0x30a80000 0x10000>;
 893                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 894                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
 895                                         <&clks IMX7D_UART6_ROOT_CLK>;
 896                                 clock-names = "ipg", "per";
 897                                 status = "disabled";
 898                         };
 899
 900                         uart7: serial@30a90000 {
 901                                 compatible = "fsl,imx7d-uart",
 902                                              "fsl,imx6q-uart";
 903                                 reg = <0x30a90000 0x10000>;
 904                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 905                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
 906                                         <&clks IMX7D_UART7_ROOT_CLK>;
 907                                 clock-names = "ipg", "per";
 908                                 status = "disabled";
 909                         };
 910
 911                         usbotg1: usb@30b10000 {
 912                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 913                                 reg = <0x30b10000 0x200>;
 914                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 915                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 916                                 fsl,usbphy = <&usbphynop1>;
 917                                 fsl,usbmisc = <&usbmisc1 0>;
 918                                 phy-clkgate-delay-us = <400>;
 919                                 status = "disabled";
 920                         };
 921
 922                         usbh: usb@30b30000 {
 923                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 924                                 reg = <0x30b30000 0x200>;
 925                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 926                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 927                                 fsl,usbphy = <&usbphynop3>;
 928                                 fsl,usbmisc = <&usbmisc3 0>;
 929                                 phy_type = "hsic";
 930                                 dr_mode = "host";
 931                                 phy-clkgate-delay-us = <400>;
 932                                 status = "disabled";
 933                         };
 934
 935                         usbmisc1: usbmisc@30b10200 {
 936                                 #index-cells = <1>;
 937                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 938                                 reg = <0x30b10200 0x200>;
 939                         };
 940
 941                         usbmisc3: usbmisc@30b30200 {
 942                                 #index-cells = <1>;
 943                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 944                                 reg = <0x30b30200 0x200>;
 945                         };
 946
 947                         usbphynop1: usbphynop1 {
 948                                 compatible = "usb-nop-xceiv";
 949                                 clocks = <&clks IMX7D_USB_PHY1_CLK>;
 950                                 clock-names = "main_clk";
 951                         };
 952
 953                         usbphynop3: usbphynop3 {
 954                                 compatible = "usb-nop-xceiv";
 955                                 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
 956                                 clock-names = "main_clk";
 957                         };
 958
 959                         usdhc1: usdhc@30b40000 {
 960                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 961                                 reg = <0x30b40000 0x10000>;
 962                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 963                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
 964                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
 965                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
 966                                 clock-names = "ipg", "ahb", "per";
 967                                 bus-width = <4>;
 968                                 status = "disabled";
 969                         };
 970
 971                         usdhc2: usdhc@30b50000 {
 972                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 973                                 reg = <0x30b50000 0x10000>;
 974                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 975                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
 976                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
 977                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
 978                                 clock-names = "ipg", "ahb", "per";
 979                                 bus-width = <4>;
 980                                 status = "disabled";
 981                         };
 982
 983                         usdhc3: usdhc@30b60000 {
 984                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 985                                 reg = <0x30b60000 0x10000>;
 986                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 987                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
 988                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
 989                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
 990                                 clock-names = "ipg", "ahb", "per";
 991                                 bus-width = <4>;
 992                                 status = "disabled";
 993                         };
 994
 995                         sdma: sdma@30bd0000 {
 996                                 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
 997                                 reg = <0x30bd0000 0x10000>;
 998                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 999                                 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
1000                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1001                                 clock-names = "ipg", "ahb";
1002                                 #dma-cells = <3>;
1003                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1004                         };
1005
1006                         fec1: ethernet@30be0000 {
1007                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1008                                 reg = <0x30be0000 0x10000>;
1009                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1010                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1011                                         <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1012                                 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1013                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1014                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1015                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1016                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1017                                 clock-names = "ipg", "ahb", "ptp",
1018                                         "enet_clk_ref", "enet_out";
1019                                 fsl,num-tx-queues=<3>;
1020                                 fsl,num-rx-queues=<3>;
1021                                 status = "disabled";
1022                         };
1023                 };
1024         };
1025 };