arch/arm/boot/dts/imx7d.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4 // Copyright 2016 Toradex AG
   5
   6 #include "imx7s.dtsi"
   7 #include <dt-bindings/reset/imx7-reset.h>
   8
   9 / {
  10         cpus {
  11                 cpu0: cpu@0 {
  12                         clock-frequency = <996000000>;
  13                         operating-points-v2 = <&cpu0_opp_table>;
  14                         #cooling-cells = <2>;
  15                 };
  16
  17                 cpu1: cpu@1 {
  18                         compatible = "arm,cortex-a7";
  19                         device_type = "cpu";
  20                         reg = <1>;
  21                         clock-frequency = <996000000>;
  22                         operating-points-v2 = <&cpu0_opp_table>;
  23                         cpu-idle-states = <&cpu_sleep_wait>;
  24                 };
  25         };
  26
  27         timer {
  28                 compatible = "arm,armv7-timer";
  29                 interrupt-parent = <&intc>;
  30                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  31                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  32                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  33                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  34         };
  35
  36         cpu0_opp_table: opp-table {
  37                 compatible = "operating-points-v2";
  38                 opp-shared;
  39
  40                 opp-792000000 {
  41                         opp-hz = /bits/ 64 <792000000>;
  42                         opp-microvolt = <975000>;
  43                         clock-latency-ns = <150000>;
  44                 };
  45
  46                 opp-996000000 {
  47                         opp-hz = /bits/ 64 <996000000>;
  48                         opp-microvolt = <1075000>;
  49                         clock-latency-ns = <150000>;
  50                         opp-suspend;
  51                 };
  52         };
  53
  54         usbphynop2: usbphynop2 {
  55                 compatible = "usb-nop-xceiv";
  56                 clocks = <&clks IMX7D_USB_PHY2_CLK>;
  57                 clock-names = "main_clk";
  58                 #phy-cells = <0>;
  59         };
  60
  61         soc {
  62                 etm@3007d000 {
  63                         compatible = "arm,coresight-etm3x", "arm,primecell";
  64                         reg = <0x3007d000 0x1000>;
  65
  66                         /*
  67                          * System will hang if added nosmp in kernel command line
  68                          * without arm,primecell-periphid because amba bus try to
  69                          * read id and core1 power off at this time.
  70                          */
  71                         arm,primecell-periphid = <0xbb956>;
  72                         cpu = <&cpu1>;
  73                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
  74                         clock-names = "apb_pclk";
  75
  76                         out-ports {
  77                                 port {
  78                                         etm1_out_port: endpoint {
  79                                                 remote-endpoint = <&ca_funnel_in_port1>;
  80                                         };
  81                                 };
  82                         };
  83                 };
  84
  85                 intc: interrupt-controller@31001000 {
  86                         compatible = "arm,cortex-a7-gic";
  87                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  88                         #interrupt-cells = <3>;
  89                         interrupt-controller;
  90                         interrupt-parent = <&intc>;
  91                         reg = <0x31001000 0x1000>,
  92                               <0x31002000 0x2000>,
  93                               <0x31004000 0x2000>,
  94                               <0x31006000 0x2000>;
  95                 };
  96         };
  97 };
  98
  99 &aips2 {
 100         pcie_phy: pcie-phy@306d0000 {
 101                   compatible = "fsl,imx7d-pcie-phy";
 102                   reg = <0x306d0000 0x10000>;
 103                   status = "disabled";
 104         };
 105 };
 106
 107 &aips3 {
 108         usbotg2: usb@30b20000 {
 109                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 110                 reg = <0x30b20000 0x200>;
 111                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 112                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 113                 fsl,usbphy = <&usbphynop2>;
 114                 fsl,usbmisc = <&usbmisc2 0>;
 115                 phy-clkgate-delay-us = <400>;
 116                 status = "disabled";
 117         };
 118
 119         usbmisc2: usbmisc@30b20200 {
 120                 #index-cells = <1>;
 121                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 122                 reg = <0x30b20200 0x200>;
 123         };
 124
 125         fec2: ethernet@30bf0000 {
 126                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
 127                 reg = <0x30bf0000 0x10000>;
 128                 interrupt-names = "int0", "int1", "int2", "pps";
 129                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 130                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 131                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 132                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 133                 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
 134                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 135                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
 136                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
 137                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
 138                 clock-names = "ipg", "ahb", "ptp",
 139                         "enet_clk_ref", "enet_out";
 140                 fsl,num-tx-queues=<3>;
 141                 fsl,num-rx-queues=<3>;
 142                 status = "disabled";
 143         };
 144
 145         pcie: pcie@33800000 {
 146                 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
 147                 reg = <0x33800000 0x4000>,
 148                       <0x4ff00000 0x80000>;
 149                 reg-names = "dbi", "config";
 150                 #address-cells = <3>;
 151                 #size-cells = <2>;
 152                 device_type = "pci";
 153                 bus-range = <0x00 0xff>;
 154                 ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
 155                           0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
 156                 num-lanes = <1>;
 157                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 158                 interrupt-names = "msi";
 159                 #interrupt-cells = <1>;
 160                 interrupt-map-mask = <0 0 0 0x7>;
 161                 /*
 162                  * Reference manual lists pci irqs incorrectly
 163                  * Real hardware ordering is same as imx6: D+MSI, C, B, A
 164                  */
 165                 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 166                                 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 167                                 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 168                                 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
 170                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
 171                          <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
 172                 clock-names = "pcie", "pcie_bus", "pcie_phy";
 173                 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
 174                                   <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
 175                 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
 176                                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 177
 178                 fsl,max-link-speed = <2>;
 179                 power-domains = <&pgc_pcie_phy>;
 180                 resets = <&src IMX7_RESET_PCIEPHY>,
 181                          <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
 182                          <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
 183                 reset-names = "pciephy", "apps", "turnoff";
 184                 fsl,imx7d-pcie-phy = <&pcie_phy>;
 185                 status = "disabled";
 186         };
 187 };
 188
 189 &ca_funnel_in_ports {
 190         #address-cells = <1>;
 191         #size-cells = <0>;
 192
 193         port@1 {
 194                 reg = <1>;
 195                 ca_funnel_in_port1: endpoint {
 196                         remote-endpoint = <&etm1_out_port>;
 197                 };
 198         };
 199 };