arch/arm/boot/dts/imx7d-sdb.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
   4
   5 /dts-v1/;
   6
   7 #include "imx7d.dtsi"
   8
   9 / {
  10         model = "Freescale i.MX7 SabreSD Board";
  11         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  12
  13         memory@80000000 {
  14                 reg = <0x80000000 0x80000000>;
  15         };
  16
  17         gpio-keys {
  18                 compatible = "gpio-keys";
  19                 pinctrl-names = "default";
  20                 pinctrl-0 = <&pinctrl_gpio_keys>;
  21
  22                 volume-up {
  23                         label = "Volume Up";
  24                         gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
  25                         linux,code = <KEY_VOLUMEUP>;
  26                 };
  27
  28                 volume-down {
  29                         label = "Volume Down";
  30                         gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
  31                         linux,code = <KEY_VOLUMEDOWN>;
  32                 };
  33         };
  34
  35         spi4 {
  36                 compatible = "spi-gpio";
  37                 pinctrl-names = "default";
  38                 pinctrl-0 = <&pinctrl_spi4>;
  39                 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  40                 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  41                 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  42                 num-chipselects = <1>;
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 extended_io: gpio-expander@0 {
  47                         compatible = "fairchild,74hc595";
  48                         gpio-controller;
  49                         #gpio-cells = <2>;
  50                         reg = <0>;
  51                         registers-number = <1>;
  52                         spi-max-frequency = <100000>;
  53                 };
  54         };
  55
  56         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "usb_otg1_vbus";
  59                 regulator-min-microvolt = <5000000>;
  60                 regulator-max-microvolt = <5000000>;
  61                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  62                 enable-active-high;
  63         };
  64
  65         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "usb_otg2_vbus";
  68                 regulator-min-microvolt = <5000000>;
  69                 regulator-max-microvolt = <5000000>;
  70                 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  71                 enable-active-high;
  72         };
  73
  74         reg_can2_3v3: regulator-can2-3v3 {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "can2-3v3";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
  80         };
  81
  82         reg_vref_1v8: regulator-vref-1v8 {
  83                 compatible = "regulator-fixed";
  84                 regulator-name = "vref-1v8";
  85                 regulator-min-microvolt = <1800000>;
  86                 regulator-max-microvolt = <1800000>;
  87         };
  88
  89         reg_brcm: regulator-brcm {
  90                 compatible = "regulator-fixed";
  91                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  92                 enable-active-high;
  93                 regulator-name = "brcm_reg";
  94                 pinctrl-names = "default";
  95                 pinctrl-0 = <&pinctrl_brcm_reg>;
  96                 regulator-min-microvolt = <3300000>;
  97                 regulator-max-microvolt = <3300000>;
  98                 startup-delay-us = <200000>;
  99         };
 100
 101         reg_lcd_3v3: regulator-lcd-3v3 {
 102                 compatible = "regulator-fixed";
 103                 regulator-name = "lcd-3v3";
 104                 regulator-min-microvolt = <3300000>;
 105                 regulator-max-microvolt = <3300000>;
 106                 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
 107         };
 108
 109         reg_can2_3v3: regulator-can2-3v3 {
 110                 compatible = "regulator-fixed";
 111                 regulator-name = "can2-3v3";
 112                 pinctrl-names = "default";
 113                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
 114                 regulator-min-microvolt = <3300000>;
 115                 regulator-max-microvolt = <3300000>;
 116                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
 117         };
 118
 119         panel {
 120                 compatible = "innolux,at043tn24";
 121                 pinctrl-0 = <&pinctrl_backlight>;
 122                 enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 123                 power-supply = <&reg_lcd_3v3>;
 124
 125                 port {
 126                         panel_in: endpoint {
 127                                 remote-endpoint = <&display_out>;
 128                         };
 129                 };
 130         };
 131 };
 132
 133 &adc1 {
 134         vref-supply = <&reg_vref_1v8>;
 135         status = "okay";
 136 };
 137
 138 &adc2 {
 139         vref-supply = <&reg_vref_1v8>;
 140         status = "okay";
 141 };
 142
 143 &cpu0 {
 144         cpu-supply = <&sw1a_reg>;
 145 };
 146
 147 &ecspi3 {
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&pinctrl_ecspi3>;
 150         cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 151         status = "okay";
 152
 153         tsc2046@0 {
 154                 compatible = "ti,tsc2046";
 155                 reg = <0>;
 156                 spi-max-frequency = <1000000>;
 157                 pinctrl-names ="default";
 158                 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
 159                 interrupt-parent = <&gpio2>;
 160                 interrupts = <29 0>;
 161                 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
 162                 ti,x-min = /bits/ 16 <0>;
 163                 ti,x-max = /bits/ 16 <0>;
 164                 ti,y-min = /bits/ 16 <0>;
 165                 ti,y-max = /bits/ 16 <0>;
 166                 ti,pressure-max = /bits/ 16 <0>;
 167                 ti,x-plate-ohms = /bits/ 16 <400>;
 168                 wakeup-source;
 169         };
 170 };
 171
 172 &fec1 {
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_enet1>;
 175         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 176                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 177         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 178         assigned-clock-rates = <0>, <100000000>;
 179         phy-mode = "rgmii";
 180         phy-handle = <&ethphy0>;
 181         fsl,magic-packet;
 182         phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
 183         status = "okay";
 184
 185         mdio {
 186                 #address-cells = <1>;
 187                 #size-cells = <0>;
 188
 189                 ethphy0: ethernet-phy@0 {
 190                         reg = <0>;
 191                 };
 192
 193                 ethphy1: ethernet-phy@1 {
 194                         reg = <1>;
 195                 };
 196         };
 197 };
 198
 199 &fec2 {
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&pinctrl_enet2>;
 202         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 203                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 204         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 205         assigned-clock-rates = <0>, <100000000>;
 206         phy-mode = "rgmii";
 207         phy-handle = <&ethphy1>;
 208         fsl,magic-packet;
 209         status = "okay";
 210 };
 211
 212 &flexcan2 {
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&pinctrl_flexcan2>;
 215         xceiver-supply = <&reg_can2_3v3>;
 216         status = "okay";
 217 };
 218
 219 &i2c1 {
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pinctrl_i2c1>;
 222         status = "okay";
 223
 224         pmic: pfuze3000@8 {
 225                 compatible = "fsl,pfuze3000";
 226                 reg = <0x08>;
 227
 228                 regulators {
 229                         sw1a_reg: sw1a {
 230                                 regulator-min-microvolt = <700000>;
 231                                 regulator-max-microvolt = <1475000>;
 232                                 regulator-boot-on;
 233                                 regulator-always-on;
 234                                 regulator-ramp-delay = <6250>;
 235                         };
 236
 237                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 238                         sw1c_reg: sw1b {
 239                                 regulator-min-microvolt = <700000>;
 240                                 regulator-max-microvolt = <1475000>;
 241                                 regulator-boot-on;
 242                                 regulator-always-on;
 243                                 regulator-ramp-delay = <6250>;
 244                         };
 245
 246                         sw2_reg: sw2 {
 247                                 regulator-min-microvolt = <1500000>;
 248                                 regulator-max-microvolt = <1850000>;
 249                                 regulator-boot-on;
 250                                 regulator-always-on;
 251                         };
 252
 253                         sw3a_reg: sw3 {
 254                                 regulator-min-microvolt = <900000>;
 255                                 regulator-max-microvolt = <1650000>;
 256                                 regulator-boot-on;
 257                                 regulator-always-on;
 258                         };
 259
 260                         swbst_reg: swbst {
 261                                 regulator-min-microvolt = <5000000>;
 262                                 regulator-max-microvolt = <5150000>;
 263                         };
 264
 265                         snvs_reg: vsnvs {
 266                                 regulator-min-microvolt = <1000000>;
 267                                 regulator-max-microvolt = <3000000>;
 268                                 regulator-boot-on;
 269                                 regulator-always-on;
 270                         };
 271
 272                         vref_reg: vrefddr {
 273                                 regulator-boot-on;
 274                                 regulator-always-on;
 275                         };
 276
 277                         vgen1_reg: vldo1 {
 278                                 regulator-min-microvolt = <1800000>;
 279                                 regulator-max-microvolt = <3300000>;
 280                                 regulator-always-on;
 281                         };
 282
 283                         vgen2_reg: vldo2 {
 284                                 regulator-min-microvolt = <800000>;
 285                                 regulator-max-microvolt = <1550000>;
 286                         };
 287
 288                         vgen3_reg: vccsd {
 289                                 regulator-min-microvolt = <2850000>;
 290                                 regulator-max-microvolt = <3300000>;
 291                                 regulator-always-on;
 292                         };
 293
 294                         vgen4_reg: v33 {
 295                                 regulator-min-microvolt = <2850000>;
 296                                 regulator-max-microvolt = <3300000>;
 297                                 regulator-always-on;
 298                         };
 299
 300                         vgen5_reg: vldo3 {
 301                                 regulator-min-microvolt = <1800000>;
 302                                 regulator-max-microvolt = <3300000>;
 303                                 regulator-always-on;
 304                         };
 305
 306                         vgen6_reg: vldo4 {
 307                                 regulator-min-microvolt = <2800000>;
 308                                 regulator-max-microvolt = <2800000>;
 309                                 regulator-always-on;
 310                         };
 311                 };
 312         };
 313 };
 314
 315 &i2c2 {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&pinctrl_i2c2>;
 318         status = "okay";
 319
 320         mpl3115@60 {
 321                 compatible = "fsl,mpl3115";
 322                 reg = <0x60>;
 323         };
 324 };
 325
 326 &i2c3 {
 327         pinctrl-names = "default";
 328         pinctrl-0 = <&pinctrl_i2c3>;
 329         status = "okay";
 330 };
 331
 332 &i2c4 {
 333         pinctrl-names = "default";
 334         pinctrl-0 = <&pinctrl_i2c4>;
 335         status = "okay";
 336
 337         codec: wm8960@1a {
 338                 compatible = "wlf,wm8960";
 339                 reg = <0x1a>;
 340                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 341                 clock-names = "mclk";
 342                 wlf,shared-lrclk;
 343         };
 344 };
 345
 346 &lcdif {
 347         pinctrl-names = "default";
 348         pinctrl-0 = <&pinctrl_lcdif>;
 349         status = "okay";
 350
 351         port {
 352                 display_out: endpoint {
 353                         remote-endpoint = <&panel_in>;
 354                 };
 355         };
 356 };
 357
 358 &pcie {
 359         reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
 360         status = "okay";
 361 };
 362
 363 &uart1 {
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_uart1>;
 366         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 367         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 368         status = "okay";
 369 };
 370
 371 &uart6 {
 372         pinctrl-names = "default";
 373         pinctrl-0 = <&pinctrl_uart6>;
 374         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 375         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 376         uart-has-rtscts;
 377         status = "okay";
 378 };
 379
 380 &usbotg1 {
 381         vbus-supply = <&reg_usb_otg1_vbus>;
 382         status = "okay";
 383 };
 384
 385 &usbotg2 {
 386         vbus-supply = <&reg_usb_otg2_vbus>;
 387         dr_mode = "host";
 388         status = "okay";
 389 };
 390
 391 &usdhc1 {
 392         pinctrl-names = "default";
 393         pinctrl-0 = <&pinctrl_usdhc1>;
 394         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 395         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 396         wakeup-source;
 397         keep-power-in-suspend;
 398         status = "okay";
 399 };
 400
 401 &usdhc2 {
 402         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 403         pinctrl-0 = <&pinctrl_usdhc2>;
 404         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 405         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 406         wakeup-source;
 407         keep-power-in-suspend;
 408         non-removable;
 409         vmmc-supply = <&reg_brcm>;
 410         fsl,tuning-step = <2>;
 411         status = "okay";
 412 };
 413
 414 &usdhc3 {
 415         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 416         pinctrl-0 = <&pinctrl_usdhc3>;
 417         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 418         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 419         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 420         assigned-clock-rates = <400000000>;
 421         bus-width = <8>;
 422         fsl,tuning-step = <2>;
 423         non-removable;
 424         status = "okay";
 425 };
 426
 427 &wdog1 {
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&pinctrl_wdog>;
 430         fsl,ext-reset-output;
 431 };
 432
 433 &iomuxc {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&pinctrl_hog>;
 436
 437         imx7d-sdb {
 438                 pinctrl_brcm_reg: brcmreggrp {
 439                         fsl,pins = <
 440                                 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x14
 441                         >;
 442                 };
 443
 444                 pinctrl_ecspi3: ecspi3grp {
 445                         fsl,pins = <
 446                                 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
 447                                 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
 448                                 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
 449                                 MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
 450                         >;
 451                 };
 452
 453                 pinctrl_enet1: enet1grp {
 454                         fsl,pins = <
 455                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 456                                 MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 457                                 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 458                                 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 459                                 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 460                                 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 461                                 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 462                                 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 463                                 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 464                                 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 465                                 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 466                                 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 467                                 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 468                                 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 469                         >;
 470                 };
 471
 472                 pinctrl_enet2: enet2grp {
 473                         fsl,pins = <
 474                                 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 475                                 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 476                                 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 477                                 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 478                                 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 479                                 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 480                                 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 481                                 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 482                                 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 483                                 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 484                                 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 485                                 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 486                         >;
 487                 };
 488
 489                 pinctrl_flexcan2: flexcan2grp {
 490                         fsl,pins = <
 491                                 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
 492                                 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
 493                         >;
 494                 };
 495
 496                 pinctrl_flexcan2_reg: flexcan2reggrp {
 497                         fsl,pins = <
 498                                 MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x59    /* CAN_STBY */
 499                         >;
 500                 };
 501
 502                 pinctrl_gpio_keys: gpio_keysgrp {
 503                         fsl,pins = <
 504                                 MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x59
 505                                 MX7D_PAD_SD2_WP__GPIO5_IO10             0x59
 506                         >;
 507                 };
 508
 509                 pinctrl_hog: hoggrp {
 510                         fsl,pins = <
 511                                 MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 512                                 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
 513                         >;
 514                 };
 515
 516                 pinctrl_i2c1: i2c1grp {
 517                         fsl,pins = <
 518                                 MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 519                                 MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 520                         >;
 521                 };
 522
 523                 pinctrl_i2c2: i2c2grp {
 524                         fsl,pins = <
 525                                 MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 526                                 MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 527                         >;
 528                 };
 529
 530                 pinctrl_i2c3: i2c3grp {
 531                         fsl,pins = <
 532                                 MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 533                                 MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 534                         >;
 535                 };
 536
 537                 pinctrl_i2c4: i2c4grp {
 538                         fsl,pins = <
 539                                 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 540                                 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 541                         >;
 542                 };
 543
 544                 pinctrl_lcdif: lcdifgrp {
 545                         fsl,pins = <
 546                                 MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 547                                 MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 548                                 MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 549                                 MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 550                                 MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 551                                 MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 552                                 MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 553                                 MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 554                                 MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 555                                 MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 556                                 MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 557                                 MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 558                                 MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 559                                 MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 560                                 MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 561                                 MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 562                                 MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 563                                 MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 564                                 MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 565                                 MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 566                                 MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 567                                 MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 568                                 MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 569                                 MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 570                                 MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 571                                 MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 572                                 MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 573                                 MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 574                                 MX7D_PAD_LCD_RESET__LCD_RESET           0x79
 575                         >;
 576                 };
 577
 578                 pinctrl_spi4: spi4grp {
 579                         fsl,pins = <
 580                                 MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
 581                                 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
 582                                 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
 583                         >;
 584                 };
 585
 586                 pinctrl_tsc2046_pendown: tsc2046_pendown {
 587                         fsl,pins = <
 588                                 MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
 589                         >;
 590                 };
 591
 592                 pinctrl_uart1: uart1grp {
 593                         fsl,pins = <
 594                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 595                                 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 596                         >;
 597                 };
 598
 599                 pinctrl_uart5: uart5grp {
 600                         fsl,pins = <
 601                                 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
 602                                 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
 603                                 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
 604                                 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
 605                         >;
 606                 };
 607
 608                 pinctrl_uart6: uart6grp {
 609                         fsl,pins = <
 610                                 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 611                                 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 612                                 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 613                                 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 614                         >;
 615                 };
 616
 617                 pinctrl_usdhc1: usdhc1grp {
 618                         fsl,pins = <
 619                                 MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 620                                 MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 621                                 MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 622                                 MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 623                                 MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 624                                 MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 625                                 MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
 626                                 MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
 627                                 MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
 628                         >;
 629                 };
 630
 631                 pinctrl_usdhc2: usdhc2grp {
 632                         fsl,pins = <
 633                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 634                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 635                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 636                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 637                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 638                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 639                         >;
 640                 };
 641
 642                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
 643                         fsl,pins = <
 644                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
 645                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
 646                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
 647                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
 648                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
 649                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
 650                         >;
 651                 };
 652
 653                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
 654                         fsl,pins = <
 655                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
 656                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
 657                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
 658                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
 659                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
 660                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
 661                         >;
 662                 };
 663
 664
 665                 pinctrl_usdhc3: usdhc3grp {
 666                         fsl,pins = <
 667                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 668                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 669                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 670                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 671                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 672                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 673                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 674                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 675                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 676                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 677                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 678                         >;
 679                 };
 680
 681                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 682                         fsl,pins = <
 683                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 684                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 685                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 686                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 687                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 688                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 689                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 690                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 691                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 692                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 693                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 694                         >;
 695                 };
 696
 697                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 698                         fsl,pins = <
 699                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 700                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 701                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 702                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 703                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 704                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 705                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 706                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 707                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 708                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 709                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 710                         >;
 711                 };
 712         };
 713 };
 714
 715 &iomuxc_lpsr {
 716         pinctrl_wdog: wdoggrp {
 717                 fsl,pins = <
 718                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B          0x74
 719                 >;
 720         };
 721
 722         pinctrl_backlight: backlightgrp {
 723                 fsl,pins = <
 724                         MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1             0x110b0
 725                 >;
 726         };
 727 };