arch/arm/boot/dts/imx7d-sdb.dts

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /dts-v1/;
  44
  45 #include "imx7d.dtsi"
  46
  47 / {
  48         model = "Freescale i.MX7 SabreSD Board";
  49         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  50
  51         memory@80000000 {
  52                 reg = <0x80000000 0x80000000>;
  53         };
  54
  55         spi4 {
  56                 compatible = "spi-gpio";
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&pinctrl_spi4>;
  59                 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  60                 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  61                 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  62                 num-chipselects = <1>;
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65
  66                 extended_io: gpio-expander@0 {
  67                         compatible = "fairchild,74hc595";
  68                         gpio-controller;
  69                         #gpio-cells = <2>;
  70                         reg = <0>;
  71                         registers-number = <1>;
  72                         spi-max-frequency = <100000>;
  73                 };
  74         };
  75
  76         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  77                 compatible = "regulator-fixed";
  78                 regulator-name = "usb_otg1_vbus";
  79                 regulator-min-microvolt = <5000000>;
  80                 regulator-max-microvolt = <5000000>;
  81                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  82                 enable-active-high;
  83         };
  84
  85         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "usb_otg2_vbus";
  88                 regulator-min-microvolt = <5000000>;
  89                 regulator-max-microvolt = <5000000>;
  90                 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  91                 enable-active-high;
  92         };
  93
  94         reg_can2_3v3: regulator-can2-3v3 {
  95                 compatible = "regulator-fixed";
  96                 regulator-name = "can2-3v3";
  97                 regulator-min-microvolt = <3300000>;
  98                 regulator-max-microvolt = <3300000>;
  99                 gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
 100         };
 101
 102         reg_vref_1v8: regulator-vref-1v8 {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "vref-1v8";
 105                 regulator-min-microvolt = <1800000>;
 106                 regulator-max-microvolt = <1800000>;
 107         };
 108
 109         reg_brcm: regulator-brcm {
 110                 compatible = "regulator-fixed";
 111                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 112                 enable-active-high;
 113                 regulator-name = "brcm_reg";
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_brcm_reg>;
 116                 regulator-min-microvolt = <3300000>;
 117                 regulator-max-microvolt = <3300000>;
 118                 startup-delay-us = <200000>;
 119         };
 120
 121         reg_lcd_3v3: regulator-lcd-3v3 {
 122                 compatible = "regulator-fixed";
 123                 regulator-name = "lcd-3v3";
 124                 regulator-min-microvolt = <3300000>;
 125                 regulator-max-microvolt = <3300000>;
 126                 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
 127         };
 128
 129         reg_can2_3v3: regulator-can2-3v3 {
 130                 compatible = "regulator-fixed";
 131                 regulator-name = "can2-3v3";
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
 134                 regulator-min-microvolt = <3300000>;
 135                 regulator-max-microvolt = <3300000>;
 136                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
 137         };
 138
 139         panel {
 140                 compatible = "innolux,at043tn24";
 141                 pinctrl-0 = <&pinctrl_backlight>;
 142                 enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 143                 power-supply = <&reg_lcd_3v3>;
 144
 145                 port {
 146                         panel_in: endpoint {
 147                                 remote-endpoint = <&display_out>;
 148                         };
 149                 };
 150         };
 151 };
 152
 153 &adc1 {
 154         vref-supply = <&reg_vref_1v8>;
 155         status = "okay";
 156 };
 157
 158 &adc2 {
 159         vref-supply = <&reg_vref_1v8>;
 160         status = "okay";
 161 };
 162
 163 &cpu0 {
 164         arm-supply = <&sw1a_reg>;
 165 };
 166
 167 &ecspi3 {
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_ecspi3>;
 170         cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 171         status = "okay";
 172
 173         tsc2046@0 {
 174                 compatible = "ti,tsc2046";
 175                 reg = <0>;
 176                 spi-max-frequency = <1000000>;
 177                 pinctrl-names ="default";
 178                 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
 179                 interrupt-parent = <&gpio2>;
 180                 interrupts = <29 0>;
 181                 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
 182                 ti,x-min = /bits/ 16 <0>;
 183                 ti,x-max = /bits/ 16 <0>;
 184                 ti,y-min = /bits/ 16 <0>;
 185                 ti,y-max = /bits/ 16 <0>;
 186                 ti,pressure-max = /bits/ 16 <0>;
 187                 ti,x-plate-ohms = /bits/ 16 <400>;
 188                 wakeup-source;
 189         };
 190 };
 191
 192 &fec1 {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&pinctrl_enet1>;
 195         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 196                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 197         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 198         assigned-clock-rates = <0>, <100000000>;
 199         phy-mode = "rgmii";
 200         phy-handle = <&ethphy0>;
 201         fsl,magic-packet;
 202         phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
 203         status = "okay";
 204
 205         mdio {
 206                 #address-cells = <1>;
 207                 #size-cells = <0>;
 208
 209                 ethphy0: ethernet-phy@0 {
 210                         reg = <0>;
 211                 };
 212
 213                 ethphy1: ethernet-phy@1 {
 214                         reg = <1>;
 215                 };
 216         };
 217 };
 218
 219 &fec2 {
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pinctrl_enet2>;
 222         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 223                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 224         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 225         assigned-clock-rates = <0>, <100000000>;
 226         phy-mode = "rgmii";
 227         phy-handle = <&ethphy1>;
 228         fsl,magic-packet;
 229         status = "okay";
 230 };
 231
 232 &flexcan2 {
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_flexcan2>;
 235         xceiver-supply = <&reg_can2_3v3>;
 236         status = "okay";
 237 };
 238
 239 &i2c1 {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_i2c1>;
 242         status = "okay";
 243
 244         pmic: pfuze3000@8 {
 245                 compatible = "fsl,pfuze3000";
 246                 reg = <0x08>;
 247
 248                 regulators {
 249                         sw1a_reg: sw1a {
 250                                 regulator-min-microvolt = <700000>;
 251                                 regulator-max-microvolt = <1475000>;
 252                                 regulator-boot-on;
 253                                 regulator-always-on;
 254                                 regulator-ramp-delay = <6250>;
 255                         };
 256
 257                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 258                         sw1c_reg: sw1b {
 259                                 regulator-min-microvolt = <700000>;
 260                                 regulator-max-microvolt = <1475000>;
 261                                 regulator-boot-on;
 262                                 regulator-always-on;
 263                                 regulator-ramp-delay = <6250>;
 264                         };
 265
 266                         sw2_reg: sw2 {
 267                                 regulator-min-microvolt = <1500000>;
 268                                 regulator-max-microvolt = <1850000>;
 269                                 regulator-boot-on;
 270                                 regulator-always-on;
 271                         };
 272
 273                         sw3a_reg: sw3 {
 274                                 regulator-min-microvolt = <900000>;
 275                                 regulator-max-microvolt = <1650000>;
 276                                 regulator-boot-on;
 277                                 regulator-always-on;
 278                         };
 279
 280                         swbst_reg: swbst {
 281                                 regulator-min-microvolt = <5000000>;
 282                                 regulator-max-microvolt = <5150000>;
 283                         };
 284
 285                         snvs_reg: vsnvs {
 286                                 regulator-min-microvolt = <1000000>;
 287                                 regulator-max-microvolt = <3000000>;
 288                                 regulator-boot-on;
 289                                 regulator-always-on;
 290                         };
 291
 292                         vref_reg: vrefddr {
 293                                 regulator-boot-on;
 294                                 regulator-always-on;
 295                         };
 296
 297                         vgen1_reg: vldo1 {
 298                                 regulator-min-microvolt = <1800000>;
 299                                 regulator-max-microvolt = <3300000>;
 300                                 regulator-always-on;
 301                         };
 302
 303                         vgen2_reg: vldo2 {
 304                                 regulator-min-microvolt = <800000>;
 305                                 regulator-max-microvolt = <1550000>;
 306                         };
 307
 308                         vgen3_reg: vccsd {
 309                                 regulator-min-microvolt = <2850000>;
 310                                 regulator-max-microvolt = <3300000>;
 311                                 regulator-always-on;
 312                         };
 313
 314                         vgen4_reg: v33 {
 315                                 regulator-min-microvolt = <2850000>;
 316                                 regulator-max-microvolt = <3300000>;
 317                                 regulator-always-on;
 318                         };
 319
 320                         vgen5_reg: vldo3 {
 321                                 regulator-min-microvolt = <1800000>;
 322                                 regulator-max-microvolt = <3300000>;
 323                                 regulator-always-on;
 324                         };
 325
 326                         vgen6_reg: vldo4 {
 327                                 regulator-min-microvolt = <2800000>;
 328                                 regulator-max-microvolt = <2800000>;
 329                                 regulator-always-on;
 330                         };
 331                 };
 332         };
 333 };
 334
 335 &i2c2 {
 336         pinctrl-names = "default";
 337         pinctrl-0 = <&pinctrl_i2c2>;
 338         status = "okay";
 339
 340         mpl3115@60 {
 341                 compatible = "fsl,mpl3115";
 342                 reg = <0x60>;
 343         };
 344 };
 345
 346 &i2c3 {
 347         pinctrl-names = "default";
 348         pinctrl-0 = <&pinctrl_i2c3>;
 349         status = "okay";
 350 };
 351
 352 &i2c4 {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_i2c4>;
 355         status = "okay";
 356
 357         codec: wm8960@1a {
 358                 compatible = "wlf,wm8960";
 359                 reg = <0x1a>;
 360                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 361                 clock-names = "mclk";
 362                 wlf,shared-lrclk;
 363         };
 364 };
 365
 366 &lcdif {
 367         pinctrl-names = "default";
 368         pinctrl-0 = <&pinctrl_lcdif>;
 369         status = "okay";
 370
 371         port {
 372                 display_out: endpoint {
 373                         remote-endpoint = <&panel_in>;
 374                 };
 375         };
 376 };
 377
 378 &pcie {
 379         reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
 380         status = "okay";
 381 };
 382
 383 &uart1 {
 384         pinctrl-names = "default";
 385         pinctrl-0 = <&pinctrl_uart1>;
 386         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 387         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 388         status = "okay";
 389 };
 390
 391 &uart6 {
 392         pinctrl-names = "default";
 393         pinctrl-0 = <&pinctrl_uart6>;
 394         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 395         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 396         uart-has-rtscts;
 397         status = "okay";
 398 };
 399
 400 &usbotg1 {
 401         vbus-supply = <&reg_usb_otg1_vbus>;
 402         status = "okay";
 403 };
 404
 405 &usbotg2 {
 406         vbus-supply = <&reg_usb_otg2_vbus>;
 407         dr_mode = "host";
 408         status = "okay";
 409 };
 410
 411 &usdhc1 {
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_usdhc1>;
 414         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 415         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 416         wakeup-source;
 417         keep-power-in-suspend;
 418         status = "okay";
 419 };
 420
 421 &usdhc2 {
 422         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 423         pinctrl-0 = <&pinctrl_usdhc2>;
 424         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 425         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 426         wakeup-source;
 427         keep-power-in-suspend;
 428         non-removable;
 429         vmmc-supply = <&reg_brcm>;
 430         fsl,tuning-step = <2>;
 431         status = "okay";
 432 };
 433
 434 &usdhc3 {
 435         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 436         pinctrl-0 = <&pinctrl_usdhc3>;
 437         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 438         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 439         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 440         assigned-clock-rates = <400000000>;
 441         bus-width = <8>;
 442         fsl,tuning-step = <2>;
 443         non-removable;
 444         status = "okay";
 445 };
 446
 447 &wdog1 {
 448         pinctrl-names = "default";
 449         pinctrl-0 = <&pinctrl_wdog>;
 450         fsl,ext-reset-output;
 451 };
 452
 453 &iomuxc {
 454         pinctrl-names = "default";
 455         pinctrl-0 = <&pinctrl_hog>;
 456
 457         imx7d-sdb {
 458                 pinctrl_brcm_reg: brcmreggrp {
 459                         fsl,pins = <
 460                                 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x14
 461                         >;
 462                 };
 463
 464                 pinctrl_ecspi3: ecspi3grp {
 465                         fsl,pins = <
 466                                 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
 467                                 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
 468                                 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
 469                                 MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
 470                         >;
 471                 };
 472
 473                 pinctrl_enet1: enet1grp {
 474                         fsl,pins = <
 475                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 476                                 MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 477                                 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 478                                 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 479                                 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 480                                 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 481                                 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 482                                 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 483                                 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 484                                 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 485                                 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 486                                 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 487                                 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 488                                 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 489                         >;
 490                 };
 491
 492                 pinctrl_enet2: enet2grp {
 493                         fsl,pins = <
 494                                 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 495                                 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 496                                 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 497                                 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 498                                 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 499                                 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 500                                 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 501                                 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 502                                 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 503                                 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 504                                 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 505                                 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 506                         >;
 507                 };
 508
 509                 pinctrl_flexcan2: flexcan2grp {
 510                         fsl,pins = <
 511                                 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
 512                                 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
 513                         >;
 514                 };
 515
 516                 pinctrl_flexcan2_reg: flexcan2reggrp {
 517                         fsl,pins = <
 518                                 MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x59    /* CAN_STBY */
 519                         >;
 520                 };
 521
 522
 523                 pinctrl_hog: hoggrp {
 524                         fsl,pins = <
 525                                 MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 526                                 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
 527                         >;
 528                 };
 529
 530                 pinctrl_i2c1: i2c1grp {
 531                         fsl,pins = <
 532                                 MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 533                                 MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 534                         >;
 535                 };
 536
 537                 pinctrl_i2c2: i2c2grp {
 538                         fsl,pins = <
 539                                 MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 540                                 MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 541                         >;
 542                 };
 543
 544                 pinctrl_i2c3: i2c3grp {
 545                         fsl,pins = <
 546                                 MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 547                                 MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 548                         >;
 549                 };
 550
 551                 pinctrl_i2c4: i2c4grp {
 552                         fsl,pins = <
 553                                 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 554                                 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 555                         >;
 556                 };
 557
 558                 pinctrl_lcdif: lcdifgrp {
 559                         fsl,pins = <
 560                                 MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 561                                 MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 562                                 MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 563                                 MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 564                                 MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 565                                 MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 566                                 MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 567                                 MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 568                                 MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 569                                 MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 570                                 MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 571                                 MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 572                                 MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 573                                 MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 574                                 MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 575                                 MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 576                                 MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 577                                 MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 578                                 MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 579                                 MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 580                                 MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 581                                 MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 582                                 MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 583                                 MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 584                                 MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 585                                 MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 586                                 MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 587                                 MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 588                                 MX7D_PAD_LCD_RESET__LCD_RESET           0x79
 589                         >;
 590                 };
 591
 592                 pinctrl_spi4: spi4grp {
 593                         fsl,pins = <
 594                                 MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
 595                                 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
 596                                 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
 597                         >;
 598                 };
 599
 600                 pinctrl_tsc2046_pendown: tsc2046_pendown {
 601                         fsl,pins = <
 602                                 MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
 603                         >;
 604                 };
 605
 606                 pinctrl_uart1: uart1grp {
 607                         fsl,pins = <
 608                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 609                                 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 610                         >;
 611                 };
 612
 613                 pinctrl_uart5: uart5grp {
 614                         fsl,pins = <
 615                                 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
 616                                 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
 617                                 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
 618                                 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
 619                         >;
 620                 };
 621
 622                 pinctrl_uart6: uart6grp {
 623                         fsl,pins = <
 624                                 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 625                                 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 626                                 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 627                                 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 628                         >;
 629                 };
 630
 631                 pinctrl_usdhc1: usdhc1grp {
 632                         fsl,pins = <
 633                                 MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 634                                 MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 635                                 MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 636                                 MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 637                                 MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 638                                 MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 639                                 MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
 640                                 MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
 641                                 MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
 642                         >;
 643                 };
 644
 645                 pinctrl_usdhc2: usdhc2grp {
 646                         fsl,pins = <
 647                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 648                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 649                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 650                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 651                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 652                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 653                         >;
 654                 };
 655
 656                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
 657                         fsl,pins = <
 658                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
 659                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
 660                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
 661                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
 662                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
 663                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
 664                         >;
 665                 };
 666
 667                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
 668                         fsl,pins = <
 669                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
 670                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
 671                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
 672                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
 673                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
 674                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
 675                         >;
 676                 };
 677
 678
 679                 pinctrl_usdhc3: usdhc3grp {
 680                         fsl,pins = <
 681                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 682                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 683                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 684                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 685                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 686                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 687                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 688                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 689                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 690                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 691                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 692                         >;
 693                 };
 694
 695                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 696                         fsl,pins = <
 697                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 698                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 699                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 700                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 701                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 702                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 703                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 704                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 705                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 706                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 707                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 708                         >;
 709                 };
 710
 711                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 712                         fsl,pins = <
 713                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 714                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 715                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 716                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 717                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 718                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 719                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 720                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 721                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 722                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 723                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 724                         >;
 725                 };
 726         };
 727 };
 728
 729 &iomuxc_lpsr {
 730         pinctrl_wdog: wdoggrp {
 731                 fsl,pins = <
 732                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B          0x74
 733                 >;
 734         };
 735
 736         pinctrl_backlight: backlightgrp {
 737                 fsl,pins = <
 738                         MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1             0x110b0
 739                 >;
 740         };
 741 };