arch/arm/boot/dts/imx7d-sdb.dts

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /dts-v1/;
  44
  45 #include "imx7d.dtsi"
  46
  47 / {
  48         model = "Freescale i.MX7 SabreSD Board";
  49         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  50
  51         memory {
  52                 reg = <0x80000000 0x80000000>;
  53         };
  54
  55         regulators {
  56                 compatible = "simple-bus";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 reg_usb_otg1_vbus: regulator@0 {
  61                         compatible = "regulator-fixed";
  62                         reg = <0>;
  63                         regulator-name = "usb_otg1_vbus";
  64                         regulator-min-microvolt = <5000000>;
  65                         regulator-max-microvolt = <5000000>;
  66                         gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  67                         enable-active-high;
  68                 };
  69
  70                 reg_usb_otg2_vbus: regulator@1 {
  71                         compatible = "regulator-fixed";
  72                         reg = <1>;
  73                         regulator-name = "usb_otg2_vbus";
  74                         regulator-min-microvolt = <5000000>;
  75                         regulator-max-microvolt = <5000000>;
  76                         gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  77                         enable-active-high;
  78                 };
  79
  80                 reg_can2_3v3: regulator@2 {
  81                         compatible = "regulator-fixed";
  82                         reg = <2>;
  83                         regulator-name = "can2-3v3";
  84                         regulator-min-microvolt = <3300000>;
  85                         regulator-max-microvolt = <3300000>;
  86                         gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
  87                 };
  88
  89                 reg_vref_1v8: regulator@3 {
  90                         compatible = "regulator-fixed";
  91                         reg = <3>;
  92                         regulator-name = "vref-1v8";
  93                         regulator-min-microvolt = <1800000>;
  94                         regulator-max-microvolt = <1800000>;
  95                 };
  96         };
  97 };
  98
  99 &adc1 {
 100         vref-supply = <&reg_vref_1v8>;
 101         status = "okay";
 102 };
 103
 104 &adc2 {
 105         vref-supply = <&reg_vref_1v8>;
 106         status = "okay";
 107 };
 108
 109 &cpu0 {
 110         arm-supply = <&sw1a_reg>;
 111 };
 112
 113 &ecspi3 {
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&pinctrl_ecspi3>;
 116         cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 117         status = "okay";
 118
 119         tsc2046@0 {
 120                 compatible = "ti,tsc2046";
 121                 reg = <0>;
 122                 spi-max-frequency = <1000000>;
 123                 pinctrl-names ="default";
 124                 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
 125                 interrupt-parent = <&gpio2>;
 126                 interrupts = <29 0>;
 127                 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
 128                 ti,x-min = /bits/ 16 <0>;
 129                 ti,x-max = /bits/ 16 <0>;
 130                 ti,y-min = /bits/ 16 <0>;
 131                 ti,y-max = /bits/ 16 <0>;
 132                 ti,pressure-max = /bits/ 16 <0>;
 133                 ti,x-plate-ohms = /bits/ 16 <400>;
 134                 wakeup-source;
 135         };
 136 };
 137
 138 &fec1 {
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_enet1>;
 141         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 142                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 143         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 144         assigned-clock-rates = <0>, <100000000>;
 145         phy-mode = "rgmii";
 146         phy-handle = <&ethphy0>;
 147         fsl,magic-packet;
 148         status = "okay";
 149
 150         mdio {
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153
 154                 ethphy0: ethernet-phy@0 {
 155                         reg = <0>;
 156                 };
 157
 158                 ethphy1: ethernet-phy@1 {
 159                         reg = <1>;
 160                 };
 161         };
 162 };
 163
 164 &fec2 {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&pinctrl_enet2>;
 167         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 168                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 169         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 170         assigned-clock-rates = <0>, <100000000>;
 171         phy-mode = "rgmii";
 172         phy-handle = <&ethphy1>;
 173         fsl,magic-packet;
 174         status = "okay";
 175 };
 176
 177 &i2c1 {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_i2c1>;
 180         status = "okay";
 181
 182         pmic: pfuze3000@08 {
 183                 compatible = "fsl,pfuze3000";
 184                 reg = <0x08>;
 185
 186                 regulators {
 187                         sw1a_reg: sw1a {
 188                                 regulator-min-microvolt = <700000>;
 189                                 regulator-max-microvolt = <1475000>;
 190                                 regulator-boot-on;
 191                                 regulator-always-on;
 192                                 regulator-ramp-delay = <6250>;
 193                         };
 194
 195                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 196                         sw1c_reg: sw1b {
 197                                 regulator-min-microvolt = <700000>;
 198                                 regulator-max-microvolt = <1475000>;
 199                                 regulator-boot-on;
 200                                 regulator-always-on;
 201                                 regulator-ramp-delay = <6250>;
 202                         };
 203
 204                         sw2_reg: sw2 {
 205                                 regulator-min-microvolt = <1500000>;
 206                                 regulator-max-microvolt = <1850000>;
 207                                 regulator-boot-on;
 208                                 regulator-always-on;
 209                         };
 210
 211                         sw3a_reg: sw3 {
 212                                 regulator-min-microvolt = <900000>;
 213                                 regulator-max-microvolt = <1650000>;
 214                                 regulator-boot-on;
 215                                 regulator-always-on;
 216                         };
 217
 218                         swbst_reg: swbst {
 219                                 regulator-min-microvolt = <5000000>;
 220                                 regulator-max-microvolt = <5150000>;
 221                         };
 222
 223                         snvs_reg: vsnvs {
 224                                 regulator-min-microvolt = <1000000>;
 225                                 regulator-max-microvolt = <3000000>;
 226                                 regulator-boot-on;
 227                                 regulator-always-on;
 228                         };
 229
 230                         vref_reg: vrefddr {
 231                                 regulator-boot-on;
 232                                 regulator-always-on;
 233                         };
 234
 235                         vgen1_reg: vldo1 {
 236                                 regulator-min-microvolt = <1800000>;
 237                                 regulator-max-microvolt = <3300000>;
 238                                 regulator-always-on;
 239                         };
 240
 241                         vgen2_reg: vldo2 {
 242                                 regulator-min-microvolt = <800000>;
 243                                 regulator-max-microvolt = <1550000>;
 244                         };
 245
 246                         vgen3_reg: vccsd {
 247                                 regulator-min-microvolt = <2850000>;
 248                                 regulator-max-microvolt = <3300000>;
 249                                 regulator-always-on;
 250                         };
 251
 252                         vgen4_reg: v33 {
 253                                 regulator-min-microvolt = <2850000>;
 254                                 regulator-max-microvolt = <3300000>;
 255                                 regulator-always-on;
 256                         };
 257
 258                         vgen5_reg: vldo3 {
 259                                 regulator-min-microvolt = <1800000>;
 260                                 regulator-max-microvolt = <3300000>;
 261                                 regulator-always-on;
 262                         };
 263
 264                         vgen6_reg: vldo4 {
 265                                 regulator-min-microvolt = <1800000>;
 266                                 regulator-max-microvolt = <3300000>;
 267                                 regulator-always-on;
 268                         };
 269                 };
 270         };
 271 };
 272
 273 &i2c2 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_i2c2>;
 276         status = "okay";
 277 };
 278
 279 &i2c3 {
 280         pinctrl-names = "default";
 281         pinctrl-0 = <&pinctrl_i2c3>;
 282         status = "okay";
 283 };
 284
 285 &i2c4 {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_i2c4>;
 288         status = "okay";
 289
 290         codec: wm8960@1a {
 291                 compatible = "wlf,wm8960";
 292                 reg = <0x1a>;
 293                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 294                 clock-names = "mclk";
 295                 wlf,shared-lrclk;
 296         };
 297 };
 298
 299 &lcdif {
 300         pinctrl-names = "default";
 301         pinctrl-0 = <&pinctrl_lcdif>;
 302         display = <&display0>;
 303         status = "okay";
 304
 305         display0: display {
 306                 bits-per-pixel = <16>;
 307                 bus-width = <24>;
 308
 309                 display-timings {
 310                         native-mode = <&timing0>;
 311
 312                         timing0: timing0 {
 313                                 clock-frequency = <9200000>;
 314                                 hactive = <480>;
 315                                 vactive = <272>;
 316                                 hfront-porch = <8>;
 317                                 hback-porch = <4>;
 318                                 hsync-len = <41>;
 319                                 vback-porch = <2>;
 320                                 vfront-porch = <4>;
 321                                 vsync-len = <10>;
 322                                 hsync-active = <0>;
 323                                 vsync-active = <0>;
 324                                 de-active = <1>;
 325                                 pixelclk-active = <0>;
 326                         };
 327                 };
 328         };
 329 };
 330
 331 &pwm1 {
 332         pinctrl-names = "default";
 333         pinctrl-0 = <&pinctrl_pwm1>;
 334         status = "okay";
 335 };
 336
 337 &uart1 {
 338         pinctrl-names = "default";
 339         pinctrl-0 = <&pinctrl_uart1>;
 340         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 341         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 342         status = "okay";
 343 };
 344
 345 &usbotg1 {
 346         vbus-supply = <&reg_usb_otg1_vbus>;
 347         status = "okay";
 348 };
 349
 350 &usbotg2 {
 351         vbus-supply = <&reg_usb_otg2_vbus>;
 352         dr_mode = "host";
 353         status = "okay";
 354 };
 355
 356 &usdhc1 {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_usdhc1>;
 359         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 360         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 361         wakeup-source;
 362         keep-power-in-suspend;
 363         status = "okay";
 364 };
 365
 366 &usdhc3 {
 367         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 368         pinctrl-0 = <&pinctrl_usdhc3>;
 369         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 370         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 371         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 372         assigned-clock-rates = <400000000>;
 373         bus-width = <8>;
 374         fsl,tuning-step = <2>;
 375         non-removable;
 376         status = "okay";
 377 };
 378
 379 &wdog1 {
 380         pinctrl-names = "default";
 381         pinctrl-0 = <&pinctrl_wdog>;
 382         fsl,ext-reset-output;
 383 };
 384
 385 &iomuxc {
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&pinctrl_hog>;
 388
 389         imx7d-sdb {
 390                 pinctrl_ecspi3: ecspi3grp {
 391                         fsl,pins = <
 392                                 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
 393                                 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
 394                                 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
 395                                 MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
 396                         >;
 397                 };
 398
 399                 pinctrl_enet1: enet1grp {
 400                         fsl,pins = <
 401                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 402                                 MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 403                                 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 404                                 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 405                                 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 406                                 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 407                                 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 408                                 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 409                                 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 410                                 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 411                                 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 412                                 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 413                                 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 414                                 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 415                         >;
 416                 };
 417
 418                 pinctrl_enet2: enet2grp {
 419                         fsl,pins = <
 420                                 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 421                                 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 422                                 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 423                                 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 424                                 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 425                                 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 426                                 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 427                                 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 428                                 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 429                                 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 430                                 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 431                                 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 432                         >;
 433                 };
 434
 435                 pinctrl_hog: hoggrp {
 436                         fsl,pins = <
 437                                 MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 438                                 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
 439                         >;
 440                 };
 441
 442                 pinctrl_i2c1: i2c1grp {
 443                         fsl,pins = <
 444                                 MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 445                                 MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 446                         >;
 447                 };
 448
 449                 pinctrl_i2c2: i2c2grp {
 450                         fsl,pins = <
 451                                 MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 452                                 MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 453                         >;
 454                 };
 455
 456                 pinctrl_i2c3: i2c3grp {
 457                         fsl,pins = <
 458                                 MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 459                                 MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 460                         >;
 461                 };
 462
 463                 pinctrl_i2c4: i2c4grp {
 464                         fsl,pins = <
 465                                 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 466                                 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 467                         >;
 468                 };
 469
 470                 pinctrl_lcdif: lcdifgrp {
 471                         fsl,pins = <
 472                                 MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 473                                 MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 474                                 MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 475                                 MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 476                                 MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 477                                 MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 478                                 MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 479                                 MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 480                                 MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 481                                 MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 482                                 MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 483                                 MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 484                                 MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 485                                 MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 486                                 MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 487                                 MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 488                                 MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 489                                 MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 490                                 MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 491                                 MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 492                                 MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 493                                 MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 494                                 MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 495                                 MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 496                                 MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 497                                 MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 498                                 MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 499                                 MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 500                                 MX7D_PAD_LCD_RESET__LCD_RESET           0x79
 501                         >;
 502                 };
 503
 504                 pinctrl_tsc2046_pendown: tsc2046_pendown {
 505                         fsl,pins = <
 506                                 MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
 507                         >;
 508                 };
 509
 510                 pinctrl_uart1: uart1grp {
 511                         fsl,pins = <
 512                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 513                                 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 514                         >;
 515                 };
 516
 517                 pinctrl_uart5: uart5grp {
 518                         fsl,pins = <
 519                                 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
 520                                 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
 521                                 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
 522                                 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
 523                         >;
 524                 };
 525
 526                 pinctrl_uart6: uart6grp {
 527                         fsl,pins = <
 528                                 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 529                                 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 530                                 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 531                                 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 532                         >;
 533                 };
 534
 535                 pinctrl_usdhc1: usdhc1grp {
 536                         fsl,pins = <
 537                                 MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 538                                 MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 539                                 MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 540                                 MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 541                                 MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 542                                 MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 543                                 MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
 544                                 MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
 545                                 MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
 546                         >;
 547                 };
 548
 549                 pinctrl_usdhc2: usdhc2grp {
 550                         fsl,pins = <
 551                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 552                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 553                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 554                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 555                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 556                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 557                                 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x59 /* WL_REG_ON */
 558                         >;
 559                 };
 560
 561                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
 562                         fsl,pins = <
 563                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
 564                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
 565                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
 566                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
 567                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
 568                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
 569                         >;
 570                 };
 571
 572                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
 573                         fsl,pins = <
 574                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
 575                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
 576                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
 577                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
 578                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
 579                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
 580                         >;
 581                 };
 582
 583
 584                 pinctrl_usdhc3: usdhc3grp {
 585                         fsl,pins = <
 586                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 587                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 588                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 589                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 590                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 591                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 592                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 593                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 594                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 595                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 596                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 597                         >;
 598                 };
 599
 600                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 601                         fsl,pins = <
 602                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 603                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 604                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 605                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 606                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 607                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 608                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 609                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 610                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 611                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 612                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 613                         >;
 614                 };
 615
 616                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 617                         fsl,pins = <
 618                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 619                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 620                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 621                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 622                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 623                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 624                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 625                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 626                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 627                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 628                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 629                         >;
 630                 };
 631         };
 632 };
 633
 634 &iomuxc_lpsr {
 635         pinctrl_wdog: wdoggrp {
 636                 fsl,pins = <
 637                         MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B          0x74
 638                 >;
 639         };
 640
 641         pinctrl_pwm1: pwm1grp {
 642                 fsl,pins = <
 643                         MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT              0x110b0
 644                 >;
 645         };
 646 };