arch/arm/boot/dts/imx7-colibri.dtsi

   1 /*
   2  * Copyright 2016 Toradex AG
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 / {
  44         bl: backlight {
  45                 compatible = "pwm-backlight";
  46                 pwms = <&pwm1 0 5000000 0>;
  47         };
  48
  49         reg_module_3v3: regulator-module-3v3 {
  50                 compatible = "regulator-fixed";
  51                 regulator-name = "+V3.3";
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54         };
  55
  56         reg_module_3v3_avdd: regulator-module-3v3-avdd {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "+V3.3_AVDD_AUDIO";
  59                 regulator-min-microvolt = <3300000>;
  60                 regulator-max-microvolt = <3300000>;
  61         };
  62
  63         sound {
  64                 compatible = "simple-audio-card";
  65                 simple-audio-card,name = "imx7-sgtl5000";
  66                 simple-audio-card,format = "i2s";
  67                 simple-audio-card,bitclock-master = <&dailink_master>;
  68                 simple-audio-card,frame-master = <&dailink_master>;
  69                 simple-audio-card,cpu {
  70                         sound-dai = <&sai1>;
  71                 };
  72
  73                 dailink_master: simple-audio-card,codec {
  74                         sound-dai = <&codec>;
  75                         clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
  76                 };
  77         };
  78 };
  79
  80 &adc1 {
  81         vref-supply = <&reg_DCDC3>;
  82 };
  83
  84 &adc2 {
  85         vref-supply = <&reg_DCDC3>;
  86 };
  87
  88 &cpu0 {
  89         arm-supply = <&reg_DCDC2>;
  90 };
  91
  92 &fec1 {
  93         pinctrl-names = "default";
  94         pinctrl-0 = <&pinctrl_enet1>;
  95         clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
  96                 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
  97                 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
  98                 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
  99         clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
 100         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 101                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 102         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 103         assigned-clock-rates = <0>, <100000000>;
 104         phy-mode = "rmii";
 105         phy-supply = <&reg_LDO1>;
 106         fsl,magic-packet;
 107 };
 108
 109 &gpmi {
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_gpmi_nand>;
 112         fsl,use-minimum-ecc;
 113         nand-on-flash-bbt;
 114         nand-ecc-mode = "hw";
 115         status = "okay";
 116 };
 117
 118 &i2c1 {
 119         clock-frequency = <100000>;
 120         pinctrl-names = "default";
 121         pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
 122         status = "okay";
 123
 124         codec: sgtl5000@a {
 125                 compatible = "fsl,sgtl5000";
 126                 #sound-dai-cells = <0>;
 127                 reg = <0x0a>;
 128                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 129                 pinctrl-names = "default";
 130                 pinctrl-0 = <&pinctrl_sai1_mclk>;
 131                 VDDA-supply = <&reg_module_3v3_avdd>;
 132                 VDDIO-supply = <&reg_module_3v3>;
 133                 VDDD-supply = <&reg_DCDC3>;
 134         };
 135
 136         ad7879@2c {
 137                 compatible = "adi,ad7879-1";
 138                 reg = <0x2c>;
 139                 interrupt-parent = <&gpio1>;
 140                 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
 141                 touchscreen-max-pressure = <4096>;
 142                 adi,resistance-plate-x = <120>;
 143                 adi,first-conversion-delay = /bits/ 8 <3>;
 144                 adi,acquisition-time = /bits/ 8 <1>;
 145                 adi,median-filter-size = /bits/ 8 <2>;
 146                 adi,averaging = /bits/ 8 <1>;
 147                 adi,conversion-interval = /bits/ 8 <255>;
 148         };
 149
 150         pmic@33 {
 151                 compatible = "ricoh,rn5t567";
 152                 reg = <0x33>;
 153
 154                 regulators {
 155                         reg_DCDC1: DCDC1 {  /* V1.0_SOC */
 156                                 regulator-min-microvolt = <1000000>;
 157                                 regulator-max-microvolt = <1100000>;
 158                                 regulator-boot-on;
 159                                 regulator-always-on;
 160                         };
 161
 162                         reg_DCDC2: DCDC2 { /* V1.1_ARM */
 163                                 regulator-min-microvolt = <975000>;
 164                                 regulator-max-microvolt = <1100000>;
 165                                 regulator-boot-on;
 166                                 regulator-always-on;
 167                         };
 168
 169                         reg_DCDC3: DCDC3 { /* V1.8 */
 170                                 regulator-min-microvolt = <1800000>;
 171                                 regulator-max-microvolt = <1800000>;
 172                                 regulator-boot-on;
 173                                 regulator-always-on;
 174                         };
 175
 176                         reg_DCDC4: DCDC4 { /* V1.35_DRAM */
 177                                 regulator-min-microvolt = <1350000>;
 178                                 regulator-max-microvolt = <1350000>;
 179                                 regulator-boot-on;
 180                                 regulator-always-on;
 181                         };
 182
 183                         reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
 184                                 regulator-min-microvolt = <1800000>;
 185                                 regulator-max-microvolt = <3300000>;
 186                                 regulator-boot-on;
 187                         };
 188
 189                         reg_LDO2: LDO2 { /* +V1.8_SD */
 190                                 regulator-min-microvolt = <1800000>;
 191                                 regulator-max-microvolt = <3300000>;
 192                                 regulator-boot-on;
 193                                 regulator-always-on;
 194                         };
 195
 196                         reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
 197                                 regulator-min-microvolt = <3300000>;
 198                                 regulator-max-microvolt = <3300000>;
 199                                 regulator-boot-on;
 200                                 regulator-always-on;
 201                         };
 202
 203                         reg_LDO4: LDO4 { /* V1.8_LPSR */
 204                                 regulator-min-microvolt = <1800000>;
 205                                 regulator-max-microvolt = <1800000>;
 206                                 regulator-boot-on;
 207                                 regulator-always-on;
 208                         };
 209
 210                         reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
 211                                 regulator-min-microvolt = <3300000>;
 212                                 regulator-max-microvolt = <3300000>;
 213                                 regulator-boot-on;
 214                                 regulator-always-on;
 215                         };
 216                 };
 217         };
 218 };
 219
 220 &i2c4 {
 221         clock-frequency = <100000>;
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_i2c4>;
 224 };
 225
 226 &lcdif {
 227         pinctrl-names = "default";
 228         pinctrl-0 = <&pinctrl_lcdif_dat
 229                      &pinctrl_lcdif_ctrl>;
 230 };
 231
 232 &pwm1 {
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_pwm1>;
 235 };
 236
 237 &pwm2 {
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&pinctrl_pwm2>;
 240 };
 241
 242 &pwm3 {
 243         pinctrl-names = "default";
 244         pinctrl-0 = <&pinctrl_pwm3>;
 245 };
 246
 247 &pwm4 {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pinctrl_pwm4>;
 250 };
 251
 252 &reg_1p0d {
 253         vin-supply = <&reg_DCDC3>;
 254 };
 255
 256 &sai1 {
 257         pinctrl-names = "default";
 258         pinctrl-0 = <&pinctrl_sai1>;
 259         status = "okay";
 260 };
 261
 262 &snvs_pwrkey {
 263         status = "disabled";
 264 };
 265
 266 &uart1 {
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
 269         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 270         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 271         uart-has-rtscts;
 272         fsl,dte-mode;
 273 };
 274
 275 &uart2 {
 276         pinctrl-names = "default";
 277         pinctrl-0 = <&pinctrl_uart2>;
 278         assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
 279         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 280         uart-has-rtscts;
 281         fsl,dte-mode;
 282 };
 283
 284 &uart3 {
 285         pinctrl-names = "default";
 286         pinctrl-0 = <&pinctrl_uart3>;
 287         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 288         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 289         fsl,dte-mode;
 290 };
 291
 292 &usbotg1 {
 293         dr_mode = "host";
 294 };
 295
 296 &usdhc1 {
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
 299         no-1-8-v;
 300         cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 301         disable-wp;
 302 };
 303
 304 &iomuxc {
 305         pinctrl-names = "default";
 306         pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
 307
 308         pinctrl_gpio1: gpio1-grp {
 309                 fsl,pins = <
 310                         MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3     0x14 /* SODIMM 55 */
 311                         MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2     0x14 /* SODIMM 63 */
 312                         MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0X14 /* SODIMM 73 */
 313                         MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16       0X14 /* SODIMM 77 */
 314                         MX7D_PAD_EPDC_DATA09__GPIO2_IO9         0x14 /* SODIMM 89 */
 315                         MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x14 /* SODIMM 91 */
 316                         MX7D_PAD_LCD_RESET__GPIO3_IO4           0x14 /* SODIMM 93 */
 317                         MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x14 /* SODIMM 95 */
 318                         MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11    0x14 /* SODIMM 99 */
 319                         MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x14 /* SODIMM 105 */
 320                         MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x14 /* SODIMM 107 */
 321                         MX7D_PAD_EPDC_DATA00__GPIO2_IO0         0x14 /* SODIMM 111 */
 322                         MX7D_PAD_EPDC_DATA01__GPIO2_IO1         0x14 /* SODIMM 113 */
 323                         MX7D_PAD_EPDC_DATA02__GPIO2_IO2         0x14 /* SODIMM 115 */
 324                         MX7D_PAD_EPDC_DATA03__GPIO2_IO3         0x14 /* SODIMM 117 */
 325                         MX7D_PAD_EPDC_DATA04__GPIO2_IO4         0x14 /* SODIMM 119 */
 326                         MX7D_PAD_EPDC_DATA05__GPIO2_IO5         0x14 /* SODIMM 121 */
 327                         MX7D_PAD_EPDC_DATA06__GPIO2_IO6         0x14 /* SODIMM 123 */
 328                         MX7D_PAD_EPDC_DATA07__GPIO2_IO7         0x14 /* SODIMM 125 */
 329                         MX7D_PAD_EPDC_SDCE2__GPIO2_IO22         0x14 /* SODIMM 127 */
 330                         MX7D_PAD_UART3_RTS_B__GPIO4_IO6         0x14 /* SODIMM 131 */
 331                         MX7D_PAD_EPDC_GDRL__GPIO2_IO26          0x14 /* SODIMM 133 */
 332                         MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17       0x14 /* SODIMM 24 */
 333                         MX7D_PAD_SD2_DATA2__GPIO5_IO16          0x14 /* SODIMM 100 */
 334                         MX7D_PAD_SD2_DATA3__GPIO5_IO17          0x14 /* SODIMM 102 */
 335                         MX7D_PAD_EPDC_GDSP__GPIO2_IO27          0x14 /* SODIMM 104 */
 336                         MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x14 /* SODIMM 106 */
 337                         MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x14 /* SODIMM 110 */
 338                         MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x14 /* SODIMM 112 */
 339                         MX7D_PAD_EPDC_SDCLK__GPIO2_IO16         0x14 /* SODIMM 114 */
 340                         MX7D_PAD_EPDC_SDLE__GPIO2_IO17          0x14 /* SODIMM 116 */
 341                         MX7D_PAD_EPDC_SDOE__GPIO2_IO18          0x14 /* SODIMM 118 */
 342                         MX7D_PAD_EPDC_SDSHR__GPIO2_IO19         0x14 /* SODIMM 120 */
 343                         MX7D_PAD_EPDC_SDCE0__GPIO2_IO20         0x14 /* SODIMM 122 */
 344                         MX7D_PAD_EPDC_SDCE1__GPIO2_IO21         0x14 /* SODIMM 124 */
 345                         MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x14 /* SODIMM 126 */
 346                         MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x14 /* SODIMM 128 */
 347                         MX7D_PAD_EPDC_SDCE3__GPIO2_IO23         0x14 /* SODIMM 130 */
 348                         MX7D_PAD_EPDC_GDCLK__GPIO2_IO24         0x14 /* SODIMM 132 */
 349                         MX7D_PAD_EPDC_GDOE__GPIO2_IO25          0x14 /* SODIMM 134 */
 350                         MX7D_PAD_EPDC_DATA12__GPIO2_IO12        0x14 /* SODIMM 150 */
 351                         MX7D_PAD_EPDC_DATA11__GPIO2_IO11        0x14 /* SODIMM 152 */
 352                         MX7D_PAD_SD2_CLK__GPIO5_IO12            0x14 /* SODIMM 184 */
 353                         MX7D_PAD_SD2_CMD__GPIO5_IO13            0x14 /* SODIMM 186 */
 354                 >;
 355         };
 356
 357         pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
 358                 fsl,pins = <
 359                         MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x14 /* SODIMM 65 */
 360                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x14 /* SODIMM 69 */
 361                         MX7D_PAD_SD1_WP__GPIO5_IO1              0x14 /* SODIMM 71 */
 362                         MX7D_PAD_I2C4_SDA__GPIO4_IO15           0x14 /* SODIMM 75 */
 363                         MX7D_PAD_ECSPI1_MISO__GPIO4_IO18        0x14 /* SODIMM 79 */
 364                         MX7D_PAD_I2C3_SCL__GPIO4_IO12           0x14 /* SODIMM 81 */
 365                         MX7D_PAD_ECSPI2_MISO__GPIO4_IO22        0x14 /* SODIMM 85 */
 366                         MX7D_PAD_ECSPI1_SS0__GPIO4_IO19         0x14 /* SODIMM 97 */
 367                         MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16        0x14 /* SODIMM 101 */
 368                         MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17        0x14 /* SODIMM 103 */
 369                         MX7D_PAD_I2C3_SDA__GPIO4_IO13           0x14 /* SODIMM 94 */
 370                         MX7D_PAD_I2C4_SCL__GPIO4_IO14           0x14 /* SODIMM 96 */
 371                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x14 /* SODIMM 98 */
 372                 >;
 373         };
 374
 375         pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
 376                 fsl,pins = <
 377                         MX7D_PAD_LCD_DATA18__GPIO3_IO23         0x14 /* SODIMM 136 */
 378                         MX7D_PAD_LCD_DATA19__GPIO3_IO24         0x14 /* SODIMM 138 */
 379                         MX7D_PAD_LCD_DATA20__GPIO3_IO25         0x14 /* SODIMM 140 */
 380                         MX7D_PAD_LCD_DATA21__GPIO3_IO26         0x14 /* SODIMM 142 */
 381                         MX7D_PAD_LCD_DATA22__GPIO3_IO27         0x14 /* SODIMM 146 */
 382                         MX7D_PAD_LCD_DATA23__GPIO3_IO28         0x14 /* SODIMM 148 */
 383                 >;
 384         };
 385
 386         pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
 387                 fsl,pins = <
 388                         MX7D_PAD_GPIO1_IO15__GPIO1_IO15         0x14 /* SODIMM 178 */
 389                         MX7D_PAD_GPIO1_IO14__GPIO1_IO14         0x14 /* SODIMM 188 */
 390                 >;
 391         };
 392
 393         pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
 394                 fsl,pins = <
 395                         MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
 396                 >;
 397         };
 398
 399         pinctrl_enet1: enet1grp {
 400                 fsl,pins = <
 401                         MX7D_PAD_ENET1_CRS__GPIO7_IO14                  0x14
 402                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
 403                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x73
 404                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x73
 405                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER           0x73
 406
 407                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
 408                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x73
 409                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x73
 410                         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1          0x73
 411                         MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x3
 412                         MX7D_PAD_SD2_WP__ENET1_MDC                      0x3
 413                 >;
 414         };
 415
 416         pinctrl_ecspi3_cs: ecspi3-cs-grp {
 417                 fsl,pins = <
 418                         MX7D_PAD_I2C2_SDA__GPIO4_IO11           0x14
 419                 >;
 420         };
 421
 422         pinctrl_ecspi3: ecspi3-grp {
 423                 fsl,pins = <
 424                         MX7D_PAD_I2C1_SCL__ECSPI3_MISO          0x2
 425                         MX7D_PAD_I2C1_SDA__ECSPI3_MOSI          0x2
 426                         MX7D_PAD_I2C2_SCL__ECSPI3_SCLK          0x2
 427                 >;
 428         };
 429
 430         pinctrl_flexcan2: flexcan2-grp {
 431                 fsl,pins = <
 432                         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
 433                         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
 434                 >;
 435         };
 436
 437         pinctrl_gpmi_nand: gpmi-nand-grp {
 438                 fsl,pins = <
 439                         MX7D_PAD_SD3_CLK__NAND_CLE              0x71
 440                         MX7D_PAD_SD3_CMD__NAND_ALE              0x71
 441                         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       0x71
 442                         MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       0x71
 443                         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     0x74
 444                         MX7D_PAD_SD3_STROBE__NAND_RE_B          0x71
 445                         MX7D_PAD_SD3_RESET_B__NAND_WE_B         0x71
 446                         MX7D_PAD_SD3_DATA0__NAND_DATA00         0x71
 447                         MX7D_PAD_SD3_DATA1__NAND_DATA01         0x71
 448                         MX7D_PAD_SD3_DATA2__NAND_DATA02         0x71
 449                         MX7D_PAD_SD3_DATA3__NAND_DATA03         0x71
 450                         MX7D_PAD_SD3_DATA4__NAND_DATA04         0x71
 451                         MX7D_PAD_SD3_DATA5__NAND_DATA05         0x71
 452                         MX7D_PAD_SD3_DATA6__NAND_DATA06         0x71
 453                         MX7D_PAD_SD3_DATA7__NAND_DATA07         0x71
 454                 >;
 455         };
 456
 457         pinctrl_i2c4: i2c4-grp {
 458                 fsl,pins = <
 459                         MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA      0x4000007f
 460                         MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL      0x4000007f
 461                 >;
 462         };
 463
 464         pinctrl_lcdif_dat: lcdif-dat-grp {
 465                 fsl,pins = <
 466                         MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 467                         MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 468                         MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 469                         MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 470                         MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 471                         MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 472                         MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 473                         MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 474                         MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 475                         MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 476                         MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 477                         MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 478                         MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 479                         MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 480                         MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 481                         MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 482                         MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 483                         MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 484                 >;
 485         };
 486
 487         pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
 488                 fsl,pins = <
 489                         MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 490                         MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 491                         MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 492                         MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 493                         MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 494                         MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 495                 >;
 496         };
 497
 498         pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
 499                 fsl,pins = <
 500                         MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 501                         MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 502                         MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 503                         MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 504                 >;
 505         };
 506
 507         pinctrl_pwm1: pwm1-grp {
 508                 fsl,pins = <
 509                         MX7D_PAD_GPIO1_IO08__PWM1_OUT           0x79
 510                 >;
 511         };
 512
 513         pinctrl_pwm2: pwm2-grp {
 514                 fsl,pins = <
 515                         MX7D_PAD_GPIO1_IO09__PWM2_OUT           0x79
 516                 >;
 517         };
 518
 519         pinctrl_pwm3: pwm3-grp {
 520                 fsl,pins = <
 521                         MX7D_PAD_GPIO1_IO10__PWM3_OUT           0x79
 522                 >;
 523         };
 524
 525         pinctrl_pwm4: pwm4-grp {
 526                 fsl,pins = <
 527                         MX7D_PAD_GPIO1_IO11__PWM4_OUT           0x79
 528                 >;
 529         };
 530
 531         pinctrl_uart1: uart1-grp {
 532                 fsl,pins = <
 533                         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX    0x79
 534                         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX    0x79
 535                         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS    0x79
 536                         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS    0x79
 537                 >;
 538         };
 539
 540         pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
 541                 fsl,pins = <
 542                         MX7D_PAD_SD2_DATA1__GPIO5_IO15          0x14 /* DCD */
 543                         MX7D_PAD_SD2_DATA0__GPIO5_IO14          0x14 /* DTR */
 544                 >;
 545         };
 546
 547         pinctrl_uart2: uart2-grp {
 548                 fsl,pins = <
 549                         MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
 550                         MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
 551                         MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
 552                         MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
 553                 >;
 554         };
 555         pinctrl_uart3: uart3-grp {
 556                 fsl,pins = <
 557                         MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
 558                         MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
 559                 >;
 560         };
 561
 562         pinctrl_usbotg2_reg: gpio-usbotg2-vbus {
 563                 fsl,pins = <
 564                         MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
 565                 >;
 566         };
 567
 568         pinctrl_usdhc1: usdhc1-grp {
 569                 fsl,pins = <
 570                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
 571                         MX7D_PAD_SD1_CLK__SD1_CLK       0x19
 572                         MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
 573                         MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
 574                         MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
 575                         MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
 576                 >;
 577         };
 578
 579         pinctrl_sai1: sai1-grp {
 580                 fsl,pins = <
 581                         MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
 582                         MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
 583                         MX7D_PAD_ENET1_COL__SAI1_TX_DATA0       0x30
 584                         MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0    0x1f
 585                 >;
 586         };
 587
 588         pinctrl_sai1_mclk: sai1grp_mclk {
 589                 fsl,pins = <
 590                         MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
 591                 >;
 592         };
 593 };
 594
 595 &iomuxc_lpsr {
 596         pinctrl-names = "default";
 597         pinctrl-0 = <&pinctrl_gpio_lpsr>;
 598
 599         pinctrl_gpio_lpsr: gpio1-grp {
 600                 fsl,pins = <
 601                         MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1     0x59
 602                         MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2     0x59
 603                         MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3     0x59
 604                 >;
 605         };
 606
 607         pinctrl_i2c1: i2c1-grp {
 608                 fsl,pins = <
 609                         MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA      0x4000007f
 610                         MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL      0x4000007f
 611                 >;
 612         };
 613
 614         pinctrl_cd_usdhc1: usdhc1-cd-grp {
 615                 fsl,pins = <
 616                         MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0     0x59 /* CD */
 617                 >;
 618         };
 619
 620         pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
 621                 fsl,pins = <
 622                         MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7     0x14 /* DSR */
 623                         MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6     0x14 /* RI */
 624                 >;
 625         };
 626 };