arch/arm/boot/dts/imx6ul.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6ul-pinfunc.h"
  14
  15 / {
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         /*
  19          * The decompressor and also some bootloaders rely on a
  20          * pre-existing /chosen node to be available to insert the
  21          * command line and merge other ATAGS info.
  22          * Also for U-Boot there must be a pre-existing /memory node.
  23          */
  24         chosen {};
  25         memory { device_type = "memory"; reg = <0 0>; };
  26
  27         aliases {
  28                 ethernet0 = &fec1;
  29                 ethernet1 = &fec2;
  30                 gpio0 = &gpio1;
  31                 gpio1 = &gpio2;
  32                 gpio2 = &gpio3;
  33                 gpio3 = &gpio4;
  34                 gpio4 = &gpio5;
  35                 i2c0 = &i2c1;
  36                 i2c1 = &i2c2;
  37                 i2c2 = &i2c3;
  38                 i2c3 = &i2c4;
  39                 mmc0 = &usdhc1;
  40                 mmc1 = &usdhc2;
  41                 serial0 = &uart1;
  42                 serial1 = &uart2;
  43                 serial2 = &uart3;
  44                 serial3 = &uart4;
  45                 serial4 = &uart5;
  46                 serial5 = &uart6;
  47                 serial6 = &uart7;
  48                 serial7 = &uart8;
  49                 sai1 = &sai1;
  50                 sai2 = &sai2;
  51                 sai3 = &sai3;
  52                 spi0 = &ecspi1;
  53                 spi1 = &ecspi2;
  54                 spi2 = &ecspi3;
  55                 spi3 = &ecspi4;
  56                 usbphy0 = &usbphy1;
  57                 usbphy1 = &usbphy2;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu0: cpu@0 {
  65                         compatible = "arm,cortex-a7";
  66                         device_type = "cpu";
  67                         reg = <0>;
  68                         clock-latency = <61036>; /* two CLK32 periods */
  69                         operating-points = <
  70                                 /* kHz  uV */
  71                                 696000  1275000
  72                                 528000  1175000
  73                                 396000  1025000
  74                                 198000  950000
  75                         >;
  76                         fsl,soc-operating-points = <
  77                                 /* KHz  uV */
  78                                 696000  1275000
  79                                 528000  1175000
  80                                 396000  1175000
  81                                 198000  1175000
  82                         >;
  83                         clocks = <&clks IMX6UL_CLK_ARM>,
  84                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  85                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  86                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  87                                  <&clks IMX6UL_CLK_STEP>,
  88                                  <&clks IMX6UL_CLK_PLL1_SW>,
  89                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  90                                  <&clks IMX6UL_PLL1_BYPASS>,
  91                                  <&clks IMX6UL_CLK_PLL1>,
  92                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  93                                  <&clks IMX6UL_CLK_OSC>;
  94                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  95                                       "secondary_sel", "step", "pll1_sw",
  96                                       "pll1_sys", "pll1_bypass", "pll1",
  97                                       "pll1_bypass_src", "osc";
  98                         arm-supply = <&reg_arm>;
  99                         soc-supply = <&reg_soc>;
 100                 };
 101         };
 102
 103         intc: interrupt-controller@a01000 {
 104                 compatible = "arm,gic-400", "arm,cortex-a7-gic";
 105                 #interrupt-cells = <3>;
 106                 interrupt-controller;
 107                 reg = <0x00a01000 0x1000>,
 108                       <0x00a02000 0x2000>,
 109                       <0x00a04000 0x2000>,
 110                       <0x00a06000 0x2000>;
 111         };
 112
 113         ckil: clock-cli {
 114                 compatible = "fixed-clock";
 115                 #clock-cells = <0>;
 116                 clock-frequency = <32768>;
 117                 clock-output-names = "ckil";
 118         };
 119
 120         osc: clock-osc {
 121                 compatible = "fixed-clock";
 122                 #clock-cells = <0>;
 123                 clock-frequency = <24000000>;
 124                 clock-output-names = "osc";
 125         };
 126
 127         ipp_di0: clock-di0 {
 128                 compatible = "fixed-clock";
 129                 #clock-cells = <0>;
 130                 clock-frequency = <0>;
 131                 clock-output-names = "ipp_di0";
 132         };
 133
 134         ipp_di1: clock-di1 {
 135                 compatible = "fixed-clock";
 136                 #clock-cells = <0>;
 137                 clock-frequency = <0>;
 138                 clock-output-names = "ipp_di1";
 139         };
 140
 141         tempmon: tempmon {
 142                 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
 143                 interrupt-parent = <&gpc>;
 144                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 145                 fsl,tempmon = <&anatop>;
 146                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 147                 nvmem-cell-names = "calib", "temp_grade";
 148                 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
 149         };
 150
 151         pmu {
 152                 compatible = "arm,cortex-a7-pmu";
 153                 interrupt-parent = <&gpc>;
 154                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 155                 status = "disabled";
 156         };
 157
 158         soc {
 159                 #address-cells = <1>;
 160                 #size-cells = <1>;
 161                 compatible = "simple-bus";
 162                 interrupt-parent = <&gpc>;
 163                 ranges;
 164
 165                 ocram: sram@900000 {
 166                         compatible = "mmio-sram";
 167                         reg = <0x00900000 0x20000>;
 168                 };
 169
 170                 dma_apbh: dma-apbh@1804000 {
 171                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 172                         reg = <0x01804000 0x2000>;
 173                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 174                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 175                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 176                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 177                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 178                         #dma-cells = <1>;
 179                         dma-channels = <4>;
 180                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 181                 };
 182
 183                 gpmi: gpmi-nand@1806000         {
 184                         compatible = "fsl,imx6q-gpmi-nand";
 185                         #address-cells = <1>;
 186                         #size-cells = <1>;
 187                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 188                         reg-names = "gpmi-nand", "bch";
 189                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 190                         interrupt-names = "bch";
 191                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 192                                  <&clks IMX6UL_CLK_GPMI_APB>,
 193                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 194                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 195                                  <&clks IMX6UL_CLK_PER_BCH>;
 196                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 197                                       "gpmi_bch_apb", "per1_bch";
 198                         dmas = <&dma_apbh 0>;
 199                         dma-names = "rx-tx";
 200                         status = "disabled";
 201                 };
 202
 203                 aips1: aips-bus@2000000 {
 204                         compatible = "fsl,aips-bus", "simple-bus";
 205                         #address-cells = <1>;
 206                         #size-cells = <1>;
 207                         reg = <0x02000000 0x100000>;
 208                         ranges;
 209
 210                         spba-bus@2000000 {
 211                                 compatible = "fsl,spba-bus", "simple-bus";
 212                                 #address-cells = <1>;
 213                                 #size-cells = <1>;
 214                                 reg = <0x02000000 0x40000>;
 215                                 ranges;
 216
 217                                 ecspi1: ecspi@2008000 {
 218                                         #address-cells = <1>;
 219                                         #size-cells = <0>;
 220                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 221                                         reg = <0x02008000 0x4000>;
 222                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 223                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 224                                                  <&clks IMX6UL_CLK_ECSPI1>;
 225                                         clock-names = "ipg", "per";
 226                                         status = "disabled";
 227                                 };
 228
 229                                 ecspi2: ecspi@200c000 {
 230                                         #address-cells = <1>;
 231                                         #size-cells = <0>;
 232                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 233                                         reg = <0x0200c000 0x4000>;
 234                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 235                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 236                                                  <&clks IMX6UL_CLK_ECSPI2>;
 237                                         clock-names = "ipg", "per";
 238                                         status = "disabled";
 239                                 };
 240
 241                                 ecspi3: ecspi@2010000 {
 242                                         #address-cells = <1>;
 243                                         #size-cells = <0>;
 244                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 245                                         reg = <0x02010000 0x4000>;
 246                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 247                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 248                                                  <&clks IMX6UL_CLK_ECSPI3>;
 249                                         clock-names = "ipg", "per";
 250                                         status = "disabled";
 251                                 };
 252
 253                                 ecspi4: ecspi@2014000 {
 254                                         #address-cells = <1>;
 255                                         #size-cells = <0>;
 256                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 257                                         reg = <0x02014000 0x4000>;
 258                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 259                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 260                                                  <&clks IMX6UL_CLK_ECSPI4>;
 261                                         clock-names = "ipg", "per";
 262                                         status = "disabled";
 263                                 };
 264
 265                                 uart7: serial@2018000 {
 266                                         compatible = "fsl,imx6ul-uart",
 267                                                      "fsl,imx6q-uart";
 268                                         reg = <0x02018000 0x4000>;
 269                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 270                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 271                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 272                                         clock-names = "ipg", "per";
 273                                         status = "disabled";
 274                                 };
 275
 276                                 uart1: serial@2020000 {
 277                                         compatible = "fsl,imx6ul-uart",
 278                                                      "fsl,imx6q-uart";
 279                                         reg = <0x02020000 0x4000>;
 280                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 281                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 282                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 283                                         clock-names = "ipg", "per";
 284                                         status = "disabled";
 285                                 };
 286
 287                                 uart8: serial@2024000 {
 288                                         compatible = "fsl,imx6ul-uart",
 289                                                      "fsl,imx6q-uart";
 290                                         reg = <0x02024000 0x4000>;
 291                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 292                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 293                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 294                                         clock-names = "ipg", "per";
 295                                         status = "disabled";
 296                                 };
 297
 298                                 sai1: sai@2028000 {
 299                                         #sound-dai-cells = <0>;
 300                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 301                                         reg = <0x02028000 0x4000>;
 302                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 303                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 304                                                  <&clks IMX6UL_CLK_SAI1>,
 305                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 306                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 307                                         dmas = <&sdma 35 24 0>,
 308                                                <&sdma 36 24 0>;
 309                                         dma-names = "rx", "tx";
 310                                         status = "disabled";
 311                                 };
 312
 313                                 sai2: sai@202c000 {
 314                                         #sound-dai-cells = <0>;
 315                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 316                                         reg = <0x0202c000 0x4000>;
 317                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 318                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 319                                                  <&clks IMX6UL_CLK_SAI2>,
 320                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 321                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 322                                         dmas = <&sdma 37 24 0>,
 323                                                <&sdma 38 24 0>;
 324                                         dma-names = "rx", "tx";
 325                                         status = "disabled";
 326                                 };
 327
 328                                 sai3: sai@2030000 {
 329                                         #sound-dai-cells = <0>;
 330                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 331                                         reg = <0x02030000 0x4000>;
 332                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 333                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 334                                                  <&clks IMX6UL_CLK_SAI3>,
 335                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 336                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 337                                         dmas = <&sdma 39 24 0>,
 338                                                <&sdma 40 24 0>;
 339                                         dma-names = "rx", "tx";
 340                                         status = "disabled";
 341                                 };
 342                         };
 343
 344                         tsc: tsc@2040000 {
 345                                 compatible = "fsl,imx6ul-tsc";
 346                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 347                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 348                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 349                                 clocks = <&clks IMX6UL_CLK_IPG>,
 350                                          <&clks IMX6UL_CLK_ADC2>;
 351                                 clock-names = "tsc", "adc";
 352                                 status = "disabled";
 353                         };
 354
 355                         pwm1: pwm@2080000 {
 356                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 357                                 reg = <0x02080000 0x4000>;
 358                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 359                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 360                                          <&clks IMX6UL_CLK_PWM1>;
 361                                 clock-names = "ipg", "per";
 362                                 #pwm-cells = <2>;
 363                                 status = "disabled";
 364                         };
 365
 366                         pwm2: pwm@2084000 {
 367                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 368                                 reg = <0x02084000 0x4000>;
 369                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 370                                 clocks = <&clks IMX6UL_CLK_PWM2>,
 371                                          <&clks IMX6UL_CLK_PWM2>;
 372                                 clock-names = "ipg", "per";
 373                                 #pwm-cells = <2>;
 374                                 status = "disabled";
 375                         };
 376
 377                         pwm3: pwm@2088000 {
 378                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 379                                 reg = <0x02088000 0x4000>;
 380                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 381                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 382                                          <&clks IMX6UL_CLK_PWM3>;
 383                                 clock-names = "ipg", "per";
 384                                 #pwm-cells = <2>;
 385                                 status = "disabled";
 386                         };
 387
 388                         pwm4: pwm@208c000 {
 389                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 390                                 reg = <0x0208c000 0x4000>;
 391                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 392                                 clocks = <&clks IMX6UL_CLK_PWM4>,
 393                                          <&clks IMX6UL_CLK_PWM4>;
 394                                 clock-names = "ipg", "per";
 395                                 #pwm-cells = <2>;
 396                                 status = "disabled";
 397                         };
 398
 399                         can1: flexcan@2090000 {
 400                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 401                                 reg = <0x02090000 0x4000>;
 402                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 403                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 404                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 405                                 clock-names = "ipg", "per";
 406                                 status = "disabled";
 407                         };
 408
 409                         can2: flexcan@2094000 {
 410                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 411                                 reg = <0x02094000 0x4000>;
 412                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 413                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 414                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 415                                 clock-names = "ipg", "per";
 416                                 status = "disabled";
 417                         };
 418
 419                         gpt1: gpt@2098000 {
 420                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 421                                 reg = <0x02098000 0x4000>;
 422                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 423                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 424                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 425                                 clock-names = "ipg", "per";
 426                         };
 427
 428                         gpio1: gpio@209c000 {
 429                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 430                                 reg = <0x0209c000 0x4000>;
 431                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 432                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 433                                 gpio-controller;
 434                                 #gpio-cells = <2>;
 435                                 interrupt-controller;
 436                                 #interrupt-cells = <2>;
 437                                 gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 438                                               <&iomuxc 16 33 16>;
 439                         };
 440
 441                         gpio2: gpio@20a0000 {
 442                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 443                                 reg = <0x020a0000 0x4000>;
 444                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 445                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 446                                 gpio-controller;
 447                                 #gpio-cells = <2>;
 448                                 interrupt-controller;
 449                                 #interrupt-cells = <2>;
 450                                 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
 451                         };
 452
 453                         gpio3: gpio@20a4000 {
 454                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 455                                 reg = <0x020a4000 0x4000>;
 456                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 457                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 458                                 gpio-controller;
 459                                 #gpio-cells = <2>;
 460                                 interrupt-controller;
 461                                 #interrupt-cells = <2>;
 462                                 gpio-ranges = <&iomuxc 0 65 29>;
 463                         };
 464
 465                         gpio4: gpio@20a8000 {
 466                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 467                                 reg = <0x020a8000 0x4000>;
 468                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 469                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 470                                 gpio-controller;
 471                                 #gpio-cells = <2>;
 472                                 interrupt-controller;
 473                                 #interrupt-cells = <2>;
 474                                 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
 475                         };
 476
 477                         gpio5: gpio@20ac000 {
 478                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 479                                 reg = <0x020ac000 0x4000>;
 480                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 481                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 482                                 gpio-controller;
 483                                 #gpio-cells = <2>;
 484                                 interrupt-controller;
 485                                 #interrupt-cells = <2>;
 486                                 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
 487                         };
 488
 489                         fec2: ethernet@20b4000 {
 490                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 491                                 reg = <0x020b4000 0x4000>;
 492                                 interrupt-names = "int0", "pps";
 493                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 494                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 495                                 clocks = <&clks IMX6UL_CLK_ENET>,
 496                                          <&clks IMX6UL_CLK_ENET_AHB>,
 497                                          <&clks IMX6UL_CLK_ENET_PTP>,
 498                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 499                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 500                                 clock-names = "ipg", "ahb", "ptp",
 501                                               "enet_clk_ref", "enet_out";
 502                                 fsl,num-tx-queues=<1>;
 503                                 fsl,num-rx-queues=<1>;
 504                                 status = "disabled";
 505                         };
 506
 507                         kpp: kpp@20b8000 {
 508                                 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
 509                                 reg = <0x020b8000 0x4000>;
 510                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 511                                 clocks = <&clks IMX6UL_CLK_KPP>;
 512                                 status = "disabled";
 513                         };
 514
 515                         wdog1: wdog@20bc000 {
 516                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 517                                 reg = <0x020bc000 0x4000>;
 518                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 519                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 520                         };
 521
 522                         wdog2: wdog@20c0000 {
 523                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 524                                 reg = <0x020c0000 0x4000>;
 525                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 526                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 527                                 status = "disabled";
 528                         };
 529
 530                         clks: ccm@20c4000 {
 531                                 compatible = "fsl,imx6ul-ccm";
 532                                 reg = <0x020c4000 0x4000>;
 533                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 534                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 535                                 #clock-cells = <1>;
 536                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 537                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 538                         };
 539
 540                         anatop: anatop@20c8000 {
 541                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 542                                              "syscon", "simple-bus";
 543                                 reg = <0x020c8000 0x1000>;
 544                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 545                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 546                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 547                                 #address-cells = <1>;
 548                                 #size-cells = <0>;
 549
 550                                 reg_3p0: regulator-3p0@20c8110 {
 551                                         reg = <0x20c8110>;
 552                                         compatible = "fsl,anatop-regulator";
 553                                         regulator-name = "vdd3p0";
 554                                         regulator-min-microvolt = <2625000>;
 555                                         regulator-max-microvolt = <3400000>;
 556                                         anatop-reg-offset = <0x120>;
 557                                         anatop-vol-bit-shift = <8>;
 558                                         anatop-vol-bit-width = <5>;
 559                                         anatop-min-bit-val = <0>;
 560                                         anatop-min-voltage = <2625000>;
 561                                         anatop-max-voltage = <3400000>;
 562                                         anatop-enable-bit = <0>;
 563                                 };
 564
 565                                 reg_arm: regulator-vddcore@20c8140 {
 566                                         reg = <0x20c8140>;
 567                                         compatible = "fsl,anatop-regulator";
 568                                         regulator-name = "cpu";
 569                                         regulator-min-microvolt = <725000>;
 570                                         regulator-max-microvolt = <1450000>;
 571                                         regulator-always-on;
 572                                         anatop-reg-offset = <0x140>;
 573                                         anatop-vol-bit-shift = <0>;
 574                                         anatop-vol-bit-width = <5>;
 575                                         anatop-delay-reg-offset = <0x170>;
 576                                         anatop-delay-bit-shift = <24>;
 577                                         anatop-delay-bit-width = <2>;
 578                                         anatop-min-bit-val = <1>;
 579                                         anatop-min-voltage = <725000>;
 580                                         anatop-max-voltage = <1450000>;
 581                                 };
 582
 583                                 reg_soc: regulator-vddsoc@20c8140 {
 584                                         reg = <0x20c8140>;
 585                                         compatible = "fsl,anatop-regulator";
 586                                         regulator-name = "vddsoc";
 587                                         regulator-min-microvolt = <725000>;
 588                                         regulator-max-microvolt = <1450000>;
 589                                         regulator-always-on;
 590                                         anatop-reg-offset = <0x140>;
 591                                         anatop-vol-bit-shift = <18>;
 592                                         anatop-vol-bit-width = <5>;
 593                                         anatop-delay-reg-offset = <0x170>;
 594                                         anatop-delay-bit-shift = <28>;
 595                                         anatop-delay-bit-width = <2>;
 596                                         anatop-min-bit-val = <1>;
 597                                         anatop-min-voltage = <725000>;
 598                                         anatop-max-voltage = <1450000>;
 599                                 };
 600                         };
 601
 602                         usbphy1: usbphy@20c9000 {
 603                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 604                                 reg = <0x020c9000 0x1000>;
 605                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 606                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 607                                 phy-3p0-supply = <&reg_3p0>;
 608                                 fsl,anatop = <&anatop>;
 609                         };
 610
 611                         usbphy2: usbphy@20ca000 {
 612                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 613                                 reg = <0x020ca000 0x1000>;
 614                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 615                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 616                                 phy-3p0-supply = <&reg_3p0>;
 617                                 fsl,anatop = <&anatop>;
 618                         };
 619
 620                         snvs: snvs@20cc000 {
 621                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 622                                 reg = <0x020cc000 0x4000>;
 623
 624                                 snvs_rtc: snvs-rtc-lp {
 625                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 626                                         regmap = <&snvs>;
 627                                         offset = <0x34>;
 628                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 629                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 630                                 };
 631
 632                                 snvs_poweroff: snvs-poweroff {
 633                                         compatible = "syscon-poweroff";
 634                                         regmap = <&snvs>;
 635                                         offset = <0x38>;
 636                                         value = <0x60>;
 637                                         mask = <0x60>;
 638                                         status = "disabled";
 639                                 };
 640
 641                                 snvs_pwrkey: snvs-powerkey {
 642                                         compatible = "fsl,sec-v4.0-pwrkey";
 643                                         regmap = <&snvs>;
 644                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 645                                         linux,keycode = <KEY_POWER>;
 646                                         wakeup-source;
 647                                 };
 648
 649                                 snvs_lpgpr: snvs-lpgpr {
 650                                         compatible = "fsl,imx6ul-snvs-lpgpr";
 651                                 };
 652                         };
 653
 654                         epit1: epit@20d0000 {
 655                                 reg = <0x020d0000 0x4000>;
 656                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 657                         };
 658
 659                         epit2: epit@20d4000 {
 660                                 reg = <0x020d4000 0x4000>;
 661                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 662                         };
 663
 664                         src: src@20d8000 {
 665                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 666                                 reg = <0x020d8000 0x4000>;
 667                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 668                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 669                                 #reset-cells = <1>;
 670                         };
 671
 672                         gpc: gpc@20dc000 {
 673                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 674                                 reg = <0x020dc000 0x4000>;
 675                                 interrupt-controller;
 676                                 #interrupt-cells = <3>;
 677                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 678                                 interrupt-parent = <&intc>;
 679                         };
 680
 681                         iomuxc: iomuxc@20e0000 {
 682                                 compatible = "fsl,imx6ul-iomuxc";
 683                                 reg = <0x020e0000 0x4000>;
 684                         };
 685
 686                         gpr: iomuxc-gpr@20e4000 {
 687                                 compatible = "fsl,imx6ul-iomuxc-gpr",
 688                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 689                                 reg = <0x020e4000 0x4000>;
 690                         };
 691
 692                         gpt2: gpt@20e8000 {
 693                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 694                                 reg = <0x020e8000 0x4000>;
 695                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 696                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 697                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 698                                 clock-names = "ipg", "per";
 699                         };
 700
 701                         sdma: sdma@20ec000 {
 702                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
 703                                              "fsl,imx35-sdma";
 704                                 reg = <0x020ec000 0x4000>;
 705                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 706                                 clocks = <&clks IMX6UL_CLK_SDMA>,
 707                                          <&clks IMX6UL_CLK_SDMA>;
 708                                 clock-names = "ipg", "ahb";
 709                                 #dma-cells = <3>;
 710                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 711                         };
 712
 713                         pwm5: pwm@20f0000 {
 714                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 715                                 reg = <0x020f0000 0x4000>;
 716                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 717                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 718                                          <&clks IMX6UL_CLK_PWM5>;
 719                                 clock-names = "ipg", "per";
 720                                 #pwm-cells = <2>;
 721                                 status = "disabled";
 722                         };
 723
 724                         pwm6: pwm@20f4000 {
 725                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 726                                 reg = <0x020f4000 0x4000>;
 727                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 728                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 729                                          <&clks IMX6UL_CLK_PWM6>;
 730                                 clock-names = "ipg", "per";
 731                                 #pwm-cells = <2>;
 732                                 status = "disabled";
 733                         };
 734
 735                         pwm7: pwm@20f8000 {
 736                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 737                                 reg = <0x020f8000 0x4000>;
 738                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 739                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 740                                          <&clks IMX6UL_CLK_PWM7>;
 741                                 clock-names = "ipg", "per";
 742                                 #pwm-cells = <2>;
 743                                 status = "disabled";
 744                         };
 745
 746                         pwm8: pwm@20fc000 {
 747                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 748                                 reg = <0x020fc000 0x4000>;
 749                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 750                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 751                                          <&clks IMX6UL_CLK_PWM8>;
 752                                 clock-names = "ipg", "per";
 753                                 #pwm-cells = <2>;
 754                                 status = "disabled";
 755                         };
 756                 };
 757
 758                 aips2: aips-bus@2100000 {
 759                         compatible = "fsl,aips-bus", "simple-bus";
 760                         #address-cells = <1>;
 761                         #size-cells = <1>;
 762                         reg = <0x02100000 0x100000>;
 763                         ranges;
 764
 765                         usbotg1: usb@2184000 {
 766                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 767                                 reg = <0x02184000 0x200>;
 768                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 769                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 770                                 fsl,usbphy = <&usbphy1>;
 771                                 fsl,usbmisc = <&usbmisc 0>;
 772                                 fsl,anatop = <&anatop>;
 773                                 ahb-burst-config = <0x0>;
 774                                 tx-burst-size-dword = <0x10>;
 775                                 rx-burst-size-dword = <0x10>;
 776                                 status = "disabled";
 777                         };
 778
 779                         usbotg2: usb@2184200 {
 780                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 781                                 reg = <0x02184200 0x200>;
 782                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 783                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 784                                 fsl,usbphy = <&usbphy2>;
 785                                 fsl,usbmisc = <&usbmisc 1>;
 786                                 ahb-burst-config = <0x0>;
 787                                 tx-burst-size-dword = <0x10>;
 788                                 rx-burst-size-dword = <0x10>;
 789                                 status = "disabled";
 790                         };
 791
 792                         usbmisc: usbmisc@2184800 {
 793                                 #index-cells = <1>;
 794                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 795                                 reg = <0x02184800 0x200>;
 796                         };
 797
 798                         fec1: ethernet@2188000 {
 799                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 800                                 reg = <0x02188000 0x4000>;
 801                                 interrupt-names = "int0", "pps";
 802                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 803                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 804                                 clocks = <&clks IMX6UL_CLK_ENET>,
 805                                          <&clks IMX6UL_CLK_ENET_AHB>,
 806                                          <&clks IMX6UL_CLK_ENET_PTP>,
 807                                          <&clks IMX6UL_CLK_ENET_REF>,
 808                                          <&clks IMX6UL_CLK_ENET_REF>;
 809                                 clock-names = "ipg", "ahb", "ptp",
 810                                               "enet_clk_ref", "enet_out";
 811                                 fsl,num-tx-queues=<1>;
 812                                 fsl,num-rx-queues=<1>;
 813                                 status = "disabled";
 814                         };
 815
 816                         usdhc1: usdhc@2190000 {
 817                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 818                                 reg = <0x02190000 0x4000>;
 819                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 820                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 821                                          <&clks IMX6UL_CLK_USDHC1>,
 822                                          <&clks IMX6UL_CLK_USDHC1>;
 823                                 clock-names = "ipg", "ahb", "per";
 824                                 bus-width = <4>;
 825                                 status = "disabled";
 826                         };
 827
 828                         usdhc2: usdhc@2194000 {
 829                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 830                                 reg = <0x02194000 0x4000>;
 831                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 832                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 833                                          <&clks IMX6UL_CLK_USDHC2>,
 834                                          <&clks IMX6UL_CLK_USDHC2>;
 835                                 clock-names = "ipg", "ahb", "per";
 836                                 bus-width = <4>;
 837                                 status = "disabled";
 838                         };
 839
 840                         adc1: adc@2198000 {
 841                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 842                                 reg = <0x02198000 0x4000>;
 843                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 844                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 845                                 num-channels = <2>;
 846                                 clock-names = "adc";
 847                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 848                                                          <20000000>;
 849                                 status = "disabled";
 850                         };
 851
 852                         i2c1: i2c@21a0000 {
 853                                 #address-cells = <1>;
 854                                 #size-cells = <0>;
 855                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 856                                 reg = <0x021a0000 0x4000>;
 857                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 858                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 859                                 status = "disabled";
 860                         };
 861
 862                         i2c2: i2c@21a4000 {
 863                                 #address-cells = <1>;
 864                                 #size-cells = <0>;
 865                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 866                                 reg = <0x021a4000 0x4000>;
 867                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 868                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 869                                 status = "disabled";
 870                         };
 871
 872                         i2c3: i2c@21a8000 {
 873                                 #address-cells = <1>;
 874                                 #size-cells = <0>;
 875                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 876                                 reg = <0x021a8000 0x4000>;
 877                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 878                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 879                                 status = "disabled";
 880                         };
 881
 882                         mmdc: mmdc@21b0000 {
 883                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 884                                 reg = <0x021b0000 0x4000>;
 885                         };
 886
 887                         ocotp: ocotp-ctrl@21bc000 {
 888                                 #address-cells = <1>;
 889                                 #size-cells = <1>;
 890                                 compatible = "fsl,imx6ul-ocotp", "syscon";
 891                                 reg = <0x021bc000 0x4000>;
 892                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
 893
 894                                 tempmon_calib: calib@38 {
 895                                         reg = <0x38 4>;
 896                                 };
 897
 898                                 tempmon_temp_grade: temp-grade@20 {
 899                                         reg = <0x20 4>;
 900                                 };
 901                         };
 902
 903                         lcdif: lcdif@21c8000 {
 904                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 905                                 reg = <0x021c8000 0x4000>;
 906                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 907                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 908                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 909                                          <&clks IMX6UL_CLK_DUMMY>;
 910                                 clock-names = "pix", "axi", "disp_axi";
 911                                 status = "disabled";
 912                         };
 913
 914                         qspi: qspi@21e0000 {
 915                                 #address-cells = <1>;
 916                                 #size-cells = <0>;
 917                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 918                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 919                                 reg-names = "QuadSPI", "QuadSPI-memory";
 920                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 921                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 922                                          <&clks IMX6UL_CLK_QSPI>;
 923                                 clock-names = "qspi_en", "qspi";
 924                                 status = "disabled";
 925                         };
 926
 927                         uart2: serial@21e8000 {
 928                                 compatible = "fsl,imx6ul-uart",
 929                                              "fsl,imx6q-uart";
 930                                 reg = <0x021e8000 0x4000>;
 931                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 932                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 933                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 934                                 clock-names = "ipg", "per";
 935                                 status = "disabled";
 936                         };
 937
 938                         uart3: serial@21ec000 {
 939                                 compatible = "fsl,imx6ul-uart",
 940                                              "fsl,imx6q-uart";
 941                                 reg = <0x021ec000 0x4000>;
 942                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 943                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 944                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 945                                 clock-names = "ipg", "per";
 946                                 status = "disabled";
 947                         };
 948
 949                         uart4: serial@21f0000 {
 950                                 compatible = "fsl,imx6ul-uart",
 951                                              "fsl,imx6q-uart";
 952                                 reg = <0x021f0000 0x4000>;
 953                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 954                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 955                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 956                                 clock-names = "ipg", "per";
 957                                 status = "disabled";
 958                         };
 959
 960                         uart5: serial@21f4000 {
 961                                 compatible = "fsl,imx6ul-uart",
 962                                              "fsl,imx6q-uart";
 963                                 reg = <0x021f4000 0x4000>;
 964                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 965                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
 966                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
 967                                 clock-names = "ipg", "per";
 968                                 status = "disabled";
 969                         };
 970
 971                         i2c4: i2c@21f8000 {
 972                                 #address-cells = <1>;
 973                                 #size-cells = <0>;
 974                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 975                                 reg = <0x021f8000 0x4000>;
 976                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 977                                 clocks = <&clks IMX6UL_CLK_I2C4>;
 978                                 status = "disabled";
 979                         };
 980
 981                         uart6: serial@21fc000 {
 982                                 compatible = "fsl,imx6ul-uart",
 983                                              "fsl,imx6q-uart";
 984                                 reg = <0x021fc000 0x4000>;
 985                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 986                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
 987                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
 988                                 clock-names = "ipg", "per";
 989                                 status = "disabled";
 990                         };
 991                 };
 992         };
 993 };