arch/arm/boot/dts/imx6ul.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/clock/imx6ul-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include "imx6ul-pinfunc.h"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         /*
  15          * The decompressor and also some bootloaders rely on a
  16          * pre-existing /chosen node to be available to insert the
  17          * command line and merge other ATAGS info.
  18          * Also for U-Boot there must be a pre-existing /memory node.
  19          */
  20         chosen {};
  21         memory { device_type = "memory"; };
  22
  23         aliases {
  24                 ethernet0 = &fec1;
  25                 ethernet1 = &fec2;
  26                 gpio0 = &gpio1;
  27                 gpio1 = &gpio2;
  28                 gpio2 = &gpio3;
  29                 gpio3 = &gpio4;
  30                 gpio4 = &gpio5;
  31                 i2c0 = &i2c1;
  32                 i2c1 = &i2c2;
  33                 i2c2 = &i2c3;
  34                 i2c3 = &i2c4;
  35                 mmc0 = &usdhc1;
  36                 mmc1 = &usdhc2;
  37                 serial0 = &uart1;
  38                 serial1 = &uart2;
  39                 serial2 = &uart3;
  40                 serial3 = &uart4;
  41                 serial4 = &uart5;
  42                 serial5 = &uart6;
  43                 serial6 = &uart7;
  44                 serial7 = &uart8;
  45                 sai1 = &sai1;
  46                 sai2 = &sai2;
  47                 sai3 = &sai3;
  48                 spi0 = &ecspi1;
  49                 spi1 = &ecspi2;
  50                 spi2 = &ecspi3;
  51                 spi3 = &ecspi4;
  52                 usbphy0 = &usbphy1;
  53                 usbphy1 = &usbphy2;
  54         };
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu0: cpu@0 {
  61                         compatible = "arm,cortex-a7";
  62                         device_type = "cpu";
  63                         reg = <0>;
  64                         clock-latency = <61036>; /* two CLK32 periods */
  65                         operating-points = <
  66                                 /* kHz  uV */
  67                                 696000  1275000
  68                                 528000  1175000
  69                                 396000  1025000
  70                                 198000  950000
  71                         >;
  72                         fsl,soc-operating-points = <
  73                                 /* KHz  uV */
  74                                 696000  1275000
  75                                 528000  1175000
  76                                 396000  1175000
  77                                 198000  1175000
  78                         >;
  79                         clocks = <&clks IMX6UL_CLK_ARM>,
  80                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  81                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  82                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  83                                  <&clks IMX6UL_CLK_STEP>,
  84                                  <&clks IMX6UL_CLK_PLL1_SW>,
  85                                  <&clks IMX6UL_CLK_PLL1_SYS>;
  86                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  87                                       "secondary_sel", "step", "pll1_sw",
  88                                       "pll1_sys";
  89                         arm-supply = <&reg_arm>;
  90                         soc-supply = <&reg_soc>;
  91                 };
  92         };
  93
  94         intc: interrupt-controller@a01000 {
  95                 compatible = "arm,gic-400", "arm,cortex-a7-gic";
  96                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  97                 #interrupt-cells = <3>;
  98                 interrupt-controller;
  99                 interrupt-parent = <&intc>;
 100                 reg = <0x00a01000 0x1000>,
 101                       <0x00a02000 0x2000>,
 102                       <0x00a04000 0x2000>,
 103                       <0x00a06000 0x2000>;
 104         };
 105
 106         timer {
 107                 compatible = "arm,armv7-timer";
 108                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 109                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 110                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 111                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 112                 interrupt-parent = <&intc>;
 113                 status = "disabled";
 114         };
 115
 116         ckil: clock-cli {
 117                 compatible = "fixed-clock";
 118                 #clock-cells = <0>;
 119                 clock-frequency = <32768>;
 120                 clock-output-names = "ckil";
 121         };
 122
 123         osc: clock-osc {
 124                 compatible = "fixed-clock";
 125                 #clock-cells = <0>;
 126                 clock-frequency = <24000000>;
 127                 clock-output-names = "osc";
 128         };
 129
 130         ipp_di0: clock-di0 {
 131                 compatible = "fixed-clock";
 132                 #clock-cells = <0>;
 133                 clock-frequency = <0>;
 134                 clock-output-names = "ipp_di0";
 135         };
 136
 137         ipp_di1: clock-di1 {
 138                 compatible = "fixed-clock";
 139                 #clock-cells = <0>;
 140                 clock-frequency = <0>;
 141                 clock-output-names = "ipp_di1";
 142         };
 143
 144         tempmon: tempmon {
 145                 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
 146                 interrupt-parent = <&gpc>;
 147                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 148                 fsl,tempmon = <&anatop>;
 149                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 150                 nvmem-cell-names = "calib", "temp_grade";
 151                 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
 152         };
 153
 154         pmu {
 155                 compatible = "arm,cortex-a7-pmu";
 156                 interrupt-parent = <&gpc>;
 157                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 158                 status = "disabled";
 159         };
 160
 161         soc {
 162                 #address-cells = <1>;
 163                 #size-cells = <1>;
 164                 compatible = "simple-bus";
 165                 interrupt-parent = <&gpc>;
 166                 ranges;
 167
 168                 ocram: sram@900000 {
 169                         compatible = "mmio-sram";
 170                         reg = <0x00900000 0x20000>;
 171                 };
 172
 173                 dma_apbh: dma-apbh@1804000 {
 174                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 175                         reg = <0x01804000 0x2000>;
 176                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 177                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 178                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 180                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 181                         #dma-cells = <1>;
 182                         dma-channels = <4>;
 183                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 184                 };
 185
 186                 gpmi: gpmi-nand@1806000         {
 187                         compatible = "fsl,imx6q-gpmi-nand";
 188                         #address-cells = <1>;
 189                         #size-cells = <1>;
 190                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 191                         reg-names = "gpmi-nand", "bch";
 192                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 193                         interrupt-names = "bch";
 194                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 195                                  <&clks IMX6UL_CLK_GPMI_APB>,
 196                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 197                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 198                                  <&clks IMX6UL_CLK_PER_BCH>;
 199                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 200                                       "gpmi_bch_apb", "per1_bch";
 201                         dmas = <&dma_apbh 0>;
 202                         dma-names = "rx-tx";
 203                         status = "disabled";
 204                 };
 205
 206                 aips1: aips-bus@2000000 {
 207                         compatible = "fsl,aips-bus", "simple-bus";
 208                         #address-cells = <1>;
 209                         #size-cells = <1>;
 210                         reg = <0x02000000 0x100000>;
 211                         ranges;
 212
 213                         spba-bus@2000000 {
 214                                 compatible = "fsl,spba-bus", "simple-bus";
 215                                 #address-cells = <1>;
 216                                 #size-cells = <1>;
 217                                 reg = <0x02000000 0x40000>;
 218                                 ranges;
 219
 220                                 ecspi1: ecspi@2008000 {
 221                                         #address-cells = <1>;
 222                                         #size-cells = <0>;
 223                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 224                                         reg = <0x02008000 0x4000>;
 225                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 226                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 227                                                  <&clks IMX6UL_CLK_ECSPI1>;
 228                                         clock-names = "ipg", "per";
 229                                         status = "disabled";
 230                                 };
 231
 232                                 ecspi2: ecspi@200c000 {
 233                                         #address-cells = <1>;
 234                                         #size-cells = <0>;
 235                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 236                                         reg = <0x0200c000 0x4000>;
 237                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 238                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 239                                                  <&clks IMX6UL_CLK_ECSPI2>;
 240                                         clock-names = "ipg", "per";
 241                                         status = "disabled";
 242                                 };
 243
 244                                 ecspi3: ecspi@2010000 {
 245                                         #address-cells = <1>;
 246                                         #size-cells = <0>;
 247                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 248                                         reg = <0x02010000 0x4000>;
 249                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 250                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 251                                                  <&clks IMX6UL_CLK_ECSPI3>;
 252                                         clock-names = "ipg", "per";
 253                                         status = "disabled";
 254                                 };
 255
 256                                 ecspi4: ecspi@2014000 {
 257                                         #address-cells = <1>;
 258                                         #size-cells = <0>;
 259                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 260                                         reg = <0x02014000 0x4000>;
 261                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 262                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 263                                                  <&clks IMX6UL_CLK_ECSPI4>;
 264                                         clock-names = "ipg", "per";
 265                                         status = "disabled";
 266                                 };
 267
 268                                 uart7: serial@2018000 {
 269                                         compatible = "fsl,imx6ul-uart",
 270                                                      "fsl,imx6q-uart";
 271                                         reg = <0x02018000 0x4000>;
 272                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 273                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 274                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 275                                         clock-names = "ipg", "per";
 276                                         status = "disabled";
 277                                 };
 278
 279                                 uart1: serial@2020000 {
 280                                         compatible = "fsl,imx6ul-uart",
 281                                                      "fsl,imx6q-uart";
 282                                         reg = <0x02020000 0x4000>;
 283                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 284                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 285                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 286                                         clock-names = "ipg", "per";
 287                                         status = "disabled";
 288                                 };
 289
 290                                 uart8: serial@2024000 {
 291                                         compatible = "fsl,imx6ul-uart",
 292                                                      "fsl,imx6q-uart";
 293                                         reg = <0x02024000 0x4000>;
 294                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 295                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 296                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 297                                         clock-names = "ipg", "per";
 298                                         status = "disabled";
 299                                 };
 300
 301                                 sai1: sai@2028000 {
 302                                         #sound-dai-cells = <0>;
 303                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 304                                         reg = <0x02028000 0x4000>;
 305                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 306                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 307                                                  <&clks IMX6UL_CLK_SAI1>,
 308                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 309                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 310                                         dmas = <&sdma 35 24 0>,
 311                                                <&sdma 36 24 0>;
 312                                         dma-names = "rx", "tx";
 313                                         status = "disabled";
 314                                 };
 315
 316                                 sai2: sai@202c000 {
 317                                         #sound-dai-cells = <0>;
 318                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 319                                         reg = <0x0202c000 0x4000>;
 320                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 321                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 322                                                  <&clks IMX6UL_CLK_SAI2>,
 323                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 324                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 325                                         dmas = <&sdma 37 24 0>,
 326                                                <&sdma 38 24 0>;
 327                                         dma-names = "rx", "tx";
 328                                         status = "disabled";
 329                                 };
 330
 331                                 sai3: sai@2030000 {
 332                                         #sound-dai-cells = <0>;
 333                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 334                                         reg = <0x02030000 0x4000>;
 335                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 336                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 337                                                  <&clks IMX6UL_CLK_SAI3>,
 338                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 339                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 340                                         dmas = <&sdma 39 24 0>,
 341                                                <&sdma 40 24 0>;
 342                                         dma-names = "rx", "tx";
 343                                         status = "disabled";
 344                                 };
 345                         };
 346
 347                         tsc: tsc@2040000 {
 348                                 compatible = "fsl,imx6ul-tsc";
 349                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 350                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 351                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 352                                 clocks = <&clks IMX6UL_CLK_IPG>,
 353                                          <&clks IMX6UL_CLK_ADC2>;
 354                                 clock-names = "tsc", "adc";
 355                                 status = "disabled";
 356                         };
 357
 358                         pwm1: pwm@2080000 {
 359                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 360                                 reg = <0x02080000 0x4000>;
 361                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 362                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 363                                          <&clks IMX6UL_CLK_PWM1>;
 364                                 clock-names = "ipg", "per";
 365                                 #pwm-cells = <2>;
 366                                 status = "disabled";
 367                         };
 368
 369                         pwm2: pwm@2084000 {
 370                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 371                                 reg = <0x02084000 0x4000>;
 372                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 373                                 clocks = <&clks IMX6UL_CLK_PWM2>,
 374                                          <&clks IMX6UL_CLK_PWM2>;
 375                                 clock-names = "ipg", "per";
 376                                 #pwm-cells = <2>;
 377                                 status = "disabled";
 378                         };
 379
 380                         pwm3: pwm@2088000 {
 381                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 382                                 reg = <0x02088000 0x4000>;
 383                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 384                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 385                                          <&clks IMX6UL_CLK_PWM3>;
 386                                 clock-names = "ipg", "per";
 387                                 #pwm-cells = <2>;
 388                                 status = "disabled";
 389                         };
 390
 391                         pwm4: pwm@208c000 {
 392                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 393                                 reg = <0x0208c000 0x4000>;
 394                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 395                                 clocks = <&clks IMX6UL_CLK_PWM4>,
 396                                          <&clks IMX6UL_CLK_PWM4>;
 397                                 clock-names = "ipg", "per";
 398                                 #pwm-cells = <2>;
 399                                 status = "disabled";
 400                         };
 401
 402                         can1: flexcan@2090000 {
 403                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 404                                 reg = <0x02090000 0x4000>;
 405                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 406                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 407                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 408                                 clock-names = "ipg", "per";
 409                                 status = "disabled";
 410                         };
 411
 412                         can2: flexcan@2094000 {
 413                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 414                                 reg = <0x02094000 0x4000>;
 415                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 416                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 417                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 418                                 clock-names = "ipg", "per";
 419                                 status = "disabled";
 420                         };
 421
 422                         gpt1: gpt@2098000 {
 423                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 424                                 reg = <0x02098000 0x4000>;
 425                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 426                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 427                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 428                                 clock-names = "ipg", "per";
 429                         };
 430
 431                         gpio1: gpio@209c000 {
 432                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 433                                 reg = <0x0209c000 0x4000>;
 434                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 435                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 436                                 gpio-controller;
 437                                 #gpio-cells = <2>;
 438                                 interrupt-controller;
 439                                 #interrupt-cells = <2>;
 440                                 gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 441                                               <&iomuxc 16 33 16>;
 442                         };
 443
 444                         gpio2: gpio@20a0000 {
 445                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 446                                 reg = <0x020a0000 0x4000>;
 447                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 448                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 449                                 gpio-controller;
 450                                 #gpio-cells = <2>;
 451                                 interrupt-controller;
 452                                 #interrupt-cells = <2>;
 453                                 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
 454                         };
 455
 456                         gpio3: gpio@20a4000 {
 457                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 458                                 reg = <0x020a4000 0x4000>;
 459                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 460                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 461                                 gpio-controller;
 462                                 #gpio-cells = <2>;
 463                                 interrupt-controller;
 464                                 #interrupt-cells = <2>;
 465                                 gpio-ranges = <&iomuxc 0 65 29>;
 466                         };
 467
 468                         gpio4: gpio@20a8000 {
 469                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 470                                 reg = <0x020a8000 0x4000>;
 471                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 472                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 473                                 gpio-controller;
 474                                 #gpio-cells = <2>;
 475                                 interrupt-controller;
 476                                 #interrupt-cells = <2>;
 477                                 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
 478                         };
 479
 480                         gpio5: gpio@20ac000 {
 481                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 482                                 reg = <0x020ac000 0x4000>;
 483                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 484                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 485                                 gpio-controller;
 486                                 #gpio-cells = <2>;
 487                                 interrupt-controller;
 488                                 #interrupt-cells = <2>;
 489                                 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
 490                         };
 491
 492                         fec2: ethernet@20b4000 {
 493                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 494                                 reg = <0x020b4000 0x4000>;
 495                                 interrupt-names = "int0", "pps";
 496                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 497                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 498                                 clocks = <&clks IMX6UL_CLK_ENET>,
 499                                          <&clks IMX6UL_CLK_ENET_AHB>,
 500                                          <&clks IMX6UL_CLK_ENET_PTP>,
 501                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 502                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 503                                 clock-names = "ipg", "ahb", "ptp",
 504                                               "enet_clk_ref", "enet_out";
 505                                 fsl,num-tx-queues=<1>;
 506                                 fsl,num-rx-queues=<1>;
 507                                 status = "disabled";
 508                         };
 509
 510                         kpp: kpp@20b8000 {
 511                                 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
 512                                 reg = <0x020b8000 0x4000>;
 513                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 514                                 clocks = <&clks IMX6UL_CLK_KPP>;
 515                                 status = "disabled";
 516                         };
 517
 518                         wdog1: wdog@20bc000 {
 519                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 520                                 reg = <0x020bc000 0x4000>;
 521                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 522                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 523                         };
 524
 525                         wdog2: wdog@20c0000 {
 526                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 527                                 reg = <0x020c0000 0x4000>;
 528                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 529                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 530                                 status = "disabled";
 531                         };
 532
 533                         clks: ccm@20c4000 {
 534                                 compatible = "fsl,imx6ul-ccm";
 535                                 reg = <0x020c4000 0x4000>;
 536                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 537                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 538                                 #clock-cells = <1>;
 539                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 540                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 541                         };
 542
 543                         anatop: anatop@20c8000 {
 544                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 545                                              "syscon", "simple-bus";
 546                                 reg = <0x020c8000 0x1000>;
 547                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 548                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 549                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 550
 551                                 reg_3p0: regulator-3p0 {
 552                                         compatible = "fsl,anatop-regulator";
 553                                         regulator-name = "vdd3p0";
 554                                         regulator-min-microvolt = <2625000>;
 555                                         regulator-max-microvolt = <3400000>;
 556                                         anatop-reg-offset = <0x120>;
 557                                         anatop-vol-bit-shift = <8>;
 558                                         anatop-vol-bit-width = <5>;
 559                                         anatop-min-bit-val = <0>;
 560                                         anatop-min-voltage = <2625000>;
 561                                         anatop-max-voltage = <3400000>;
 562                                         anatop-enable-bit = <0>;
 563                                 };
 564
 565                                 reg_arm: regulator-vddcore {
 566                                         compatible = "fsl,anatop-regulator";
 567                                         regulator-name = "cpu";
 568                                         regulator-min-microvolt = <725000>;
 569                                         regulator-max-microvolt = <1450000>;
 570                                         regulator-always-on;
 571                                         anatop-reg-offset = <0x140>;
 572                                         anatop-vol-bit-shift = <0>;
 573                                         anatop-vol-bit-width = <5>;
 574                                         anatop-delay-reg-offset = <0x170>;
 575                                         anatop-delay-bit-shift = <24>;
 576                                         anatop-delay-bit-width = <2>;
 577                                         anatop-min-bit-val = <1>;
 578                                         anatop-min-voltage = <725000>;
 579                                         anatop-max-voltage = <1450000>;
 580                                 };
 581
 582                                 reg_soc: regulator-vddsoc {
 583                                         compatible = "fsl,anatop-regulator";
 584                                         regulator-name = "vddsoc";
 585                                         regulator-min-microvolt = <725000>;
 586                                         regulator-max-microvolt = <1450000>;
 587                                         regulator-always-on;
 588                                         anatop-reg-offset = <0x140>;
 589                                         anatop-vol-bit-shift = <18>;
 590                                         anatop-vol-bit-width = <5>;
 591                                         anatop-delay-reg-offset = <0x170>;
 592                                         anatop-delay-bit-shift = <28>;
 593                                         anatop-delay-bit-width = <2>;
 594                                         anatop-min-bit-val = <1>;
 595                                         anatop-min-voltage = <725000>;
 596                                         anatop-max-voltage = <1450000>;
 597                                 };
 598                         };
 599
 600                         usbphy1: usbphy@20c9000 {
 601                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 602                                 reg = <0x020c9000 0x1000>;
 603                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 604                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 605                                 phy-3p0-supply = <&reg_3p0>;
 606                                 fsl,anatop = <&anatop>;
 607                         };
 608
 609                         usbphy2: usbphy@20ca000 {
 610                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 611                                 reg = <0x020ca000 0x1000>;
 612                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 613                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 614                                 phy-3p0-supply = <&reg_3p0>;
 615                                 fsl,anatop = <&anatop>;
 616                         };
 617
 618                         snvs: snvs@20cc000 {
 619                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 620                                 reg = <0x020cc000 0x4000>;
 621
 622                                 snvs_rtc: snvs-rtc-lp {
 623                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 624                                         regmap = <&snvs>;
 625                                         offset = <0x34>;
 626                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 627                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 628                                 };
 629
 630                                 snvs_poweroff: snvs-poweroff {
 631                                         compatible = "syscon-poweroff";
 632                                         regmap = <&snvs>;
 633                                         offset = <0x38>;
 634                                         value = <0x60>;
 635                                         mask = <0x60>;
 636                                         status = "disabled";
 637                                 };
 638
 639                                 snvs_pwrkey: snvs-powerkey {
 640                                         compatible = "fsl,sec-v4.0-pwrkey";
 641                                         regmap = <&snvs>;
 642                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 643                                         linux,keycode = <KEY_POWER>;
 644                                         wakeup-source;
 645                                 };
 646
 647                                 snvs_lpgpr: snvs-lpgpr {
 648                                         compatible = "fsl,imx6ul-snvs-lpgpr";
 649                                 };
 650                         };
 651
 652                         epit1: epit@20d0000 {
 653                                 reg = <0x020d0000 0x4000>;
 654                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 655                         };
 656
 657                         epit2: epit@20d4000 {
 658                                 reg = <0x020d4000 0x4000>;
 659                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 660                         };
 661
 662                         src: src@20d8000 {
 663                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 664                                 reg = <0x020d8000 0x4000>;
 665                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 666                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 667                                 #reset-cells = <1>;
 668                         };
 669
 670                         gpc: gpc@20dc000 {
 671                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 672                                 reg = <0x020dc000 0x4000>;
 673                                 interrupt-controller;
 674                                 #interrupt-cells = <3>;
 675                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 676                                 interrupt-parent = <&intc>;
 677                         };
 678
 679                         iomuxc: iomuxc@20e0000 {
 680                                 compatible = "fsl,imx6ul-iomuxc";
 681                                 reg = <0x020e0000 0x4000>;
 682                         };
 683
 684                         gpr: iomuxc-gpr@20e4000 {
 685                                 compatible = "fsl,imx6ul-iomuxc-gpr",
 686                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 687                                 reg = <0x020e4000 0x4000>;
 688                         };
 689
 690                         gpt2: gpt@20e8000 {
 691                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 692                                 reg = <0x020e8000 0x4000>;
 693                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 694                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 695                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 696                                 clock-names = "ipg", "per";
 697                         };
 698
 699                         sdma: sdma@20ec000 {
 700                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
 701                                              "fsl,imx35-sdma";
 702                                 reg = <0x020ec000 0x4000>;
 703                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 704                                 clocks = <&clks IMX6UL_CLK_SDMA>,
 705                                          <&clks IMX6UL_CLK_SDMA>;
 706                                 clock-names = "ipg", "ahb";
 707                                 #dma-cells = <3>;
 708                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 709                         };
 710
 711                         pwm5: pwm@20f0000 {
 712                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 713                                 reg = <0x020f0000 0x4000>;
 714                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 715                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 716                                          <&clks IMX6UL_CLK_PWM5>;
 717                                 clock-names = "ipg", "per";
 718                                 #pwm-cells = <2>;
 719                                 status = "disabled";
 720                         };
 721
 722                         pwm6: pwm@20f4000 {
 723                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 724                                 reg = <0x020f4000 0x4000>;
 725                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 726                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 727                                          <&clks IMX6UL_CLK_PWM6>;
 728                                 clock-names = "ipg", "per";
 729                                 #pwm-cells = <2>;
 730                                 status = "disabled";
 731                         };
 732
 733                         pwm7: pwm@20f8000 {
 734                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 735                                 reg = <0x020f8000 0x4000>;
 736                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 737                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 738                                          <&clks IMX6UL_CLK_PWM7>;
 739                                 clock-names = "ipg", "per";
 740                                 #pwm-cells = <2>;
 741                                 status = "disabled";
 742                         };
 743
 744                         pwm8: pwm@20fc000 {
 745                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 746                                 reg = <0x020fc000 0x4000>;
 747                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 748                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 749                                          <&clks IMX6UL_CLK_PWM8>;
 750                                 clock-names = "ipg", "per";
 751                                 #pwm-cells = <2>;
 752                                 status = "disabled";
 753                         };
 754                 };
 755
 756                 aips2: aips-bus@2100000 {
 757                         compatible = "fsl,aips-bus", "simple-bus";
 758                         #address-cells = <1>;
 759                         #size-cells = <1>;
 760                         reg = <0x02100000 0x100000>;
 761                         ranges;
 762
 763                         crypto: caam@2140000 {
 764                                 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
 765                                 #address-cells = <1>;
 766                                 #size-cells = <1>;
 767                                 reg = <0x2140000 0x3c000>;
 768                                 ranges = <0 0x2140000 0x3c000>;
 769                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 770                                 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
 771                                          <&clks IMX6UL_CLK_CAAM_MEM>;
 772                                 clock-names = "ipg", "aclk", "mem";
 773
 774                                 sec_jr0: jr0@1000 {
 775                                         compatible = "fsl,sec-v4.0-job-ring";
 776                                         reg = <0x1000 0x1000>;
 777                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 778                                 };
 779
 780                                 sec_jr1: jr1@2000 {
 781                                         compatible = "fsl,sec-v4.0-job-ring";
 782                                         reg = <0x2000 0x1000>;
 783                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 784                                 };
 785
 786                                 sec_jr2: jr2@3000 {
 787                                         compatible = "fsl,sec-v4.0-job-ring";
 788                                         reg = <0x3000 0x1000>;
 789                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 790                                 };
 791                         };
 792
 793                         usbotg1: usb@2184000 {
 794                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 795                                 reg = <0x02184000 0x200>;
 796                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 797                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 798                                 fsl,usbphy = <&usbphy1>;
 799                                 fsl,usbmisc = <&usbmisc 0>;
 800                                 fsl,anatop = <&anatop>;
 801                                 ahb-burst-config = <0x0>;
 802                                 tx-burst-size-dword = <0x10>;
 803                                 rx-burst-size-dword = <0x10>;
 804                                 status = "disabled";
 805                         };
 806
 807                         usbotg2: usb@2184200 {
 808                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 809                                 reg = <0x02184200 0x200>;
 810                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 811                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 812                                 fsl,usbphy = <&usbphy2>;
 813                                 fsl,usbmisc = <&usbmisc 1>;
 814                                 ahb-burst-config = <0x0>;
 815                                 tx-burst-size-dword = <0x10>;
 816                                 rx-burst-size-dword = <0x10>;
 817                                 status = "disabled";
 818                         };
 819
 820                         usbmisc: usbmisc@2184800 {
 821                                 #index-cells = <1>;
 822                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 823                                 reg = <0x02184800 0x200>;
 824                         };
 825
 826                         fec1: ethernet@2188000 {
 827                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 828                                 reg = <0x02188000 0x4000>;
 829                                 interrupt-names = "int0", "pps";
 830                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 831                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 832                                 clocks = <&clks IMX6UL_CLK_ENET>,
 833                                          <&clks IMX6UL_CLK_ENET_AHB>,
 834                                          <&clks IMX6UL_CLK_ENET_PTP>,
 835                                          <&clks IMX6UL_CLK_ENET_REF>,
 836                                          <&clks IMX6UL_CLK_ENET_REF>;
 837                                 clock-names = "ipg", "ahb", "ptp",
 838                                               "enet_clk_ref", "enet_out";
 839                                 fsl,num-tx-queues=<1>;
 840                                 fsl,num-rx-queues=<1>;
 841                                 status = "disabled";
 842                         };
 843
 844                         usdhc1: usdhc@2190000 {
 845                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 846                                 reg = <0x02190000 0x4000>;
 847                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 848                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 849                                          <&clks IMX6UL_CLK_USDHC1>,
 850                                          <&clks IMX6UL_CLK_USDHC1>;
 851                                 clock-names = "ipg", "ahb", "per";
 852                                 bus-width = <4>;
 853                                 status = "disabled";
 854                         };
 855
 856                         usdhc2: usdhc@2194000 {
 857                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 858                                 reg = <0x02194000 0x4000>;
 859                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 860                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 861                                          <&clks IMX6UL_CLK_USDHC2>,
 862                                          <&clks IMX6UL_CLK_USDHC2>;
 863                                 clock-names = "ipg", "ahb", "per";
 864                                 bus-width = <4>;
 865                                 status = "disabled";
 866                         };
 867
 868                         adc1: adc@2198000 {
 869                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 870                                 reg = <0x02198000 0x4000>;
 871                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 872                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 873                                 num-channels = <2>;
 874                                 clock-names = "adc";
 875                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 876                                                          <20000000>;
 877                                 status = "disabled";
 878                         };
 879
 880                         i2c1: i2c@21a0000 {
 881                                 #address-cells = <1>;
 882                                 #size-cells = <0>;
 883                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 884                                 reg = <0x021a0000 0x4000>;
 885                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 886                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 887                                 status = "disabled";
 888                         };
 889
 890                         i2c2: i2c@21a4000 {
 891                                 #address-cells = <1>;
 892                                 #size-cells = <0>;
 893                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 894                                 reg = <0x021a4000 0x4000>;
 895                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 896                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 897                                 status = "disabled";
 898                         };
 899
 900                         i2c3: i2c@21a8000 {
 901                                 #address-cells = <1>;
 902                                 #size-cells = <0>;
 903                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 904                                 reg = <0x021a8000 0x4000>;
 905                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 906                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 907                                 status = "disabled";
 908                         };
 909
 910                         mmdc: mmdc@21b0000 {
 911                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 912                                 reg = <0x021b0000 0x4000>;
 913                         };
 914
 915                         ocotp: ocotp-ctrl@21bc000 {
 916                                 #address-cells = <1>;
 917                                 #size-cells = <1>;
 918                                 compatible = "fsl,imx6ul-ocotp", "syscon";
 919                                 reg = <0x021bc000 0x4000>;
 920                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
 921
 922                                 tempmon_calib: calib@38 {
 923                                         reg = <0x38 4>;
 924                                 };
 925
 926                                 tempmon_temp_grade: temp-grade@20 {
 927                                         reg = <0x20 4>;
 928                                 };
 929                         };
 930
 931                         lcdif: lcdif@21c8000 {
 932                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 933                                 reg = <0x021c8000 0x4000>;
 934                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 935                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 936                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 937                                          <&clks IMX6UL_CLK_DUMMY>;
 938                                 clock-names = "pix", "axi", "disp_axi";
 939                                 status = "disabled";
 940                         };
 941
 942                         qspi: qspi@21e0000 {
 943                                 #address-cells = <1>;
 944                                 #size-cells = <0>;
 945                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 946                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 947                                 reg-names = "QuadSPI", "QuadSPI-memory";
 948                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 949                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 950                                          <&clks IMX6UL_CLK_QSPI>;
 951                                 clock-names = "qspi_en", "qspi";
 952                                 status = "disabled";
 953                         };
 954
 955                         wdog3: wdog@21e4000 {
 956                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 957                                 reg = <0x021e4000 0x4000>;
 958                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 959                                 clocks = <&clks IMX6UL_CLK_WDOG3>;
 960                                 status = "disabled";
 961                         };
 962
 963                         uart2: serial@21e8000 {
 964                                 compatible = "fsl,imx6ul-uart",
 965                                              "fsl,imx6q-uart";
 966                                 reg = <0x021e8000 0x4000>;
 967                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 968                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 969                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 970                                 clock-names = "ipg", "per";
 971                                 status = "disabled";
 972                         };
 973
 974                         uart3: serial@21ec000 {
 975                                 compatible = "fsl,imx6ul-uart",
 976                                              "fsl,imx6q-uart";
 977                                 reg = <0x021ec000 0x4000>;
 978                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 979                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 980                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 981                                 clock-names = "ipg", "per";
 982                                 status = "disabled";
 983                         };
 984
 985                         uart4: serial@21f0000 {
 986                                 compatible = "fsl,imx6ul-uart",
 987                                              "fsl,imx6q-uart";
 988                                 reg = <0x021f0000 0x4000>;
 989                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 990                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 991                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 992                                 clock-names = "ipg", "per";
 993                                 status = "disabled";
 994                         };
 995
 996                         uart5: serial@21f4000 {
 997                                 compatible = "fsl,imx6ul-uart",
 998                                              "fsl,imx6q-uart";
 999                                 reg = <0x021f4000 0x4000>;
1000                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1001                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1002                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
1003                                 clock-names = "ipg", "per";
1004                                 status = "disabled";
1005                         };
1006
1007                         i2c4: i2c@21f8000 {
1008                                 #address-cells = <1>;
1009                                 #size-cells = <0>;
1010                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1011                                 reg = <0x021f8000 0x4000>;
1012                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1013                                 clocks = <&clks IMX6UL_CLK_I2C4>;
1014                                 status = "disabled";
1015                         };
1016
1017                         uart6: serial@21fc000 {
1018                                 compatible = "fsl,imx6ul-uart",
1019                                              "fsl,imx6q-uart";
1020                                 reg = <0x021fc000 0x4000>;
1021                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1022                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1023                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
1024                                 clock-names = "ipg", "per";
1025                                 status = "disabled";
1026                         };
1027                 };
1028         };
1029 };