Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6ul-pico.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 //
3 // Copyright 2015 Technexion Ltd.
4 //
5 // Author: Wig Cheng  <wig.cheng@technexion.com>
6 //         Richard Hu <richard.hu@technexion.com>
7 //         Tapani Utriainen <tapani@technexion.com>
8 /dts-v1/;
9
10 #include "imx6ul.dtsi"
11
12 / {
13         /* Will be filled by the bootloader */
14         memory@80000000 {
15                 device_type = "memory";
16                 reg = <0x80000000 0>;
17         };
18
19         chosen {
20                 stdout-path = &uart6;
21         };
22
23         backlight {
24                 compatible = "pwm-backlight";
25                 pwms = <&pwm3 0 5000000>;
26                 brightness-levels = <0 4 8 16 32 64 128 255>;
27                 default-brightness-level = <6>;
28                 status = "okay";
29         };
30
31         reg_2p5v: regulator-2p5v {
32                 compatible = "regulator-fixed";
33                 regulator-name = "2P5V";
34                 regulator-min-microvolt = <2500000>;
35                 regulator-max-microvolt = <2500000>;
36         };
37
38         reg_3p3v: regulator-3p3v {
39                 compatible = "regulator-fixed";
40                 regulator-name = "3P3V";
41                 regulator-min-microvolt = <3300000>;
42                 regulator-max-microvolt = <3300000>;
43         };
44
45         reg_sd1_vmmc: regulator-sd1-vmmc {
46                 compatible = "regulator-fixed";
47                 regulator-name = "VSD_3V3";
48                 regulator-min-microvolt = <3300000>;
49                 regulator-max-microvolt = <3300000>;
50                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
51                 enable-active-high;
52         };
53
54         reg_usb_otg_vbus: regulator-usb-otg-vbus {
55                 compatible = "regulator-fixed";
56                 pinctrl-names = "default";
57                 pinctrl-0 = <&pinctrl_usb_otg1>;
58                 regulator-name = "usb_otg_vbus";
59                 regulator-min-microvolt = <5000000>;
60                 regulator-max-microvolt = <5000000>;
61                 gpio = <&gpio1 6 0>;
62         };
63
64         reg_brcm: regulator-brcm {
65                 compatible = "regulator-fixed";
66                 enable-active-high;
67                 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
68                 pinctrl-names = "default";
69                 pinctrl-0 = <&pinctrl_brcm_reg>;
70                 regulator-name = "brcm_reg";
71                 regulator-min-microvolt = <3300000>;
72                 regulator-max-microvolt = <3300000>;
73                 startup-delay-us = <200000>;
74         };
75 };
76
77 &can1 {
78         pinctrl-names = "default";
79         pinctrl-0 = <&pinctrl_flexcan1>;
80         status = "okay";
81 };
82
83 &can2 {
84         pinctrl-names = "default";
85         pinctrl-0 = <&pinctrl_flexcan2>;
86         status = "okay";
87 };
88
89 &clks {
90         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
91         assigned-clock-rates = <786432000>;
92 };
93
94 &fec2 {
95         pinctrl-names = "default";
96         pinctrl-0 = <&pinctrl_enet2>;
97         phy-mode = "rmii";
98         phy-handle = <&ethphy1>;
99         status = "okay";
100         phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
101         phy-reset-duration = <1>;
102
103         mdio {
104                 #address-cells = <1>;
105                 #size-cells = <0>;
106
107                 ethphy1: ethernet-phy@1 {
108                         compatible = "ethernet-phy-ieee802.3-c22";
109                         reg = <1>;
110                         max-speed = <100>;
111                         interrupt-parent = <&gpio5>;
112                         interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
113                 };
114         };
115 };
116
117 &i2c1 {
118         clock-frequency = <100000>;
119         pinctrl-names = "default";
120         pinctrl-0 = <&pinctrl_i2c1>;
121         status = "okay";
122
123         pmic: pfuze3000@8 {
124                 compatible = "fsl,pfuze3000";
125                 reg = <0x08>;
126
127                 regulators {
128                         /* VDD_ARM_SOC_IN*/
129                         sw1b_reg: sw1b {
130                                 regulator-min-microvolt = <700000>;
131                                 regulator-max-microvolt = <1475000>;
132                                 regulator-boot-on;
133                                 regulator-always-on;
134                                 regulator-ramp-delay = <6250>;
135                         };
136
137                         /* DRAM */
138                         sw3a_reg: sw3 {
139                                 regulator-min-microvolt = <900000>;
140                                 regulator-max-microvolt = <1650000>;
141                                 regulator-boot-on;
142                                 regulator-always-on;
143                         };
144
145                         /* DRAM */
146                         vref_reg: vrefddr {
147                                 regulator-boot-on;
148                                 regulator-always-on;
149                         };
150                 };
151         };
152 };
153
154 &lcdif {
155         pinctrl-names = "default";
156         pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
157         display = <&display0>;
158         status = "okay";
159
160         display0: display0 {
161                 bits-per-pixel = <32>;
162                 bus-width = <24>;
163
164                 display-timings {
165                         native-mode = <&timing0>;
166
167                         timing0: timing0 {
168                                 clock-frequency = <33200000>;
169                                 hactive = <800>;
170                                 vactive = <480>;
171                                 hfront-porch = <210>;
172                                 hback-porch = <46>;
173                                 hsync-len = <1>;
174                                 vback-porch = <22>;
175                                 vfront-porch = <23>;
176                                 vsync-len = <1>;
177                                 hsync-active = <0>;
178                                 vsync-active = <0>;
179                                 de-active = <1>;
180                                 pixelclk-active = <0>;
181                         };
182                 };
183         };
184 };
185
186 &pwm3 {
187         pinctrl-names = "default";
188         pinctrl-0 = <&pinctrl_pwm3>;
189         status = "okay";
190 };
191
192 &pwm7 {
193         pinctrl-names = "default";
194         pinctrl-0 = <&pinctrl_pwm7>;
195         status = "okay";
196 };
197
198 &pwm8 {
199         pinctrl-names = "default";
200         pinctrl-0 = <&pinctrl_pwm8>;
201         status = "okay";
202 };
203
204 &sai1 {
205         pinctrl-names = "default";
206         pinctrl-0 = <&pinctrl_sai1>;
207         status = "okay";
208 };
209
210 &uart3 {
211         pinctrl-names = "default";
212         pinctrl-0 = <&pinctrl_uart3>;
213         uart-has-rtscts;
214         status = "okay";
215 };
216
217 &uart6 {
218         pinctrl-names = "default";
219         pinctrl-0 = <&pinctrl_uart6>;
220         status = "okay";
221 };
222
223 &usbotg1 {
224         vbus-supply = <&reg_usb_otg_vbus>;
225         pinctrl-names = "default";
226         pinctrl-0 = <&pinctrl_usb_otg1_id>;
227         dr_mode = "otg";
228         disable-over-current;
229         status = "okay";
230 };
231
232 &usbotg2 {
233         dr_mode = "host";
234         disable-over-current;
235         status = "okay";
236 };
237
238 &usdhc1 {
239         pinctrl-names = "default";
240         pinctrl-0 = <&pinctrl_usdhc1>;
241         bus-width = <8>;
242         no-1-8-v;
243         non-removable;
244         keep-power-in-suspend;
245         status = "okay";
246 };
247
248 &usdhc2 {  /* Wifi SDIO */
249         pinctrl-names = "default";
250         pinctrl-0 = <&pinctrl_usdhc2>;
251         no-1-8-v;
252         non-removable;
253         keep-power-in-suspend;
254         wakeup-source;
255         vmmc-supply = <&reg_brcm>;
256         status = "okay";
257 };
258
259 &wdog1 {
260         pinctrl-names = "default";
261         pinctrl-0 = <&pinctrl_wdog>;
262         fsl,ext-reset-output;
263 };
264
265 &iomuxc {
266         pinctrl_brcm_reg: brcmreggrp {
267                 fsl,pins = <
268                         MX6UL_PAD_NAND_DATA06__GPIO4_IO08       0x10b0  /* WL_REG_ON */
269                         MX6UL_PAD_NAND_DATA04__GPIO4_IO06       0x10b0  /* WL_HOST_WAKE */
270                 >;
271         };
272
273         pinctrl_enet2: enet2grp {
274                 fsl,pins = <
275                         MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO    0x1b0b0
276                         MX6UL_PAD_ENET1_TX_EN__ENET2_MDC        0x1b0b0
277                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
278                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
279                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
280                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
281                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
282                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
283                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
284                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
285                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x800
286                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x79
287                 >;
288         };
289
290         pinctrl_flexcan1: flexcan1grp {
291                 fsl,pins = <
292                         MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX   0x1b020
293                         MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX   0x1b020
294                 >;
295         };
296
297         pinctrl_flexcan2: flexcan2grp {
298                 fsl,pins = <
299                         MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
300                         MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX      0x1b020
301                 >;
302         };
303
304         pinctrl_i2c1: i2c1grp {
305                 fsl,pins = <
306                         MX6UL_PAD_GPIO1_IO02__I2C1_SCL          0x4001b8b0
307                         MX6UL_PAD_GPIO1_IO03__I2C1_SDA          0x4001b8b0
308                 >;
309         };
310
311         pinctrl_i2c2: i2c2grp {
312                 fsl,pins = <
313                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL       0x4001b8b0
314                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA       0x4001b8b0
315                 >;
316         };
317
318         pinctrl_i2c3: i2c3grp {
319                 fsl,pins = <
320                         MX6UL_PAD_UART1_TX_DATA__I2C3_SCL       0x4001b8b0
321                         MX6UL_PAD_UART1_RX_DATA__I2C3_SDA       0x4001b8b0
322                         >;
323         };
324
325         pinctrl_lcdif_dat: lcdifdatgrp {
326                 fsl,pins = <
327                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x79
328                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x79
329                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x79
330                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x79
331                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x79
332                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x79
333                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x79
334                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x79
335                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x79
336                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x79
337                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x79
338                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x79
339                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x79
340                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x79
341                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x79
342                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x79
343                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x79
344                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x79
345                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x79
346                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x79
347                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x79
348                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x79
349                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x79
350                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x79
351                 >;
352         };
353
354         pinctrl_lcdif_ctrl: lcdifctrlgrp {
355                 fsl,pins = <
356                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x79
357                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x79
358                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x79
359                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x79
360                         /* LCD reset */
361                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x79
362                 >;
363         };
364
365         pinctrl_pwm3: pwm3grp {
366                 fsl,pins = <
367                         MX6UL_PAD_NAND_ALE__PWM3_OUT            0x110b0
368                 >;
369         };
370
371         pinctrl_pwm7: pwm7grp {
372                 fsl,pins = <
373                         MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT        0x110b0
374                 >;
375         };
376
377         pinctrl_pwm8: pwm8grp {
378                 fsl,pins = <
379                         MX6UL_PAD_ENET1_RX_ER__PWM8_OUT         0x110b0
380                 >;
381         };
382
383         pinctrl_sai1: sai1grp {
384                 fsl,pins = <
385                         MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC      0x1b0b0
386                         MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK      0x1b0b0
387                         MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA      0x110b0
388                         MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA      0x1f0b8
389                 >;
390         };
391
392         pinctrl_uart3: uart3grp {
393                 fsl,pins = <
394                         MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b0
395                         MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b0
396                         MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS    0x1b0b0
397                         MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS    0x1b0b0
398                 >;
399         };
400
401         pinctrl_uart5: uart5grp {
402                 fsl,pins = <
403                         MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x1b0b1
404                         MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x1b0b1
405                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x1b0b1
406                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x1b0b1
407                 >;
408         };
409
410         pinctrl_uart6: uart6grp {
411                 fsl,pins = <
412                         MX6UL_PAD_CSI_MCLK__UART6_DCE_TX        0x1b0b1
413                         MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX      0x1b0b1
414                 >;
415         };
416
417         pinctrl_usb_otg1: usbotg1grp {
418                 fsl,pins = <
419                         MX6UL_PAD_GPIO1_IO06__GPIO1_IO06        0x10b0
420                         >;
421         };
422
423         pinctrl_usb_otg1_id: usbotg1idgrp {
424                 fsl,pins = <
425                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
426                 >;
427         };
428
429         pinctrl_usdhc1: usdhc1grp {
430                 fsl,pins = <
431                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
432                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10071
433                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
434                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
435                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
436                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
437                         MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B      0x03029
438                         MX6UL_PAD_NAND_READY_B__USDHC1_DATA4    0x17059
439                         MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5      0x17059
440                         MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6      0x17059
441                         MX6UL_PAD_NAND_CLE__USDHC1_DATA7        0x17059
442                 >;
443         };
444
445         pinctrl_usdhc2: usdhc2grp {
446                 fsl,pins = <
447                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x17059
448                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x10059
449                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x17059
450                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x17059
451                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x17059
452                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x17059
453                 >;
454         };
455
456         pinctrl_wdog: wdoggrp {
457                 fsl,pins = <
458                         MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
459                 >;
460         };
461 };