arch/arm/boot/dts/imx6ul-geam.dts

   1 // SPDX-License-Identifier: GPL-2.0 OR X11
   2 /*
   3  * Copyright (C) 2016 Amarula Solutions B.V.
   4  * Copyright (C) 2016 Engicam S.r.l.
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/input/input.h>
  11 #include "imx6ul.dtsi"
  12
  13 / {
  14         model = "Engicam GEAM6UL Starter Kit";
  15         compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
  16
  17         memory@80000000 {
  18                 reg = <0x80000000 0x08000000>;
  19         };
  20
  21         backlight {
  22                 compatible = "pwm-backlight";
  23                 pwms = <&pwm8 0 100000>;
  24                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  25                                      10 11 12 13 14 15 16 17 18 19
  26                                      20 21 22 23 24 25 26 27 28 29
  27                                      30 31 32 33 34 35 36 37 38 39
  28                                      40 41 42 43 44 45 46 47 48 49
  29                                      50 51 52 53 54 55 56 57 58 59
  30                                      60 61 62 63 64 65 66 67 68 69
  31                                      70 71 72 73 74 75 76 77 78 79
  32                                      80 81 82 83 84 85 86 87 88 89
  33                                      90 91 92 93 94 95 96 97 98 99
  34                                     100>;
  35                 default-brightness-level = <100>;
  36         };
  37
  38         chosen {
  39                 stdout-path = &uart1;
  40         };
  41
  42         reg_1p8v: regulator-1p8v {
  43                 compatible = "regulator-fixed";
  44                 regulator-name = "1P8V";
  45                 regulator-min-microvolt = <1800000>;
  46                 regulator-max-microvolt = <1800000>;
  47                 regulator-always-on;
  48                 regulator-boot-on;
  49         };
  50
  51         reg_3p3v: regulator-3p3v {
  52                 compatible = "regulator-fixed";
  53                 regulator-name = "3P3V";
  54                 regulator-min-microvolt = <3300000>;
  55                 regulator-max-microvolt = <3300000>;
  56                 regulator-always-on;
  57                 regulator-boot-on;
  58         };
  59
  60         sound {
  61                 compatible = "simple-audio-card";
  62                 simple-audio-card,name = "imx6ul-geam-sgtl5000";
  63                 simple-audio-card,format = "i2s";
  64                 simple-audio-card,bitclock-master = <&dailink_master>;
  65                 simple-audio-card,frame-master = <&dailink_master>;
  66                 simple-audio-card,widgets =
  67                         "Microphone", "Mic Jack",
  68                         "Line", "Line In",
  69                         "Line", "Line Out",
  70                         "Headphone", "Headphone Jack";
  71                 simple-audio-card,routing =
  72                         "MIC_IN", "Mic Jack",
  73                         "Mic Jack", "Mic Bias",
  74                         "Headphone Jack", "HP_OUT";
  75
  76                 simple-audio-card,cpu {
  77                         sound-dai = <&sai2>;
  78                 };
  79
  80                 dailink_master: simple-audio-card,codec {
  81                         sound-dai = <&sgtl5000>;
  82                         clocks = <&clks IMX6UL_CLK_SAI2>;
  83                 };
  84         };
  85 };
  86
  87 &can1 {
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_flexcan1>;
  90         xceiver-supply = <&reg_3p3v>;
  91         status = "okay";
  92 };
  93
  94 &can2 {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_flexcan2>;
  97         xceiver-supply = <&reg_3p3v>;
  98         status = "okay";
  99 };
 100
 101 &fec1 {
 102         pinctrl-names = "default";
 103         pinctrl-0 = <&pinctrl_enet1>;
 104         phy-mode = "rmii";
 105         phy-handle = <&ethphy0>;
 106         status = "okay";
 107 };
 108
 109 &fec2 {
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_enet2>;
 112         phy-mode = "rmii";
 113         phy-handle = <&ethphy1>;
 114         status = "okay";
 115
 116         mdio {
 117                 #address-cells = <1>;
 118                 #size-cells = <0>;
 119
 120                 ethphy0: ethernet-phy@0 {
 121                         compatible = "ethernet-phy-ieee802.3-c22";
 122                         reg = <0>;
 123                 };
 124
 125                 ethphy1: ethernet-phy@1 {
 126                         compatible = "ethernet-phy-ieee802.3-c22";
 127                         reg = <1>;
 128                 };
 129         };
 130 };
 131
 132 &gpmi {
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&pinctrl_gpmi_nand>;
 135         nand-on-flash-bbt;
 136         status = "okay";
 137 };
 138
 139 &i2c1 {
 140         clock-frequency = <100000>;
 141         pinctrl-names = "default";
 142         pinctrl-0 = <&pinctrl_i2c1>;
 143         status = "okay";
 144
 145         sgtl5000: codec@a {
 146                 compatible = "fsl,sgtl5000";
 147                 reg = <0x0a>;
 148                 #sound-dai-cells = <0>;
 149                 clocks = <&clks IMX6UL_CLK_OSC>;
 150                 clock-names = "mclk";
 151                 VDDA-supply = <&reg_3p3v>;
 152                 VDDIO-supply = <&reg_3p3v>;
 153                 VDDD-supply = <&reg_1p8v>;
 154         };
 155 };
 156
 157 &i2c2 {
 158         clock_frequency = <100000>;
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&pinctrl_i2c2>;
 161         status = "okay";
 162 };
 163
 164 &lcdif {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&pinctrl_lcdif_dat
 167                      &pinctrl_lcdif_ctrl>;
 168         display = <&display0>;
 169         status = "okay";
 170
 171         display0: display {
 172                 bits-per-pixel = <16>;
 173                 bus-width = <18>;
 174
 175                 display-timings {
 176                         native-mode = <&timing0>;
 177                         timing0: timing0 {
 178                                 clock-frequency = <28000000>;
 179                                 hactive = <800>;
 180                                 vactive = <480>;
 181                                 hfront-porch = <30>;
 182                                 hback-porch = <30>;
 183                                 hsync-len = <64>;
 184                                 vback-porch = <5>;
 185                                 vfront-porch = <5>;
 186                                 vsync-len = <20>;
 187                                 hsync-active = <0>;
 188                                 vsync-active = <0>;
 189                                 de-active = <1>;
 190                                 pixelclk-active = <0>;
 191                         };
 192                 };
 193         };
 194 };
 195
 196 &pwm8 {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_pwm8>;
 199         status = "okay";
 200 };
 201
 202 &tsc {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_tsc>;
 205         xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 206 };
 207
 208 &sai2 {
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&pinctrl_sai2>;
 211         status = "okay";
 212 };
 213
 214 &tsc {
 215         measure-delay-time = <0x1ffff>;
 216         pre-charge-time = <0x1fff>;
 217         status = "okay";
 218 };
 219
 220 &uart1 {
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&pinctrl_uart1>;
 223         status = "okay";
 224 };
 225
 226 &uart2 {
 227         pinctrl-names = "default";
 228         pinctrl-0 = <&pinctrl_uart2>;
 229         status = "okay";
 230 };
 231
 232 &usbotg1 {
 233         dr_mode = "peripheral";
 234         status = "okay";
 235 };
 236
 237 &usbotg2 {
 238         dr_mode = "host";
 239         status = "okay";
 240 };
 241
 242 &usdhc1 {
 243         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 244         pinctrl-0 = <&pinctrl_usdhc1>;
 245         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 246         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 247         bus-width = <4>;
 248         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 249         no-1-8-v;
 250         status = "okay";
 251 };
 252
 253 &iomuxc {
 254         pinctrl_enet1: enet1grp {
 255                 fsl,pins = <
 256                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 257                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 258                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 259                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 260                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 261                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 262                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 263                 >;
 264         };
 265
 266         pinctrl_enet2: enet2grp {
 267                 fsl,pins = <
 268                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 269                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 270                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 271                         MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15       0x1b0b0         /* ENET_nRST */
 272                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 273                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 274                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 275                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 276                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 277                         MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2    0x4001b031
 278                 >;
 279         };
 280
 281         pinctrl_flexcan1: flexcan1grp {
 282                 fsl,pins = <
 283                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 284                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 285                 >;
 286         };
 287
 288         pinctrl_flexcan2: flexcan2grp {
 289                 fsl,pins = <
 290                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 291                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 292                 >;
 293         };
 294
 295         pinctrl_gpmi_nand: gpminandgrp {
 296                 fsl,pins = <
 297                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
 298                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
 299                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
 300                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
 301                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
 302                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
 303                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
 304                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
 305                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
 306                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
 307                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
 308                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
 309                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
 310                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
 311                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
 312                 >;
 313         };
 314
 315         pinctrl_i2c1: i2c1grp {
 316                 fsl,pins = <
 317                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 318                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 319                 >;
 320         };
 321
 322         pinctrl_i2c2: i2c2grp {
 323                         fsl,pins = <
 324                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 325                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 326                 >;
 327         };
 328
 329         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 330                 fsl,pins = <
 331                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 332                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 333                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 334                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 335                 >;
 336         };
 337
 338         pinctrl_lcdif_dat: lcdifdatgrp {
 339                 fsl,pins = <
 340                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 341                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 342                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 343                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 344                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 345                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 346                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 347                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 348                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 349                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 350                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 351                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 352                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 353                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 354                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 355                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 356                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 357                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 358                 >;
 359         };
 360
 361         pinctrl_pwm8: pwm8grp {
 362                 fsl,pins = <
 363                         MX6UL_PAD_ENET1_RX_ER__PWM8_OUT   0x110b0
 364                 >;
 365         };
 366
 367         pinctrl_tsc: tscgrp {
 368                 fsl,pin = <
 369                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0xb0
 370                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0xb0
 371                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0xb0
 372                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0xb0
 373                 >;
 374         };
 375
 376         pinctrl_sai2: sai2grp {
 377                 fsl,pins = <
 378                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x130b0
 379                         MX6UL_PAD_JTAG_TMS__CCM_CLKO1           0x4001b031
 380                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
 381                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
 382                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x120b0
 383                 >;
 384         };
 385
 386         pinctrl_uart1: uart1grp {
 387                 fsl,pins = <
 388                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 389                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 390                 >;
 391         };
 392
 393         pinctrl_uart2: uart2grp {
 394                 fsl,pins = <
 395                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 396                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 397                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
 398                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
 399                 >;
 400         };
 401
 402         pinctrl_usdhc1: usdhc1grp {
 403                 fsl,pins = <
 404                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
 405                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
 406                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
 407                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
 408                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
 409                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
 410                 >;
 411         };
 412
 413         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 414                 fsl,pins = <
 415                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 416                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
 417                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
 418                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
 419                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
 420                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
 421                 >;
 422         };
 423
 424         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 425                 fsl,pins = <
 426                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 427                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
 428                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
 429                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
 430                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
 431                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
 432                 >;
 433         };
 434
 435         pinctrl_usdhc2: usdhc2grp {
 436                 fsl,pins = <
 437                         MX6UL_PAD_CSI_VSYNC__USDHC2_CLK     0x17070
 438                         MX6UL_PAD_CSI_HSYNC__USDHC2_CMD     0x10070
 439                         MX6UL_PAD_CSI_DATA00__USDHC2_DATA0  0x17070
 440                         MX6UL_PAD_CSI_DATA01__USDHC2_DATA1  0x17070
 441                         MX6UL_PAD_CSI_DATA02__USDHC2_DATA2  0x17070
 442                         MX6UL_PAD_CSI_DATA03__USDHC2_DATA3  0x17070
 443                 >;
 444         };
 445 };