arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Digi International's ConnectCore6UL SBC Pro board device tree source
   4  *
   5  * Copyright 2018 Digi International, Inc.
   6  *
   7  */
   8
   9 /dts-v1/;
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6ul.dtsi"
  13 #include "imx6ul-ccimx6ulsom.dtsi"
  14
  15 / {
  16         model = "Digi International ConnectCore 6UL SBC Pro.";
  17         compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul";
  18
  19         lcd_backlight: backlight {
  20                 compatible = "pwm-backlight";
  21                 pwms = <&pwm5 0 50000>;
  22                 brightness-levels = <0 4 8 16 32 64 128 255>;
  23                 default-brightness-level = <6>;
  24                 status = "okay";
  25         };
  26
  27         reg_usb_otg1_vbus: regulator-usb-otg1 {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "usb_otg1_vbus";
  30                 regulator-min-microvolt = <5000000>;
  31                 regulator-max-microvolt = <5000000>;
  32                 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
  33                 enable-active-high;
  34         };
  35 };
  36
  37 &adc1 {
  38         pinctrl-names = "default";
  39         pinctrl-0 = <&pinctrl_adc1>;
  40         status = "okay";
  41 };
  42
  43 &can1 {
  44         pinctrl-names = "default";
  45         pinctrl-0 = <&pinctrl_flexcan1>;
  46         xceiver-supply = <&ext_3v3>;
  47         status = "okay";
  48 };
  49
  50 /* CAN2 is multiplexed with UART2 RTS/CTS */
  51 &can2 {
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pinctrl_flexcan2>;
  54         xceiver-supply = <&ext_3v3>;
  55         status = "disabled";
  56 };
  57
  58 &ecspi1 {
  59         cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
  60         pinctrl-names = "default";
  61         pinctrl-0 = <&pinctrl_ecspi1_master>;
  62         status = "okay";
  63 };
  64
  65 &fec1 {
  66         pinctrl-names = "default";
  67         pinctrl-0 = <&pinctrl_enet1>;
  68         phy-mode = "rmii";
  69         phy-handle = <&ethphy0>;
  70         status = "okay";
  71 };
  72
  73 &fec2 {
  74         pinctrl-names = "default";
  75         pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
  76         phy-mode = "rmii";
  77         phy-handle = <&ethphy1>;
  78         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
  79         phy-reset-duration = <26>;
  80         status = "okay";
  81
  82         mdio {
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85
  86                 ethphy0: ethernet-phy@0 {
  87                         compatible = "ethernet-phy-ieee802.3-c22";
  88                         smsc,disable-energy-detect;
  89                         reg = <0>;
  90                 };
  91
  92                 ethphy1: ethernet-phy@1 {
  93                         compatible = "ethernet-phy-ieee802.3-c22";
  94                         smsc,disable-energy-detect;
  95                         reg = <1>;
  96                 };
  97         };
  98 };
  99
 100 &gpio5 {
 101         emmc-usd-mux {
 102                 gpio-hog;
 103                 gpios = <1 GPIO_ACTIVE_LOW>;
 104                 output-high;
 105         };
 106 };
 107
 108 &lcdif {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_lcdif_dat0_17
 111                      &pinctrl_lcdif_clken
 112                      &pinctrl_lcdif_hvsync>;
 113         lcd-supply = <&ldo4_ext>;       /* BU90T82 LVDS bridge power */
 114         status = "okay";
 115 };
 116
 117 &ldo4_ext {
 118         regulator-max-microvolt = <1800000>;
 119 };
 120
 121 &pwm1 {
 122         status = "okay";
 123 };
 124
 125 &pwm2 {
 126         status = "okay";
 127 };
 128
 129 &pwm3 {
 130         status = "okay";
 131 };
 132
 133 &pwm4 {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_pwm4>;
 136         status = "okay";
 137 };
 138
 139 &pwm5 {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_pwm5>;
 142         status = "okay";
 143 };
 144
 145 &pwm6 {
 146         status = "okay";
 147 };
 148
 149 &pwm7 {
 150         status = "okay";
 151 };
 152
 153 &pwm8 {
 154         status = "okay";
 155 };
 156
 157 &sai2 {
 158         pinctrl-names = "default", "sleep";
 159         pinctrl-0 = <&pinctrl_sai2>;
 160         pinctrl-1 = <&pinctrl_sai2_sleep>;
 161         assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
 162                           <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,
 163                           <&clks IMX6UL_CLK_SAI2>;
 164         assigned-clock-rates = <0>, <786432000>, <12288000>;
 165         assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 166         status = "okay";
 167 };
 168
 169 /* UART2 RTS/CTS muxed with CAN2 */
 170 &uart2 {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_uart2_4wires>;
 173         uart-has-rtscts;
 174         status = "okay";
 175 };
 176
 177 /* UART3 RTS/CTS muxed with CAN 1 */
 178 &uart3 {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_uart3_2wires>;
 181         status = "okay";
 182 };
 183
 184 &uart5 {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_uart5>;
 187         status = "okay";
 188 };
 189
 190 &usbotg1 {
 191         dr_mode = "otg";
 192         vbus-supply = <&reg_usb_otg1_vbus>;
 193         pinctrl-0 = <&pinctrl_usbotg1>;
 194         status = "okay";
 195 };
 196
 197 &usbotg2 {
 198         dr_mode = "host";
 199         disable-over-current;
 200         status = "okay";
 201 };
 202
 203 /* USDHC2 (microSD conflicts with eMMC) */
 204 &usdhc2 {
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_usdhc2>;
 207         no-1-8-v;
 208         broken-cd;      /* no carrier detect line (use polling) */
 209         status = "okay";
 210 };
 211
 212 &iomuxc {
 213         pinctrl_adc1: adc1grp {
 214                 fsl,pins = <
 215                         /* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */
 216                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0xb0
 217                 >;
 218         };
 219
 220         pinctrl_ecspi1_master: ecspi1grp1 {
 221                 fsl,pins = <
 222                         MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK       0x10b0
 223                         MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI       0x10b0
 224                         MX6UL_PAD_LCD_DATA23__ECSPI1_MISO       0x10b0
 225                         MX6UL_PAD_LCD_DATA21__GPIO3_IO26        0x10b0
 226                 >;
 227         };
 228
 229         pinctrl_enet1: enet1grp {
 230                 fsl,pins = <
 231                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 232                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 233                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 234                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 235                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 236                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 237                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 238                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40017051
 239                 >;
 240         };
 241
 242         pinctrl_enet2: enet2grp {
 243                 fsl,pins = <
 244                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 245                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 246                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 247                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 248                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 249                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 250                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 251                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40017051
 252                 >;
 253         };
 254
 255         pinctrl_enet2_mdio: mdioenet2grp {
 256                 fsl,pins = <
 257                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 258                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 259                 >;
 260         };
 261
 262         pinctrl_flexcan1: flexcan1grp{
 263                 fsl,pins = <
 264                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 265                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 266                 >;
 267         };
 268         pinctrl_flexcan2: flexcan2grp{
 269                 fsl,pins = <
 270                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 271                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 272                 >;
 273         };
 274
 275         pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 {
 276                 fsl,pins = <
 277                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x79
 278                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x79
 279                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x79
 280                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x79
 281                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x79
 282                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x79
 283                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x79
 284                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x79
 285                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x79
 286                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x79
 287                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x79
 288                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x79
 289                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x79
 290                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x79
 291                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x79
 292                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x79
 293                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x79
 294                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x79
 295                 >;
 296         };
 297
 298         pinctrl_lcdif_clken: lcdifctrlgrp1 {
 299                 fsl,pins = <
 300                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x17050
 301                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x79
 302                 >;
 303         };
 304
 305         pinctrl_lcdif_hvsync: lcdifctrlgrp2 {
 306                 fsl,pins = <
 307                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x79
 308                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x79
 309                 >;
 310         };
 311
 312         pinctrl_pwm4: pwm4grp {
 313                 fsl,pins = <
 314                         MX6UL_PAD_GPIO1_IO05__PWM4_OUT          0x110b0
 315                 >;
 316         };
 317
 318         pinctrl_pwm5: pwm5grp {
 319                 fsl,pins = <
 320                         MX6UL_PAD_NAND_DQS__PWM5_OUT            0x110b0
 321                 >;
 322         };
 323
 324         pinctrl_sai2: sai2grp {
 325                 fsl,pins = <
 326                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
 327                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
 328                         MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
 329                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
 330                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
 331                         /* Interrupt */
 332                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x10b0
 333                 >;
 334         };
 335
 336         pinctrl_sai2_sleep: sai2grp-sleep {
 337                 fsl,pins = <
 338                         MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15       0x3000
 339                         MX6UL_PAD_JTAG_TCK__GPIO1_IO14          0x3000
 340                         MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x3000
 341                         MX6UL_PAD_JTAG_TDO__GPIO1_IO12          0x3000
 342                         /* Interrupt */
 343                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x3000
 344                 >;
 345         };
 346
 347         pinctrl_uart2_4wires: uart2grp-4wires {
 348                 fsl,pins = <
 349                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 350                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 351                         MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS    0x1b0b1
 352                         MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS    0x1b0b1
 353                 >;
 354         };
 355
 356         pinctrl_uart3_2wires: uart3grp-2wires {
 357                 fsl,pins = <
 358                         MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b1
 359                         MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b1
 360                 >;
 361         };
 362
 363         pinctrl_uart5: uart5grp {
 364                 fsl,pins = <
 365                         MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
 366                         MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
 367                 >;
 368         };
 369
 370         pinctrl_usdhc2: usdhc2grp {
 371                 fsl,pins = <
 372                         MX6UL_PAD_CSI_HSYNC__USDHC2_CMD         0x17059
 373                         MX6UL_PAD_CSI_VSYNC__USDHC2_CLK         0x10039
 374                         MX6UL_PAD_CSI_DATA00__USDHC2_DATA0      0x17059
 375                         MX6UL_PAD_CSI_DATA01__USDHC2_DATA1      0x17059
 376                         MX6UL_PAD_CSI_DATA02__USDHC2_DATA2      0x17059
 377                         MX6UL_PAD_CSI_DATA03__USDHC2_DATA3      0x17059
 378                         /* Mux selector between eMMC/SD# */
 379                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x79
 380                 >;
 381         };
 382
 383         pinctrl_usbotg1: usbotg1grp {
 384                 fsl,pins = <
 385                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
 386                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0x17059
 387                         MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC       0x17059
 388                 >;
 389         };
 390 };