arch/arm/boot/dts/imx6ul-14x14-evk.dts

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include "imx6ul.dtsi"
  12
  13 / {
  14         model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
  15         compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
  16
  17         chosen {
  18                 stdout-path = &uart1;
  19         };
  20
  21         memory {
  22                 reg = <0x80000000 0x20000000>;
  23         };
  24
  25         regulators {
  26                 compatible = "simple-bus";
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 reg_sd1_vmmc: sd1_regulator {
  31                         compatible = "regulator-fixed";
  32                         regulator-name = "VSD_3V3";
  33                         regulator-min-microvolt = <3300000>;
  34                         regulator-max-microvolt = <3300000>;
  35                         gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  36                         enable-active-high;
  37                 };
  38         };
  39
  40         sound {
  41                 compatible = "simple-audio-card";
  42                 simple-audio-card,name = "mx6ul-wm8960";
  43                 simple-audio-card,format = "i2s";
  44                 simple-audio-card,bitclock-master = <&dailink_master>;
  45                 simple-audio-card,frame-master = <&dailink_master>;
  46                 simple-audio-card,widgets =
  47                         "Microphone", "Mic Jack",
  48                         "Line", "Line In",
  49                         "Line", "Line Out",
  50                         "Speaker", "Speaker",
  51                         "Headphone", "Headphone Jack";
  52                 simple-audio-card,routing =
  53                         "Headphone Jack", "HP_L",
  54                         "Headphone Jack", "HP_R",
  55                         "Speaker", "SPK_LP",
  56                         "Speaker", "SPK_LN",
  57                         "Speaker", "SPK_RP",
  58                         "Speaker", "SPK_RN",
  59                         "LINPUT1", "Mic Jack",
  60                         "LINPUT3", "Mic Jack",
  61                         "RINPUT1", "Mic Jack",
  62                         "RINPUT2", "Mic Jack";
  63
  64                 simple-audio-card,cpu {
  65                         sound-dai = <&sai2>;
  66                 };
  67
  68                 dailink_master: simple-audio-card,codec {
  69                         sound-dai = <&codec>;
  70                         clocks = <&clks IMX6UL_CLK_SAI2>;
  71                 };
  72         };
  73 };
  74
  75 &clks {
  76         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  77         assigned-clock-rates = <786432000>;
  78 };
  79
  80 &cpu0 {
  81         arm-supply = <&reg_arm>;
  82         soc-supply = <&reg_soc>;
  83 };
  84
  85 &i2c2 {
  86         clock_frequency = <100000>;
  87         pinctrl-names = "default";
  88         pinctrl-0 = <&pinctrl_i2c2>;
  89         status = "okay";
  90
  91         codec: wm8960@1a {
  92                 #sound-dai-cells = <0>;
  93                 compatible = "wlf,wm8960";
  94                 reg = <0x1a>;
  95                 wlf,shared-lrclk;
  96         };
  97 };
  98
  99 &fec1 {
 100         pinctrl-names = "default";
 101         pinctrl-0 = <&pinctrl_enet1>;
 102         phy-mode = "rmii";
 103         phy-handle = <&ethphy0>;
 104         status = "okay";
 105 };
 106
 107 &fec2 {
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_enet2>;
 110         phy-mode = "rmii";
 111         phy-handle = <&ethphy1>;
 112         status = "okay";
 113
 114         mdio {
 115                 #address-cells = <1>;
 116                 #size-cells = <0>;
 117
 118                 ethphy0: ethernet-phy@2 {
 119                         reg = <2>;
 120                 };
 121
 122                 ethphy1: ethernet-phy@1 {
 123                         reg = <1>;
 124                 };
 125         };
 126 };
 127
 128 &qspi {
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_qspi>;
 131         status = "okay";
 132
 133         flash0: n25q256a@0 {
 134                 #address-cells = <1>;
 135                 #size-cells = <1>;
 136                 compatible = "micron,n25q256a";
 137                 spi-max-frequency = <29000000>;
 138                 reg = <0>;
 139         };
 140 };
 141
 142 &sai2 {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_sai2>;
 145         assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
 146                           <&clks IMX6UL_CLK_SAI2>;
 147         assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 148         assigned-clock-rates = <0>, <12288000>;
 149         status = "okay";
 150 };
 151
 152 &snvs_poweroff {
 153         status = "okay";
 154 };
 155
 156 &tsc {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_tsc>;
 159         xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 160         measure-delay-time = <0xffff>;
 161         pre-charge-time = <0xfff>;
 162         status = "okay";
 163 };
 164
 165 &uart1 {
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_uart1>;
 168         status = "okay";
 169 };
 170
 171 &uart2 {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_uart2>;
 174         fsl,uart-has-rtscts;
 175         status = "okay";
 176 };
 177
 178 &usbotg1 {
 179         dr_mode = "peripheral";
 180         status = "okay";
 181 };
 182
 183 &usbotg2 {
 184         dr_mode = "host";
 185         disable-over-current;
 186         status = "okay";
 187 };
 188
 189 &usdhc1 {
 190         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 191         pinctrl-0 = <&pinctrl_usdhc1>;
 192         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 193         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 194         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 195         keep-power-in-suspend;
 196         wakeup-source;
 197         vmmc-supply = <&reg_sd1_vmmc>;
 198         status = "okay";
 199 };
 200
 201 &usdhc2 {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_usdhc2>;
 204         no-1-8-v;
 205         keep-power-in-suspend;
 206         wakeup-source;
 207         status = "okay";
 208 };
 209
 210 &iomuxc {
 211         pinctrl-names = "default";
 212
 213         pinctrl_csi1: csi1grp {
 214                 fsl,pins = <
 215                         MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
 216                         MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
 217                         MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
 218                         MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
 219                         MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
 220                         MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
 221                         MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
 222                         MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
 223                         MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
 224                         MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
 225                         MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
 226                         MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
 227                 >;
 228         };
 229
 230         pinctrl_enet1: enet1grp {
 231                 fsl,pins = <
 232                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 233                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 234                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 235                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 236                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 237                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 238                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 239                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 240                 >;
 241         };
 242
 243         pinctrl_enet2: enet2grp {
 244                 fsl,pins = <
 245                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 246                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 247                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 248                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 249                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 250                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 251                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 252                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 253                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 254                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 255                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x17059
 256                 >;
 257         };
 258
 259         pinctrl_flexcan1: flexcan1grp{
 260                 fsl,pins = <
 261                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 262                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 263                 >;
 264         };
 265
 266         pinctrl_flexcan2: flexcan2grp{
 267                 fsl,pins = <
 268                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 269                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 270                 >;
 271         };
 272
 273         pinctrl_i2c1: i2c1grp {
 274                 fsl,pins = <
 275                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 276                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 277                 >;
 278         };
 279
 280         pinctrl_i2c2: i2c2grp {
 281                 fsl,pins = <
 282                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 283                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 284                 >;
 285         };
 286
 287         pinctrl_lcdif_dat: lcdifdatgrp {
 288                 fsl,pins = <
 289                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 290                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 291                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 292                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 293                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 294                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 295                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 296                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 297                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 298                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 299                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 300                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 301                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 302                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 303                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 304                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 305                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 306                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 307                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
 308                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
 309                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
 310                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
 311                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
 312                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
 313                 >;
 314         };
 315
 316         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 317                 fsl,pins = <
 318                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 319                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 320                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 321                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 322                         /* used for lcd reset */
 323                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
 324                 >;
 325         };
 326
 327         pinctrl_qspi: qspigrp {
 328                 fsl,pins = <
 329                         MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
 330                         MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
 331                         MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
 332                         MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
 333                         MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
 334                         MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
 335                 >;
 336         };
 337
 338         pinctrl_sai2: sai2grp {
 339                 fsl,pins = <
 340                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
 341                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
 342                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
 343                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
 344                         MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
 345                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
 346                 >;
 347         };
 348
 349         pinctrl_pwm1: pwm1grp {
 350                 fsl,pins = <
 351                         MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
 352                 >;
 353         };
 354
 355         pinctrl_sim2: sim2grp {
 356                 fsl,pins = <
 357                         MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
 358                         MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
 359                         MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
 360                         MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
 361                         MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
 362                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
 363                 >;
 364         };
 365
 366         pinctrl_tsc: tscgrp {
 367                 fsl,pins = <
 368                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
 369                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
 370                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
 371                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
 372                 >;
 373         };
 374
 375         pinctrl_uart1: uart1grp {
 376                 fsl,pins = <
 377                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 378                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 379                 >;
 380         };
 381
 382         pinctrl_uart2: uart2grp {
 383                 fsl,pins = <
 384                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 385                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 386                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
 387                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
 388                 >;
 389         };
 390
 391         pinctrl_usdhc1: usdhc1grp {
 392                 fsl,pins = <
 393                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 394                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 395                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 396                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 397                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 398                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 399                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
 400                         MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
 401                         MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
 402                 >;
 403         };
 404
 405         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 406                 fsl,pins = <
 407                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 408                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
 409                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
 410                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
 411                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
 412                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
 413
 414                 >;
 415         };
 416
 417         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 418                 fsl,pins = <
 419                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 420                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
 421                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
 422                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
 423                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
 424                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
 425                 >;
 426         };
 427
 428         pinctrl_usdhc2: usdhc2grp {
 429                 fsl,pins = <
 430                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
 431                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
 432                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
 433                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
 434                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
 435                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
 436                 >;
 437         };
 438 };