arch/arm/boot/dts/imx6sx.dtsi

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6sx-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6sx-pinfunc.h"
  14
  15 / {
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         /*
  19          * The decompressor and also some bootloaders rely on a
  20          * pre-existing /chosen node to be available to insert the
  21          * command line and merge other ATAGS info.
  22          * Also for U-Boot there must be a pre-existing /memory node.
  23          */
  24         chosen {};
  25         memory { device_type = "memory"; reg = <0 0>; };
  26
  27         aliases {
  28                 can0 = &flexcan1;
  29                 can1 = &flexcan2;
  30                 ethernet0 = &fec1;
  31                 ethernet1 = &fec2;
  32                 gpio0 = &gpio1;
  33                 gpio1 = &gpio2;
  34                 gpio2 = &gpio3;
  35                 gpio3 = &gpio4;
  36                 gpio4 = &gpio5;
  37                 gpio5 = &gpio6;
  38                 gpio6 = &gpio7;
  39                 i2c0 = &i2c1;
  40                 i2c1 = &i2c2;
  41                 i2c2 = &i2c3;
  42                 i2c3 = &i2c4;
  43                 mmc0 = &usdhc1;
  44                 mmc1 = &usdhc2;
  45                 mmc2 = &usdhc3;
  46                 mmc3 = &usdhc4;
  47                 serial0 = &uart1;
  48                 serial1 = &uart2;
  49                 serial2 = &uart3;
  50                 serial3 = &uart4;
  51                 serial4 = &uart5;
  52                 serial5 = &uart6;
  53                 spi0 = &ecspi1;
  54                 spi1 = &ecspi2;
  55                 spi2 = &ecspi3;
  56                 spi3 = &ecspi4;
  57                 spi4 = &ecspi5;
  58                 usbphy0 = &usbphy1;
  59                 usbphy1 = &usbphy2;
  60         };
  61
  62         cpus {
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65
  66                 cpu0: cpu@0 {
  67                         compatible = "arm,cortex-a9";
  68                         device_type = "cpu";
  69                         reg = <0>;
  70                         next-level-cache = <&L2>;
  71                         operating-points = <
  72                                 /* kHz    uV */
  73                                 996000  1250000
  74                                 792000  1175000
  75                                 396000  1075000
  76                                 198000  975000
  77                         >;
  78                         fsl,soc-operating-points = <
  79                                 /* ARM kHz  SOC uV */
  80                                 996000      1175000
  81                                 792000      1175000
  82                                 396000      1175000
  83                                 198000      1175000
  84                         >;
  85                         clock-latency = <61036>; /* two CLK32 periods */
  86                         clocks = <&clks IMX6SX_CLK_ARM>,
  87                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  88                                  <&clks IMX6SX_CLK_STEP>,
  89                                  <&clks IMX6SX_CLK_PLL1_SW>,
  90                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  91                         clock-names = "arm", "pll2_pfd2_396m", "step",
  92                                       "pll1_sw", "pll1_sys";
  93                         arm-supply = <&reg_arm>;
  94                         soc-supply = <&reg_soc>;
  95                 };
  96         };
  97
  98         intc: interrupt-controller@a01000 {
  99                 compatible = "arm,cortex-a9-gic";
 100                 #interrupt-cells = <3>;
 101                 interrupt-controller;
 102                 reg = <0x00a01000 0x1000>,
 103                       <0x00a00100 0x100>;
 104                 interrupt-parent = <&intc>;
 105         };
 106
 107         clocks {
 108                 #address-cells = <1>;
 109                 #size-cells = <0>;
 110
 111                 ckil: clock@0 {
 112                         compatible = "fixed-clock";
 113                         reg = <0>;
 114                         #clock-cells = <0>;
 115                         clock-frequency = <32768>;
 116                         clock-output-names = "ckil";
 117                 };
 118
 119                 osc: clock@1 {
 120                         compatible = "fixed-clock";
 121                         reg = <1>;
 122                         #clock-cells = <0>;
 123                         clock-frequency = <24000000>;
 124                         clock-output-names = "osc";
 125                 };
 126
 127                 ipp_di0: clock@2 {
 128                         compatible = "fixed-clock";
 129                         reg = <2>;
 130                         #clock-cells = <0>;
 131                         clock-frequency = <0>;
 132                         clock-output-names = "ipp_di0";
 133                 };
 134
 135                 ipp_di1: clock@3 {
 136                         compatible = "fixed-clock";
 137                         reg = <3>;
 138                         #clock-cells = <0>;
 139                         clock-frequency = <0>;
 140                         clock-output-names = "ipp_di1";
 141                 };
 142         };
 143
 144         tempmon: tempmon {
 145                 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
 146                 interrupt-parent = <&gpc>;
 147                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 148                 fsl,tempmon = <&anatop>;
 149                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 150                 nvmem-cell-names = "calib", "temp_grade";
 151                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 152         };
 153
 154         pmu {
 155                 compatible = "arm,cortex-a9-pmu";
 156                 interrupt-parent = <&gpc>;
 157                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 158         };
 159
 160         soc {
 161                 #address-cells = <1>;
 162                 #size-cells = <1>;
 163                 compatible = "simple-bus";
 164                 interrupt-parent = <&gpc>;
 165                 ranges;
 166
 167                 ocram: sram@900000 {
 168                         compatible = "mmio-sram";
 169                         reg = <0x00900000 0x20000>;
 170                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 171                 };
 172
 173                 L2: l2-cache@a02000 {
 174                         compatible = "arm,pl310-cache";
 175                         reg = <0x00a02000 0x1000>;
 176                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 177                         cache-unified;
 178                         cache-level = <2>;
 179                         arm,tag-latency = <4 2 3>;
 180                         arm,data-latency = <4 2 3>;
 181                 };
 182
 183                 gpu: gpu@1800000 {
 184                         compatible = "vivante,gc";
 185                         reg = <0x01800000 0x4000>;
 186                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 187                         clocks = <&clks IMX6SX_CLK_GPU>,
 188                                  <&clks IMX6SX_CLK_GPU>,
 189                                  <&clks IMX6SX_CLK_GPU>;
 190                         clock-names = "bus", "core", "shader";
 191                 };
 192
 193                 dma_apbh: dma-apbh@1804000 {
 194                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 195                         reg = <0x01804000 0x2000>;
 196                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 197                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 200                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 201                         #dma-cells = <1>;
 202                         dma-channels = <4>;
 203                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 204                 };
 205
 206                 gpmi: gpmi-nand@1806000{
 207                         compatible = "fsl,imx6sx-gpmi-nand";
 208                         #address-cells = <1>;
 209                         #size-cells = <1>;
 210                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 211                         reg-names = "gpmi-nand", "bch";
 212                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 213                         interrupt-names = "bch";
 214                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 215                                  <&clks IMX6SX_CLK_GPMI_APB>,
 216                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 217                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 218                                  <&clks IMX6SX_CLK_PER1_BCH>;
 219                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 220                                       "gpmi_bch_apb", "per1_bch";
 221                         dmas = <&dma_apbh 0>;
 222                         dma-names = "rx-tx";
 223                         status = "disabled";
 224                 };
 225
 226                 aips1: aips-bus@2000000 {
 227                         compatible = "fsl,aips-bus", "simple-bus";
 228                         #address-cells = <1>;
 229                         #size-cells = <1>;
 230                         reg = <0x02000000 0x100000>;
 231                         ranges;
 232
 233                         spba-bus@2000000 {
 234                                 compatible = "fsl,spba-bus", "simple-bus";
 235                                 #address-cells = <1>;
 236                                 #size-cells = <1>;
 237                                 reg = <0x02000000 0x40000>;
 238                                 ranges;
 239
 240                                 spdif: spdif@2004000 {
 241                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 242                                         reg = <0x02004000 0x4000>;
 243                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 244                                         dmas = <&sdma 14 18 0>,
 245                                                <&sdma 15 18 0>;
 246                                         dma-names = "rx", "tx";
 247                                         clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
 248                                                  <&clks IMX6SX_CLK_OSC>,
 249                                                  <&clks IMX6SX_CLK_SPDIF>,
 250                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 251                                                  <&clks IMX6SX_CLK_IPG>,
 252                                                  <&clks 0>, <&clks 0>,
 253                                                  <&clks IMX6SX_CLK_SPBA>;
 254                                         clock-names = "core", "rxtx0",
 255                                                       "rxtx1", "rxtx2",
 256                                                       "rxtx3", "rxtx4",
 257                                                       "rxtx5", "rxtx6",
 258                                                       "rxtx7", "spba";
 259                                         status = "disabled";
 260                                 };
 261
 262                                 ecspi1: ecspi@2008000 {
 263                                         #address-cells = <1>;
 264                                         #size-cells = <0>;
 265                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 266                                         reg = <0x02008000 0x4000>;
 267                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 268                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 269                                                  <&clks IMX6SX_CLK_ECSPI1>;
 270                                         clock-names = "ipg", "per";
 271                                         status = "disabled";
 272                                 };
 273
 274                                 ecspi2: ecspi@200c000 {
 275                                         #address-cells = <1>;
 276                                         #size-cells = <0>;
 277                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 278                                         reg = <0x0200c000 0x4000>;
 279                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 280                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 281                                                  <&clks IMX6SX_CLK_ECSPI2>;
 282                                         clock-names = "ipg", "per";
 283                                         status = "disabled";
 284                                 };
 285
 286                                 ecspi3: ecspi@2010000 {
 287                                         #address-cells = <1>;
 288                                         #size-cells = <0>;
 289                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 290                                         reg = <0x02010000 0x4000>;
 291                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 292                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 293                                                  <&clks IMX6SX_CLK_ECSPI3>;
 294                                         clock-names = "ipg", "per";
 295                                         status = "disabled";
 296                                 };
 297
 298                                 ecspi4: ecspi@2014000 {
 299                                         #address-cells = <1>;
 300                                         #size-cells = <0>;
 301                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 302                                         reg = <0x02014000 0x4000>;
 303                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 304                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 305                                                  <&clks IMX6SX_CLK_ECSPI4>;
 306                                         clock-names = "ipg", "per";
 307                                         status = "disabled";
 308                                 };
 309
 310                                 uart1: serial@2020000 {
 311                                         compatible = "fsl,imx6sx-uart",
 312                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 313                                         reg = <0x02020000 0x4000>;
 314                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 315                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 316                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 317                                         clock-names = "ipg", "per";
 318                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 319                                         dma-names = "rx", "tx";
 320                                         status = "disabled";
 321                                 };
 322
 323                                 esai: esai@2024000 {
 324                                         reg = <0x02024000 0x4000>;
 325                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 326                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 327                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 328                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 329                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 330                                                  <&clks IMX6SX_CLK_SPBA>;
 331                                         clock-names = "core", "mem", "extal",
 332                                                       "fsys", "spba";
 333                                         status = "disabled";
 334                                 };
 335
 336                                 ssi1: ssi@2028000 {
 337                                         #sound-dai-cells = <0>;
 338                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 339                                         reg = <0x02028000 0x4000>;
 340                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 341                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 342                                                  <&clks IMX6SX_CLK_SSI1>;
 343                                         clock-names = "ipg", "baud";
 344                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 345                                         dma-names = "rx", "tx";
 346                                         fsl,fifo-depth = <15>;
 347                                         status = "disabled";
 348                                 };
 349
 350                                 ssi2: ssi@202c000 {
 351                                         #sound-dai-cells = <0>;
 352                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 353                                         reg = <0x0202c000 0x4000>;
 354                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 355                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 356                                                  <&clks IMX6SX_CLK_SSI2>;
 357                                         clock-names = "ipg", "baud";
 358                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 359                                         dma-names = "rx", "tx";
 360                                         fsl,fifo-depth = <15>;
 361                                         status = "disabled";
 362                                 };
 363
 364                                 ssi3: ssi@2030000 {
 365                                         #sound-dai-cells = <0>;
 366                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 367                                         reg = <0x02030000 0x4000>;
 368                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 369                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 370                                                  <&clks IMX6SX_CLK_SSI3>;
 371                                         clock-names = "ipg", "baud";
 372                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 373                                         dma-names = "rx", "tx";
 374                                         fsl,fifo-depth = <15>;
 375                                         status = "disabled";
 376                                 };
 377
 378                                 asrc: asrc@2034000 {
 379                                         reg = <0x02034000 0x4000>;
 380                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 381                                         clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
 382                                                  <&clks IMX6SX_CLK_ASRC_IPG>,
 383                                                  <&clks IMX6SX_CLK_SPDIF>,
 384                                                  <&clks IMX6SX_CLK_SPBA>;
 385                                         clock-names = "mem", "ipg", "asrck", "spba";
 386                                         dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
 387                                                <&sdma 19 20 1>, <&sdma 20 20 1>,
 388                                                <&sdma 21 20 1>, <&sdma 22 20 1>;
 389                                         dma-names = "rxa", "rxb", "rxc",
 390                                                     "txa", "txb", "txc";
 391                                         status = "okay";
 392                                 };
 393                         };
 394
 395                         pwm1: pwm@2080000 {
 396                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 397                                 reg = <0x02080000 0x4000>;
 398                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 399                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 400                                          <&clks IMX6SX_CLK_PWM1>;
 401                                 clock-names = "ipg", "per";
 402                                 #pwm-cells = <2>;
 403                         };
 404
 405                         pwm2: pwm@2084000 {
 406                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 407                                 reg = <0x02084000 0x4000>;
 408                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 409                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 410                                          <&clks IMX6SX_CLK_PWM2>;
 411                                 clock-names = "ipg", "per";
 412                                 #pwm-cells = <2>;
 413                         };
 414
 415                         pwm3: pwm@2088000 {
 416                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 417                                 reg = <0x02088000 0x4000>;
 418                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 419                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 420                                          <&clks IMX6SX_CLK_PWM3>;
 421                                 clock-names = "ipg", "per";
 422                                 #pwm-cells = <2>;
 423                         };
 424
 425                         pwm4: pwm@208c000 {
 426                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 427                                 reg = <0x0208c000 0x4000>;
 428                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 429                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 430                                          <&clks IMX6SX_CLK_PWM4>;
 431                                 clock-names = "ipg", "per";
 432                                 #pwm-cells = <2>;
 433                         };
 434
 435                         flexcan1: can@2090000 {
 436                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 437                                 reg = <0x02090000 0x4000>;
 438                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 439                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 440                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 441                                 clock-names = "ipg", "per";
 442                                 status = "disabled";
 443                         };
 444
 445                         flexcan2: can@2094000 {
 446                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 447                                 reg = <0x02094000 0x4000>;
 448                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 449                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 450                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 451                                 clock-names = "ipg", "per";
 452                                 status = "disabled";
 453                         };
 454
 455                         gpt: gpt@2098000 {
 456                                 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
 457                                 reg = <0x02098000 0x4000>;
 458                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 459                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 460                                          <&clks IMX6SX_CLK_GPT_3M>;
 461                                 clock-names = "ipg", "per";
 462                         };
 463
 464                         gpio1: gpio@209c000 {
 465                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 466                                 reg = <0x0209c000 0x4000>;
 467                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 468                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 469                                 gpio-controller;
 470                                 #gpio-cells = <2>;
 471                                 interrupt-controller;
 472                                 #interrupt-cells = <2>;
 473                                 gpio-ranges = <&iomuxc 0 5 26>;
 474                         };
 475
 476                         gpio2: gpio@20a0000 {
 477                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 478                                 reg = <0x020a0000 0x4000>;
 479                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 480                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 481                                 gpio-controller;
 482                                 #gpio-cells = <2>;
 483                                 interrupt-controller;
 484                                 #interrupt-cells = <2>;
 485                                 gpio-ranges = <&iomuxc 0 31 20>;
 486                         };
 487
 488                         gpio3: gpio@20a4000 {
 489                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 490                                 reg = <0x020a4000 0x4000>;
 491                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 492                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 493                                 gpio-controller;
 494                                 #gpio-cells = <2>;
 495                                 interrupt-controller;
 496                                 #interrupt-cells = <2>;
 497                                 gpio-ranges = <&iomuxc 0 51 29>;
 498                         };
 499
 500                         gpio4: gpio@20a8000 {
 501                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 502                                 reg = <0x020a8000 0x4000>;
 503                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 504                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 505                                 gpio-controller;
 506                                 #gpio-cells = <2>;
 507                                 interrupt-controller;
 508                                 #interrupt-cells = <2>;
 509                                 gpio-ranges = <&iomuxc 0 80 32>;
 510                         };
 511
 512                         gpio5: gpio@20ac000 {
 513                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 514                                 reg = <0x020ac000 0x4000>;
 515                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 516                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 517                                 gpio-controller;
 518                                 #gpio-cells = <2>;
 519                                 interrupt-controller;
 520                                 #interrupt-cells = <2>;
 521                                 gpio-ranges = <&iomuxc 0 112 24>;
 522                         };
 523
 524                         gpio6: gpio@20b0000 {
 525                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 526                                 reg = <0x020b0000 0x4000>;
 527                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 528                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 529                                 gpio-controller;
 530                                 #gpio-cells = <2>;
 531                                 interrupt-controller;
 532                                 #interrupt-cells = <2>;
 533                                 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
 534                         };
 535
 536                         gpio7: gpio@20b4000 {
 537                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 538                                 reg = <0x020b4000 0x4000>;
 539                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 540                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 541                                 gpio-controller;
 542                                 #gpio-cells = <2>;
 543                                 interrupt-controller;
 544                                 #interrupt-cells = <2>;
 545                                 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
 546                         };
 547
 548                         kpp: kpp@20b8000 {
 549                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 550                                 reg = <0x020b8000 0x4000>;
 551                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 552                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 553                                 status = "disabled";
 554                         };
 555
 556                         wdog1: wdog@20bc000 {
 557                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 558                                 reg = <0x020bc000 0x4000>;
 559                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 560                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 561                         };
 562
 563                         wdog2: wdog@20c0000 {
 564                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 565                                 reg = <0x020c0000 0x4000>;
 566                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 567                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 568                                 status = "disabled";
 569                         };
 570
 571                         clks: ccm@20c4000 {
 572                                 compatible = "fsl,imx6sx-ccm";
 573                                 reg = <0x020c4000 0x4000>;
 574                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 575                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 576                                 #clock-cells = <1>;
 577                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 578                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 579                         };
 580
 581                         anatop: anatop@20c8000 {
 582                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 583                                              "syscon", "simple-bus";
 584                                 reg = <0x020c8000 0x1000>;
 585                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 586                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 587                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 588                                 #address-cells = <1>;
 589                                 #size-cells = <0>;
 590
 591                                 regulator-1p1@20c8110 {
 592                                         reg = <0x20c8110>;
 593                                         compatible = "fsl,anatop-regulator";
 594                                         regulator-name = "vdd1p1";
 595                                         regulator-min-microvolt = <800000>;
 596                                         regulator-max-microvolt = <1375000>;
 597                                         regulator-always-on;
 598                                         anatop-reg-offset = <0x110>;
 599                                         anatop-vol-bit-shift = <8>;
 600                                         anatop-vol-bit-width = <5>;
 601                                         anatop-min-bit-val = <4>;
 602                                         anatop-min-voltage = <800000>;
 603                                         anatop-max-voltage = <1375000>;
 604                                         anatop-enable-bit = <0>;
 605                                 };
 606
 607                                 regulator-3p0@20c8120 {
 608                                         reg = <0x20c8120>;
 609                                         compatible = "fsl,anatop-regulator";
 610                                         regulator-name = "vdd3p0";
 611                                         regulator-min-microvolt = <2800000>;
 612                                         regulator-max-microvolt = <3150000>;
 613                                         regulator-always-on;
 614                                         anatop-reg-offset = <0x120>;
 615                                         anatop-vol-bit-shift = <8>;
 616                                         anatop-vol-bit-width = <5>;
 617                                         anatop-min-bit-val = <0>;
 618                                         anatop-min-voltage = <2625000>;
 619                                         anatop-max-voltage = <3400000>;
 620                                         anatop-enable-bit = <0>;
 621                                 };
 622
 623                                 regulator-2p5@20c8130 {
 624                                         reg = <0x20c8130>;
 625                                         compatible = "fsl,anatop-regulator";
 626                                         regulator-name = "vdd2p5";
 627                                         regulator-min-microvolt = <2100000>;
 628                                         regulator-max-microvolt = <2875000>;
 629                                         regulator-always-on;
 630                                         anatop-reg-offset = <0x130>;
 631                                         anatop-vol-bit-shift = <8>;
 632                                         anatop-vol-bit-width = <5>;
 633                                         anatop-min-bit-val = <0>;
 634                                         anatop-min-voltage = <2100000>;
 635                                         anatop-max-voltage = <2875000>;
 636                                         anatop-enable-bit = <0>;
 637                                 };
 638
 639                                 reg_arm: regulator-vddcore@20c8140 {
 640                                         reg = <0x20c8140>;
 641                                         compatible = "fsl,anatop-regulator";
 642                                         regulator-name = "vddarm";
 643                                         regulator-min-microvolt = <725000>;
 644                                         regulator-max-microvolt = <1450000>;
 645                                         regulator-always-on;
 646                                         anatop-reg-offset = <0x140>;
 647                                         anatop-vol-bit-shift = <0>;
 648                                         anatop-vol-bit-width = <5>;
 649                                         anatop-delay-reg-offset = <0x170>;
 650                                         anatop-delay-bit-shift = <24>;
 651                                         anatop-delay-bit-width = <2>;
 652                                         anatop-min-bit-val = <1>;
 653                                         anatop-min-voltage = <725000>;
 654                                         anatop-max-voltage = <1450000>;
 655                                 };
 656
 657                                 reg_pcie: regulator-vddpcie@20c8140 {
 658                                         reg = <0x20c8140>;
 659                                         compatible = "fsl,anatop-regulator";
 660                                         regulator-name = "vddpcie";
 661                                         regulator-min-microvolt = <725000>;
 662                                         regulator-max-microvolt = <1450000>;
 663                                         anatop-reg-offset = <0x140>;
 664                                         anatop-vol-bit-shift = <9>;
 665                                         anatop-vol-bit-width = <5>;
 666                                         anatop-delay-reg-offset = <0x170>;
 667                                         anatop-delay-bit-shift = <26>;
 668                                         anatop-delay-bit-width = <2>;
 669                                         anatop-min-bit-val = <1>;
 670                                         anatop-min-voltage = <725000>;
 671                                         anatop-max-voltage = <1450000>;
 672                                 };
 673
 674                                 reg_soc: regulator-vddsoc@20c8140 {
 675                                         reg = <0x20c8140>;
 676                                         compatible = "fsl,anatop-regulator";
 677                                         regulator-name = "vddsoc";
 678                                         regulator-min-microvolt = <725000>;
 679                                         regulator-max-microvolt = <1450000>;
 680                                         regulator-always-on;
 681                                         anatop-reg-offset = <0x140>;
 682                                         anatop-vol-bit-shift = <18>;
 683                                         anatop-vol-bit-width = <5>;
 684                                         anatop-delay-reg-offset = <0x170>;
 685                                         anatop-delay-bit-shift = <28>;
 686                                         anatop-delay-bit-width = <2>;
 687                                         anatop-min-bit-val = <1>;
 688                                         anatop-min-voltage = <725000>;
 689                                         anatop-max-voltage = <1450000>;
 690                                 };
 691                         };
 692
 693                         usbphy1: usbphy@20c9000 {
 694                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 695                                 reg = <0x020c9000 0x1000>;
 696                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 697                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 698                                 fsl,anatop = <&anatop>;
 699                         };
 700
 701                         usbphy2: usbphy@20ca000 {
 702                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 703                                 reg = <0x020ca000 0x1000>;
 704                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 705                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 706                                 fsl,anatop = <&anatop>;
 707                         };
 708
 709                         snvs: snvs@20cc000 {
 710                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 711                                 reg = <0x020cc000 0x4000>;
 712
 713                                 snvs_rtc: snvs-rtc-lp {
 714                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 715                                         regmap = <&snvs>;
 716                                         offset = <0x34>;
 717                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 718                                 };
 719
 720                                 snvs_poweroff: snvs-poweroff {
 721                                         compatible = "syscon-poweroff";
 722                                         regmap = <&snvs>;
 723                                         offset = <0x38>;
 724                                         value = <0x60>;
 725                                         mask = <0x60>;
 726                                         status = "disabled";
 727                                 };
 728
 729                                 snvs_pwrkey: snvs-powerkey {
 730                                         compatible = "fsl,sec-v4.0-pwrkey";
 731                                         regmap = <&snvs>;
 732                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 733                                         linux,keycode = <KEY_POWER>;
 734                                         wakeup-source;
 735                                 };
 736                         };
 737
 738                         epit1: epit@20d0000 {
 739                                 reg = <0x020d0000 0x4000>;
 740                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 741                         };
 742
 743                         epit2: epit@20d4000 {
 744                                 reg = <0x020d4000 0x4000>;
 745                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 746                         };
 747
 748                         src: src@20d8000 {
 749                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 750                                 reg = <0x020d8000 0x4000>;
 751                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 752                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 753                                 #reset-cells = <1>;
 754                         };
 755
 756                         gpc: gpc@20dc000 {
 757                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 758                                 reg = <0x020dc000 0x4000>;
 759                                 interrupt-controller;
 760                                 #interrupt-cells = <3>;
 761                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 762                                 interrupt-parent = <&intc>;
 763                                 clocks = <&clks IMX6SX_CLK_IPG>;
 764                                 clock-names = "ipg";
 765
 766                                 pgc {
 767                                         #address-cells = <1>;
 768                                         #size-cells = <0>;
 769
 770                                         pd_pci: power-domain@3 {
 771                                                 reg = <3>;
 772                                                 #power-domain-cells = <0>;
 773                                                 power-supply = <&reg_pcie>;
 774                                         };
 775                                 };
 776                         };
 777
 778                         iomuxc: iomuxc@20e0000 {
 779                                 compatible = "fsl,imx6sx-iomuxc";
 780                                 reg = <0x020e0000 0x4000>;
 781                         };
 782
 783                         gpr: iomuxc-gpr@20e4000 {
 784                                 compatible = "fsl,imx6sx-iomuxc-gpr",
 785                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 786                                 reg = <0x020e4000 0x4000>;
 787                         };
 788
 789                         sdma: sdma@20ec000 {
 790                                 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
 791                                 reg = <0x020ec000 0x4000>;
 792                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 793                                 clocks = <&clks IMX6SX_CLK_SDMA>,
 794                                          <&clks IMX6SX_CLK_SDMA>;
 795                                 clock-names = "ipg", "ahb";
 796                                 #dma-cells = <3>;
 797                                 /* imx6sx reuses imx6q sdma firmware */
 798                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 799                         };
 800                 };
 801
 802                 aips2: aips-bus@2100000 {
 803                         compatible = "fsl,aips-bus", "simple-bus";
 804                         #address-cells = <1>;
 805                         #size-cells = <1>;
 806                         reg = <0x02100000 0x100000>;
 807                         ranges;
 808
 809                         crypto: caam@2100000 {
 810                                 compatible = "fsl,sec-v4.0";
 811                                 fsl,sec-era = <4>;
 812                                 #address-cells = <1>;
 813                                 #size-cells = <1>;
 814                                 reg = <0x2100000 0x10000>;
 815                                 ranges = <0 0x2100000 0x10000>;
 816                                 interrupt-parent = <&intc>;
 817                                 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
 818                                          <&clks IMX6SX_CLK_CAAM_ACLK>,
 819                                          <&clks IMX6SX_CLK_CAAM_IPG>,
 820                                          <&clks IMX6SX_CLK_EIM_SLOW>;
 821                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
 822
 823                                 sec_jr0: jr0@1000 {
 824                                         compatible = "fsl,sec-v4.0-job-ring";
 825                                         reg = <0x1000 0x1000>;
 826                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 827                                 };
 828
 829                                 sec_jr1: jr1@2000 {
 830                                         compatible = "fsl,sec-v4.0-job-ring";
 831                                         reg = <0x2000 0x1000>;
 832                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 833                                 };
 834                         };
 835
 836                         usbotg1: usb@2184000 {
 837                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 838                                 reg = <0x02184000 0x200>;
 839                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 840                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 841                                 fsl,usbphy = <&usbphy1>;
 842                                 fsl,usbmisc = <&usbmisc 0>;
 843                                 fsl,anatop = <&anatop>;
 844                                 ahb-burst-config = <0x0>;
 845                                 tx-burst-size-dword = <0x10>;
 846                                 rx-burst-size-dword = <0x10>;
 847                                 status = "disabled";
 848                         };
 849
 850                         usbotg2: usb@2184200 {
 851                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 852                                 reg = <0x02184200 0x200>;
 853                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 854                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 855                                 fsl,usbphy = <&usbphy2>;
 856                                 fsl,usbmisc = <&usbmisc 1>;
 857                                 ahb-burst-config = <0x0>;
 858                                 tx-burst-size-dword = <0x10>;
 859                                 rx-burst-size-dword = <0x10>;
 860                                 status = "disabled";
 861                         };
 862
 863                         usbh: usb@2184400 {
 864                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 865                                 reg = <0x02184400 0x200>;
 866                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 867                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 868                                 fsl,usbmisc = <&usbmisc 2>;
 869                                 phy_type = "hsic";
 870                                 fsl,anatop = <&anatop>;
 871                                 dr_mode = "host";
 872                                 ahb-burst-config = <0x0>;
 873                                 tx-burst-size-dword = <0x10>;
 874                                 rx-burst-size-dword = <0x10>;
 875                                 status = "disabled";
 876                         };
 877
 878                         usbmisc: usbmisc@2184800 {
 879                                 #index-cells = <1>;
 880                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
 881                                 reg = <0x02184800 0x200>;
 882                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 883                         };
 884
 885                         fec1: ethernet@2188000 {
 886                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 887                                 reg = <0x02188000 0x4000>;
 888                                 interrupt-names = "int0", "pps";
 889                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 890                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 891                                 clocks = <&clks IMX6SX_CLK_ENET>,
 892                                          <&clks IMX6SX_CLK_ENET_AHB>,
 893                                          <&clks IMX6SX_CLK_ENET_PTP>,
 894                                          <&clks IMX6SX_CLK_ENET_REF>,
 895                                          <&clks IMX6SX_CLK_ENET_PTP>;
 896                                 clock-names = "ipg", "ahb", "ptp",
 897                                               "enet_clk_ref", "enet_out";
 898                                 fsl,num-tx-queues=<3>;
 899                                 fsl,num-rx-queues=<3>;
 900                                 status = "disabled";
 901                         };
 902
 903                         mlb: mlb@218c000 {
 904                                 reg = <0x0218c000 0x4000>;
 905                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 906                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 907                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 908                                 clocks = <&clks IMX6SX_CLK_MLB>;
 909                                 status = "disabled";
 910                         };
 911
 912                         usdhc1: usdhc@2190000 {
 913                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 914                                 reg = <0x02190000 0x4000>;
 915                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 916                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 917                                          <&clks IMX6SX_CLK_USDHC1>,
 918                                          <&clks IMX6SX_CLK_USDHC1>;
 919                                 clock-names = "ipg", "ahb", "per";
 920                                 bus-width = <4>;
 921                                 status = "disabled";
 922                         };
 923
 924                         usdhc2: usdhc@2194000 {
 925                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 926                                 reg = <0x02194000 0x4000>;
 927                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 928                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 929                                          <&clks IMX6SX_CLK_USDHC2>,
 930                                          <&clks IMX6SX_CLK_USDHC2>;
 931                                 clock-names = "ipg", "ahb", "per";
 932                                 bus-width = <4>;
 933                                 status = "disabled";
 934                         };
 935
 936                         usdhc3: usdhc@2198000 {
 937                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 938                                 reg = <0x02198000 0x4000>;
 939                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 940                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
 941                                          <&clks IMX6SX_CLK_USDHC3>,
 942                                          <&clks IMX6SX_CLK_USDHC3>;
 943                                 clock-names = "ipg", "ahb", "per";
 944                                 bus-width = <4>;
 945                                 status = "disabled";
 946                         };
 947
 948                         usdhc4: usdhc@219c000 {
 949                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 950                                 reg = <0x0219c000 0x4000>;
 951                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 952                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
 953                                          <&clks IMX6SX_CLK_USDHC4>,
 954                                          <&clks IMX6SX_CLK_USDHC4>;
 955                                 clock-names = "ipg", "ahb", "per";
 956                                 bus-width = <4>;
 957                                 status = "disabled";
 958                         };
 959
 960                         i2c1: i2c@21a0000 {
 961                                 #address-cells = <1>;
 962                                 #size-cells = <0>;
 963                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 964                                 reg = <0x021a0000 0x4000>;
 965                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 966                                 clocks = <&clks IMX6SX_CLK_I2C1>;
 967                                 status = "disabled";
 968                         };
 969
 970                         i2c2: i2c@21a4000 {
 971                                 #address-cells = <1>;
 972                                 #size-cells = <0>;
 973                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 974                                 reg = <0x021a4000 0x4000>;
 975                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 976                                 clocks = <&clks IMX6SX_CLK_I2C2>;
 977                                 status = "disabled";
 978                         };
 979
 980                         i2c3: i2c@21a8000 {
 981                                 #address-cells = <1>;
 982                                 #size-cells = <0>;
 983                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 984                                 reg = <0x021a8000 0x4000>;
 985                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 986                                 clocks = <&clks IMX6SX_CLK_I2C3>;
 987                                 status = "disabled";
 988                         };
 989
 990                         mmdc: mmdc@21b0000 {
 991                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
 992                                 reg = <0x021b0000 0x4000>;
 993                         };
 994
 995                         fec2: ethernet@21b4000 {
 996                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 997                                 reg = <0x021b4000 0x4000>;
 998                                 interrupt-names = "int0", "pps";
 999                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1000                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1001                                 clocks = <&clks IMX6SX_CLK_ENET>,
1002                                          <&clks IMX6SX_CLK_ENET_AHB>,
1003                                          <&clks IMX6SX_CLK_ENET_PTP>,
1004                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
1005                                          <&clks IMX6SX_CLK_ENET_PTP>;
1006                                 clock-names = "ipg", "ahb", "ptp",
1007                                               "enet_clk_ref", "enet_out";
1008                                 status = "disabled";
1009                         };
1010
1011                         weim: weim@21b8000 {
1012                                 #address-cells = <2>;
1013                                 #size-cells = <1>;
1014                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1015                                 reg = <0x021b8000 0x4000>;
1016                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1017                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1018                                 fsl,weim-cs-gpr = <&gpr>;
1019                                 status = "disabled";
1020                         };
1021
1022                         ocotp: ocotp@21bc000 {
1023                                 #address-cells = <1>;
1024                                 #size-cells = <1>;
1025                                 compatible = "fsl,imx6sx-ocotp", "syscon";
1026                                 reg = <0x021bc000 0x4000>;
1027                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1028
1029                                 tempmon_calib: calib@38 {
1030                                         reg = <0x38 4>;
1031                                 };
1032
1033                                 tempmon_temp_grade: temp-grade@20 {
1034                                         reg = <0x20 4>;
1035                                 };
1036                         };
1037
1038                         sai1: sai@21d4000 {
1039                                 compatible = "fsl,imx6sx-sai";
1040                                 reg = <0x021d4000 0x4000>;
1041                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1042                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1043                                          <&clks IMX6SX_CLK_SAI1>,
1044                                          <&clks 0>, <&clks 0>;
1045                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1046                                 dma-names = "rx", "tx";
1047                                 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1048                                 status = "disabled";
1049                         };
1050
1051                         audmux: audmux@21d8000 {
1052                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1053                                 reg = <0x021d8000 0x4000>;
1054                                 status = "disabled";
1055                         };
1056
1057                         sai2: sai@21dc000 {
1058                                 compatible = "fsl,imx6sx-sai";
1059                                 reg = <0x021dc000 0x4000>;
1060                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1061                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1062                                          <&clks IMX6SX_CLK_SAI2>,
1063                                          <&clks 0>, <&clks 0>;
1064                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1065                                 dma-names = "rx", "tx";
1066                                 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1067                                 status = "disabled";
1068                         };
1069
1070                         qspi1: qspi@21e0000 {
1071                                 #address-cells = <1>;
1072                                 #size-cells = <0>;
1073                                 compatible = "fsl,imx6sx-qspi";
1074                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1075                                 reg-names = "QuadSPI", "QuadSPI-memory";
1076                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1077                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1078                                          <&clks IMX6SX_CLK_QSPI1>;
1079                                 clock-names = "qspi_en", "qspi";
1080                                 status = "disabled";
1081                         };
1082
1083                         qspi2: qspi@21e4000 {
1084                                 #address-cells = <1>;
1085                                 #size-cells = <0>;
1086                                 compatible = "fsl,imx6sx-qspi";
1087                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1088                                 reg-names = "QuadSPI", "QuadSPI-memory";
1089                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1090                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1091                                          <&clks IMX6SX_CLK_QSPI2>;
1092                                 clock-names = "qspi_en", "qspi";
1093                                 status = "disabled";
1094                         };
1095
1096                         uart2: serial@21e8000 {
1097                                 compatible = "fsl,imx6sx-uart",
1098                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1099                                 reg = <0x021e8000 0x4000>;
1100                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1101                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1102                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1103                                 clock-names = "ipg", "per";
1104                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1105                                 dma-names = "rx", "tx";
1106                                 status = "disabled";
1107                         };
1108
1109                         uart3: serial@21ec000 {
1110                                 compatible = "fsl,imx6sx-uart",
1111                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1112                                 reg = <0x021ec000 0x4000>;
1113                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1114                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1115                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1116                                 clock-names = "ipg", "per";
1117                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1118                                 dma-names = "rx", "tx";
1119                                 status = "disabled";
1120                         };
1121
1122                         uart4: serial@21f0000 {
1123                                 compatible = "fsl,imx6sx-uart",
1124                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1125                                 reg = <0x021f0000 0x4000>;
1126                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1127                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1128                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1129                                 clock-names = "ipg", "per";
1130                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1131                                 dma-names = "rx", "tx";
1132                                 status = "disabled";
1133                         };
1134
1135                         uart5: serial@21f4000 {
1136                                 compatible = "fsl,imx6sx-uart",
1137                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1138                                 reg = <0x021f4000 0x4000>;
1139                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1140                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1141                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1142                                 clock-names = "ipg", "per";
1143                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1144                                 dma-names = "rx", "tx";
1145                                 status = "disabled";
1146                         };
1147
1148                         i2c4: i2c@21f8000 {
1149                                 #address-cells = <1>;
1150                                 #size-cells = <0>;
1151                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1152                                 reg = <0x021f8000 0x4000>;
1153                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1154                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1155                                 status = "disabled";
1156                         };
1157                 };
1158
1159                 aips3: aips-bus@2200000 {
1160                         compatible = "fsl,aips-bus", "simple-bus";
1161                         #address-cells = <1>;
1162                         #size-cells = <1>;
1163                         reg = <0x02200000 0x100000>;
1164                         ranges;
1165
1166                         spba-bus@2240000 {
1167                                 compatible = "fsl,spba-bus", "simple-bus";
1168                                 #address-cells = <1>;
1169                                 #size-cells = <1>;
1170                                 reg = <0x02240000 0x40000>;
1171                                 ranges;
1172
1173                                 csi1: csi@2214000 {
1174                                         reg = <0x02214000 0x4000>;
1175                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1176                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1177                                                  <&clks IMX6SX_CLK_CSI>,
1178                                                  <&clks IMX6SX_CLK_DCIC1>;
1179                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1180                                         status = "disabled";
1181                                 };
1182
1183                                 pxp: pxp@2218000 {
1184                                         reg = <0x02218000 0x4000>;
1185                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1186                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1187                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1188                                         clock-names = "pxp-axi", "disp-axi";
1189                                         status = "disabled";
1190                                 };
1191
1192                                 csi2: csi@221c000 {
1193                                         reg = <0x0221c000 0x4000>;
1194                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1195                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1196                                                  <&clks IMX6SX_CLK_CSI>,
1197                                                  <&clks IMX6SX_CLK_DCIC2>;
1198                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1199                                         status = "disabled";
1200                                 };
1201
1202                                 lcdif1: lcdif@2220000 {
1203                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1204                                         reg = <0x02220000 0x4000>;
1205                                         interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1206                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1207                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1208                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1209                                         clock-names = "pix", "axi", "disp_axi";
1210                                         status = "disabled";
1211                                 };
1212
1213                                 lcdif2: lcdif@2224000 {
1214                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1215                                         reg = <0x02224000 0x4000>;
1216                                         interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1217                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1218                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1219                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1220                                         clock-names = "pix", "axi", "disp_axi";
1221                                         status = "disabled";
1222                                 };
1223
1224                                 vadc: vadc@2228000 {
1225                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1226                                         reg-names = "vadc-vafe", "vadc-vdec";
1227                                         clocks = <&clks IMX6SX_CLK_VADC>,
1228                                                  <&clks IMX6SX_CLK_CSI>;
1229                                         clock-names = "vadc", "csi";
1230                                         status = "disabled";
1231                                 };
1232                         };
1233
1234                         adc1: adc@2280000 {
1235                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1236                                 reg = <0x02280000 0x4000>;
1237                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1238                                 clocks = <&clks IMX6SX_CLK_IPG>;
1239                                 clock-names = "adc";
1240                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1241                                                          <20000000>;
1242                                 status = "disabled";
1243                         };
1244
1245                         adc2: adc@2284000 {
1246                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1247                                 reg = <0x02284000 0x4000>;
1248                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1249                                 clocks = <&clks IMX6SX_CLK_IPG>;
1250                                 clock-names = "adc";
1251                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1252                                                          <20000000>;
1253                                 status = "disabled";
1254                         };
1255
1256                         wdog3: wdog@2288000 {
1257                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1258                                 reg = <0x02288000 0x4000>;
1259                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1260                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1261                                 status = "disabled";
1262                         };
1263
1264                         ecspi5: ecspi@228c000 {
1265                                 #address-cells = <1>;
1266                                 #size-cells = <0>;
1267                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1268                                 reg = <0x0228c000 0x4000>;
1269                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1270                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1271                                          <&clks IMX6SX_CLK_ECSPI5>;
1272                                 clock-names = "ipg", "per";
1273                                 status = "disabled";
1274                         };
1275
1276                         uart6: serial@22a0000 {
1277                                 compatible = "fsl,imx6sx-uart",
1278                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1279                                 reg = <0x022a0000 0x4000>;
1280                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1281                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1282                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1283                                 clock-names = "ipg", "per";
1284                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1285                                 dma-names = "rx", "tx";
1286                                 status = "disabled";
1287                         };
1288
1289                         pwm5: pwm@22a4000 {
1290                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1291                                 reg = <0x022a4000 0x4000>;
1292                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1293                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1294                                          <&clks IMX6SX_CLK_PWM5>;
1295                                 clock-names = "ipg", "per";
1296                                 #pwm-cells = <2>;
1297                         };
1298
1299                         pwm6: pwm@22a8000 {
1300                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1301                                 reg = <0x022a8000 0x4000>;
1302                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1303                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1304                                          <&clks IMX6SX_CLK_PWM6>;
1305                                 clock-names = "ipg", "per";
1306                                 #pwm-cells = <2>;
1307                         };
1308
1309                         pwm7: pwm@22ac000 {
1310                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1311                                 reg = <0x022ac000 0x4000>;
1312                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1313                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1314                                          <&clks IMX6SX_CLK_PWM7>;
1315                                 clock-names = "ipg", "per";
1316                                 #pwm-cells = <2>;
1317                         };
1318
1319                         pwm8: pwm@22b0000 {
1320                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1321                                 reg = <0x0022b0000 0x4000>;
1322                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1323                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1324                                          <&clks IMX6SX_CLK_PWM8>;
1325                                 clock-names = "ipg", "per";
1326                                 #pwm-cells = <2>;
1327                         };
1328                 };
1329
1330                 pcie: pcie@8ffc000 {
1331                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1332                         reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1333                         reg-names = "dbi", "config";
1334                         #address-cells = <3>;
1335                         #size-cells = <2>;
1336                         device_type = "pci";
1337                         bus-range = <0x00 0xff>;
1338                         ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
1339                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1340                         num-lanes = <1>;
1341                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1342                         interrupt-names = "msi";
1343                         #interrupt-cells = <1>;
1344                         interrupt-map-mask = <0 0 0 0x7>;
1345                         interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1346                                         <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1347                                         <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1348                                         <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1349                         clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1350                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1351                                  <&clks IMX6SX_CLK_PCIE_REF_125M>,
1352                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1353                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1354                         power-domains = <&pd_pci>;
1355                         status = "disabled";
1356                 };
1357         };
1358
1359         gpu-subsystem {
1360                 compatible = "fsl,imx-gpu-subsystem";
1361                 cores = <&gpu>;
1362         };
1363 };