2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6sx-pinfunc.h"
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
25 memory { device_type = "memory"; reg = <0 0>; };
67 compatible = "arm,cortex-a9";
70 next-level-cache = <&L2>;
78 fsl,soc-operating-points = <
85 clock-latency = <61036>; /* two CLK32 periods */
86 clocks = <&clks IMX6SX_CLK_ARM>,
87 <&clks IMX6SX_CLK_PLL2_PFD2>,
88 <&clks IMX6SX_CLK_STEP>,
89 <&clks IMX6SX_CLK_PLL1_SW>,
90 <&clks IMX6SX_CLK_PLL1_SYS>;
91 clock-names = "arm", "pll2_pfd2_396m", "step",
92 "pll1_sw", "pll1_sys";
93 arm-supply = <®_arm>;
94 soc-supply = <®_soc>;
98 intc: interrupt-controller@00a01000 {
99 compatible = "arm,cortex-a9-gic";
100 #interrupt-cells = <3>;
101 interrupt-controller;
102 reg = <0x00a01000 0x1000>,
104 interrupt-parent = <&intc>;
108 #address-cells = <1>;
112 compatible = "fixed-clock";
115 clock-frequency = <32768>;
116 clock-output-names = "ckil";
120 compatible = "fixed-clock";
123 clock-frequency = <24000000>;
124 clock-output-names = "osc";
128 compatible = "fixed-clock";
131 clock-frequency = <0>;
132 clock-output-names = "ipp_di0";
136 compatible = "fixed-clock";
139 clock-frequency = <0>;
140 clock-output-names = "ipp_di1";
145 #address-cells = <1>;
147 compatible = "simple-bus";
148 interrupt-parent = <&gpc>;
152 compatible = "arm,cortex-a9-pmu";
153 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
156 ocram: sram@00900000 {
157 compatible = "mmio-sram";
158 reg = <0x00900000 0x20000>;
159 clocks = <&clks IMX6SX_CLK_OCRAM>;
162 L2: l2-cache@00a02000 {
163 compatible = "arm,pl310-cache";
164 reg = <0x00a02000 0x1000>;
165 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
168 arm,tag-latency = <4 2 3>;
169 arm,data-latency = <4 2 3>;
173 compatible = "vivante,gc";
174 reg = <0x01800000 0x4000>;
175 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6SX_CLK_GPU>,
177 <&clks IMX6SX_CLK_GPU>,
178 <&clks IMX6SX_CLK_GPU>;
179 clock-names = "bus", "core", "shader";
182 dma_apbh: dma-apbh@01804000 {
183 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
184 reg = <0x01804000 0x2000>;
185 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
192 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
195 gpmi: gpmi-nand@01806000{
196 compatible = "fsl,imx6sx-gpmi-nand";
197 #address-cells = <1>;
199 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
200 reg-names = "gpmi-nand", "bch";
201 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-names = "bch";
203 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
204 <&clks IMX6SX_CLK_GPMI_APB>,
205 <&clks IMX6SX_CLK_GPMI_BCH>,
206 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
207 <&clks IMX6SX_CLK_PER1_BCH>;
208 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
209 "gpmi_bch_apb", "per1_bch";
210 dmas = <&dma_apbh 0>;
215 aips1: aips-bus@02000000 {
216 compatible = "fsl,aips-bus", "simple-bus";
217 #address-cells = <1>;
219 reg = <0x02000000 0x100000>;
223 compatible = "fsl,spba-bus", "simple-bus";
224 #address-cells = <1>;
226 reg = <0x02000000 0x40000>;
229 spdif: spdif@02004000 {
230 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
231 reg = <0x02004000 0x4000>;
232 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
233 dmas = <&sdma 14 18 0>,
235 dma-names = "rx", "tx";
236 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
237 <&clks IMX6SX_CLK_OSC>,
238 <&clks IMX6SX_CLK_SPDIF>,
239 <&clks 0>, <&clks 0>, <&clks 0>,
240 <&clks IMX6SX_CLK_IPG>,
241 <&clks 0>, <&clks 0>,
242 <&clks IMX6SX_CLK_SPBA>;
243 clock-names = "core", "rxtx0",
251 ecspi1: ecspi@02008000 {
252 #address-cells = <1>;
254 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
255 reg = <0x02008000 0x4000>;
256 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6SX_CLK_ECSPI1>,
258 <&clks IMX6SX_CLK_ECSPI1>;
259 clock-names = "ipg", "per";
263 ecspi2: ecspi@0200c000 {
264 #address-cells = <1>;
266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
267 reg = <0x0200c000 0x4000>;
268 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6SX_CLK_ECSPI2>,
270 <&clks IMX6SX_CLK_ECSPI2>;
271 clock-names = "ipg", "per";
275 ecspi3: ecspi@02010000 {
276 #address-cells = <1>;
278 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
279 reg = <0x02010000 0x4000>;
280 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clks IMX6SX_CLK_ECSPI3>,
282 <&clks IMX6SX_CLK_ECSPI3>;
283 clock-names = "ipg", "per";
287 ecspi4: ecspi@02014000 {
288 #address-cells = <1>;
290 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
291 reg = <0x02014000 0x4000>;
292 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6SX_CLK_ECSPI4>,
294 <&clks IMX6SX_CLK_ECSPI4>;
295 clock-names = "ipg", "per";
299 uart1: serial@02020000 {
300 compatible = "fsl,imx6sx-uart",
301 "fsl,imx6q-uart", "fsl,imx21-uart";
302 reg = <0x02020000 0x4000>;
303 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SX_CLK_UART_IPG>,
305 <&clks IMX6SX_CLK_UART_SERIAL>;
306 clock-names = "ipg", "per";
307 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
308 dma-names = "rx", "tx";
312 esai: esai@02024000 {
313 reg = <0x02024000 0x4000>;
314 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
316 <&clks IMX6SX_CLK_ESAI_MEM>,
317 <&clks IMX6SX_CLK_ESAI_EXTAL>,
318 <&clks IMX6SX_CLK_ESAI_IPG>,
319 <&clks IMX6SX_CLK_SPBA>;
320 clock-names = "core", "mem", "extal",
326 #sound-dai-cells = <0>;
327 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
328 reg = <0x02028000 0x4000>;
329 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
331 <&clks IMX6SX_CLK_SSI1>;
332 clock-names = "ipg", "baud";
333 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
334 dma-names = "rx", "tx";
335 fsl,fifo-depth = <15>;
340 #sound-dai-cells = <0>;
341 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
342 reg = <0x0202c000 0x4000>;
343 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
345 <&clks IMX6SX_CLK_SSI2>;
346 clock-names = "ipg", "baud";
347 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
348 dma-names = "rx", "tx";
349 fsl,fifo-depth = <15>;
354 #sound-dai-cells = <0>;
355 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
356 reg = <0x02030000 0x4000>;
357 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
359 <&clks IMX6SX_CLK_SSI3>;
360 clock-names = "ipg", "baud";
361 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
362 dma-names = "rx", "tx";
363 fsl,fifo-depth = <15>;
367 asrc: asrc@02034000 {
368 reg = <0x02034000 0x4000>;
369 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
371 <&clks IMX6SX_CLK_ASRC_IPG>,
372 <&clks IMX6SX_CLK_SPDIF>,
373 <&clks IMX6SX_CLK_SPBA>;
374 clock-names = "mem", "ipg", "asrck", "spba";
375 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
376 <&sdma 19 20 1>, <&sdma 20 20 1>,
377 <&sdma 21 20 1>, <&sdma 22 20 1>;
378 dma-names = "rxa", "rxb", "rxc",
385 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
386 reg = <0x02080000 0x4000>;
387 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clks IMX6SX_CLK_PWM1>,
389 <&clks IMX6SX_CLK_PWM1>;
390 clock-names = "ipg", "per";
395 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
396 reg = <0x02084000 0x4000>;
397 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clks IMX6SX_CLK_PWM2>,
399 <&clks IMX6SX_CLK_PWM2>;
400 clock-names = "ipg", "per";
405 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
406 reg = <0x02088000 0x4000>;
407 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&clks IMX6SX_CLK_PWM3>,
409 <&clks IMX6SX_CLK_PWM3>;
410 clock-names = "ipg", "per";
415 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
416 reg = <0x0208c000 0x4000>;
417 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&clks IMX6SX_CLK_PWM4>,
419 <&clks IMX6SX_CLK_PWM4>;
420 clock-names = "ipg", "per";
424 flexcan1: can@02090000 {
425 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
426 reg = <0x02090000 0x4000>;
427 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
429 <&clks IMX6SX_CLK_CAN1_SERIAL>;
430 clock-names = "ipg", "per";
434 flexcan2: can@02094000 {
435 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
436 reg = <0x02094000 0x4000>;
437 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
439 <&clks IMX6SX_CLK_CAN2_SERIAL>;
440 clock-names = "ipg", "per";
445 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
446 reg = <0x02098000 0x4000>;
447 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
449 <&clks IMX6SX_CLK_GPT_3M>;
450 clock-names = "ipg", "per";
453 gpio1: gpio@0209c000 {
454 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
455 reg = <0x0209c000 0x4000>;
456 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 gpio-ranges = <&iomuxc 0 5 26>;
465 gpio2: gpio@020a0000 {
466 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
467 reg = <0x020a0000 0x4000>;
468 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 gpio-ranges = <&iomuxc 0 31 20>;
477 gpio3: gpio@020a4000 {
478 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
479 reg = <0x020a4000 0x4000>;
480 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 gpio-ranges = <&iomuxc 0 51 29>;
489 gpio4: gpio@020a8000 {
490 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
491 reg = <0x020a8000 0x4000>;
492 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
498 gpio-ranges = <&iomuxc 0 80 32>;
501 gpio5: gpio@020ac000 {
502 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
503 reg = <0x020ac000 0x4000>;
504 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 gpio-ranges = <&iomuxc 0 112 24>;
513 gpio6: gpio@020b0000 {
514 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
515 reg = <0x020b0000 0x4000>;
516 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
522 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
525 gpio7: gpio@020b4000 {
526 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
527 reg = <0x020b4000 0x4000>;
528 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
532 interrupt-controller;
533 #interrupt-cells = <2>;
534 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
538 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
539 reg = <0x020b8000 0x4000>;
540 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&clks IMX6SX_CLK_DUMMY>;
545 wdog1: wdog@020bc000 {
546 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
547 reg = <0x020bc000 0x4000>;
548 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&clks IMX6SX_CLK_DUMMY>;
552 wdog2: wdog@020c0000 {
553 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
554 reg = <0x020c0000 0x4000>;
555 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&clks IMX6SX_CLK_DUMMY>;
561 compatible = "fsl,imx6sx-ccm";
562 reg = <0x020c4000 0x4000>;
563 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
567 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
570 anatop: anatop@020c8000 {
571 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
572 "syscon", "simple-bus";
573 reg = <0x020c8000 0x1000>;
574 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
579 compatible = "fsl,anatop-regulator";
580 regulator-name = "vdd1p1";
581 regulator-min-microvolt = <800000>;
582 regulator-max-microvolt = <1375000>;
584 anatop-reg-offset = <0x110>;
585 anatop-vol-bit-shift = <8>;
586 anatop-vol-bit-width = <5>;
587 anatop-min-bit-val = <4>;
588 anatop-min-voltage = <800000>;
589 anatop-max-voltage = <1375000>;
590 anatop-enable-bit = <0>;
594 compatible = "fsl,anatop-regulator";
595 regulator-name = "vdd3p0";
596 regulator-min-microvolt = <2800000>;
597 regulator-max-microvolt = <3150000>;
599 anatop-reg-offset = <0x120>;
600 anatop-vol-bit-shift = <8>;
601 anatop-vol-bit-width = <5>;
602 anatop-min-bit-val = <0>;
603 anatop-min-voltage = <2625000>;
604 anatop-max-voltage = <3400000>;
605 anatop-enable-bit = <0>;
609 compatible = "fsl,anatop-regulator";
610 regulator-name = "vdd2p5";
611 regulator-min-microvolt = <2100000>;
612 regulator-max-microvolt = <2875000>;
614 anatop-reg-offset = <0x130>;
615 anatop-vol-bit-shift = <8>;
616 anatop-vol-bit-width = <5>;
617 anatop-min-bit-val = <0>;
618 anatop-min-voltage = <2100000>;
619 anatop-max-voltage = <2875000>;
620 anatop-enable-bit = <0>;
623 reg_arm: regulator-vddcore {
624 compatible = "fsl,anatop-regulator";
625 regulator-name = "vddarm";
626 regulator-min-microvolt = <725000>;
627 regulator-max-microvolt = <1450000>;
629 anatop-reg-offset = <0x140>;
630 anatop-vol-bit-shift = <0>;
631 anatop-vol-bit-width = <5>;
632 anatop-delay-reg-offset = <0x170>;
633 anatop-delay-bit-shift = <24>;
634 anatop-delay-bit-width = <2>;
635 anatop-min-bit-val = <1>;
636 anatop-min-voltage = <725000>;
637 anatop-max-voltage = <1450000>;
640 reg_pcie: regulator-vddpcie {
641 compatible = "fsl,anatop-regulator";
642 regulator-name = "vddpcie";
643 regulator-min-microvolt = <725000>;
644 regulator-max-microvolt = <1450000>;
645 anatop-reg-offset = <0x140>;
646 anatop-vol-bit-shift = <9>;
647 anatop-vol-bit-width = <5>;
648 anatop-delay-reg-offset = <0x170>;
649 anatop-delay-bit-shift = <26>;
650 anatop-delay-bit-width = <2>;
651 anatop-min-bit-val = <1>;
652 anatop-min-voltage = <725000>;
653 anatop-max-voltage = <1450000>;
656 reg_soc: regulator-vddsoc {
657 compatible = "fsl,anatop-regulator";
658 regulator-name = "vddsoc";
659 regulator-min-microvolt = <725000>;
660 regulator-max-microvolt = <1450000>;
662 anatop-reg-offset = <0x140>;
663 anatop-vol-bit-shift = <18>;
664 anatop-vol-bit-width = <5>;
665 anatop-delay-reg-offset = <0x170>;
666 anatop-delay-bit-shift = <28>;
667 anatop-delay-bit-width = <2>;
668 anatop-min-bit-val = <1>;
669 anatop-min-voltage = <725000>;
670 anatop-max-voltage = <1450000>;
675 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
676 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
677 fsl,tempmon = <&anatop>;
678 fsl,tempmon-data = <&ocotp>;
679 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
682 usbphy1: usbphy@020c9000 {
683 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
684 reg = <0x020c9000 0x1000>;
685 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&clks IMX6SX_CLK_USBPHY1>;
687 fsl,anatop = <&anatop>;
690 usbphy2: usbphy@020ca000 {
691 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
692 reg = <0x020ca000 0x1000>;
693 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&clks IMX6SX_CLK_USBPHY2>;
695 fsl,anatop = <&anatop>;
698 snvs: snvs@020cc000 {
699 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
700 reg = <0x020cc000 0x4000>;
702 snvs_rtc: snvs-rtc-lp {
703 compatible = "fsl,sec-v4.0-mon-rtc-lp";
706 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
709 snvs_poweroff: snvs-poweroff {
710 compatible = "syscon-poweroff";
717 snvs_pwrkey: snvs-powerkey {
718 compatible = "fsl,sec-v4.0-pwrkey";
720 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
721 linux,keycode = <KEY_POWER>;
726 epit1: epit@020d0000 {
727 reg = <0x020d0000 0x4000>;
728 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
731 epit2: epit@020d4000 {
732 reg = <0x020d4000 0x4000>;
733 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
737 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
738 reg = <0x020d8000 0x4000>;
739 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
745 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
746 reg = <0x020dc000 0x4000>;
747 interrupt-controller;
748 #interrupt-cells = <3>;
749 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
750 interrupt-parent = <&intc>;
753 iomuxc: iomuxc@020e0000 {
754 compatible = "fsl,imx6sx-iomuxc";
755 reg = <0x020e0000 0x4000>;
758 gpr: iomuxc-gpr@020e4000 {
759 compatible = "fsl,imx6sx-iomuxc-gpr",
760 "fsl,imx6q-iomuxc-gpr", "syscon";
761 reg = <0x020e4000 0x4000>;
764 sdma: sdma@020ec000 {
765 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
766 reg = <0x020ec000 0x4000>;
767 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&clks IMX6SX_CLK_SDMA>,
769 <&clks IMX6SX_CLK_SDMA>;
770 clock-names = "ipg", "ahb";
772 /* imx6sx reuses imx6q sdma firmware */
773 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
777 aips2: aips-bus@02100000 {
778 compatible = "fsl,aips-bus", "simple-bus";
779 #address-cells = <1>;
781 reg = <0x02100000 0x100000>;
784 crypto: caam@2100000 {
785 compatible = "fsl,sec-v4.0";
787 #address-cells = <1>;
789 reg = <0x2100000 0x10000>;
790 ranges = <0 0x2100000 0x10000>;
791 interrupt-parent = <&intc>;
792 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
793 <&clks IMX6SX_CLK_CAAM_ACLK>,
794 <&clks IMX6SX_CLK_CAAM_IPG>,
795 <&clks IMX6SX_CLK_EIM_SLOW>;
796 clock-names = "mem", "aclk", "ipg", "emi_slow";
799 compatible = "fsl,sec-v4.0-job-ring";
800 reg = <0x1000 0x1000>;
801 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
805 compatible = "fsl,sec-v4.0-job-ring";
806 reg = <0x2000 0x1000>;
807 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
811 usbotg1: usb@02184000 {
812 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
813 reg = <0x02184000 0x200>;
814 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clks IMX6SX_CLK_USBOH3>;
816 fsl,usbphy = <&usbphy1>;
817 fsl,usbmisc = <&usbmisc 0>;
818 fsl,anatop = <&anatop>;
819 ahb-burst-config = <0x0>;
820 tx-burst-size-dword = <0x10>;
821 rx-burst-size-dword = <0x10>;
825 usbotg2: usb@02184200 {
826 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
827 reg = <0x02184200 0x200>;
828 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clks IMX6SX_CLK_USBOH3>;
830 fsl,usbphy = <&usbphy2>;
831 fsl,usbmisc = <&usbmisc 1>;
832 ahb-burst-config = <0x0>;
833 tx-burst-size-dword = <0x10>;
834 rx-burst-size-dword = <0x10>;
839 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
840 reg = <0x02184400 0x200>;
841 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&clks IMX6SX_CLK_USBOH3>;
843 fsl,usbmisc = <&usbmisc 2>;
845 fsl,anatop = <&anatop>;
847 ahb-burst-config = <0x0>;
848 tx-burst-size-dword = <0x10>;
849 rx-burst-size-dword = <0x10>;
853 usbmisc: usbmisc@02184800 {
855 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
856 reg = <0x02184800 0x200>;
857 clocks = <&clks IMX6SX_CLK_USBOH3>;
860 fec1: ethernet@02188000 {
861 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
862 reg = <0x02188000 0x4000>;
863 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
864 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&clks IMX6SX_CLK_ENET>,
866 <&clks IMX6SX_CLK_ENET_AHB>,
867 <&clks IMX6SX_CLK_ENET_PTP>,
868 <&clks IMX6SX_CLK_ENET_REF>,
869 <&clks IMX6SX_CLK_ENET_PTP>;
870 clock-names = "ipg", "ahb", "ptp",
871 "enet_clk_ref", "enet_out";
872 fsl,num-tx-queues=<3>;
873 fsl,num-rx-queues=<3>;
878 reg = <0x0218c000 0x4000>;
879 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
880 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&clks IMX6SX_CLK_MLB>;
886 usdhc1: usdhc@02190000 {
887 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
888 reg = <0x02190000 0x4000>;
889 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&clks IMX6SX_CLK_USDHC1>,
891 <&clks IMX6SX_CLK_USDHC1>,
892 <&clks IMX6SX_CLK_USDHC1>;
893 clock-names = "ipg", "ahb", "per";
898 usdhc2: usdhc@02194000 {
899 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
900 reg = <0x02194000 0x4000>;
901 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&clks IMX6SX_CLK_USDHC2>,
903 <&clks IMX6SX_CLK_USDHC2>,
904 <&clks IMX6SX_CLK_USDHC2>;
905 clock-names = "ipg", "ahb", "per";
910 usdhc3: usdhc@02198000 {
911 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
912 reg = <0x02198000 0x4000>;
913 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&clks IMX6SX_CLK_USDHC3>,
915 <&clks IMX6SX_CLK_USDHC3>,
916 <&clks IMX6SX_CLK_USDHC3>;
917 clock-names = "ipg", "ahb", "per";
922 usdhc4: usdhc@0219c000 {
923 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
924 reg = <0x0219c000 0x4000>;
925 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&clks IMX6SX_CLK_USDHC4>,
927 <&clks IMX6SX_CLK_USDHC4>,
928 <&clks IMX6SX_CLK_USDHC4>;
929 clock-names = "ipg", "ahb", "per";
935 #address-cells = <1>;
937 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
938 reg = <0x021a0000 0x4000>;
939 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&clks IMX6SX_CLK_I2C1>;
945 #address-cells = <1>;
947 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
948 reg = <0x021a4000 0x4000>;
949 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&clks IMX6SX_CLK_I2C2>;
955 #address-cells = <1>;
957 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
958 reg = <0x021a8000 0x4000>;
959 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&clks IMX6SX_CLK_I2C3>;
964 mmdc: mmdc@021b0000 {
965 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
966 reg = <0x021b0000 0x4000>;
969 fec2: ethernet@021b4000 {
970 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
971 reg = <0x021b4000 0x4000>;
972 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&clks IMX6SX_CLK_ENET>,
975 <&clks IMX6SX_CLK_ENET_AHB>,
976 <&clks IMX6SX_CLK_ENET_PTP>,
977 <&clks IMX6SX_CLK_ENET2_REF_125M>,
978 <&clks IMX6SX_CLK_ENET_PTP>;
979 clock-names = "ipg", "ahb", "ptp",
980 "enet_clk_ref", "enet_out";
984 weim: weim@021b8000 {
985 #address-cells = <2>;
987 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
988 reg = <0x021b8000 0x4000>;
989 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
991 fsl,weim-cs-gpr = <&gpr>;
995 ocotp: ocotp@021bc000 {
996 compatible = "fsl,imx6sx-ocotp", "syscon";
997 reg = <0x021bc000 0x4000>;
998 clocks = <&clks IMX6SX_CLK_OCOTP>;
1001 sai1: sai@021d4000 {
1002 compatible = "fsl,imx6sx-sai";
1003 reg = <0x021d4000 0x4000>;
1004 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1006 <&clks IMX6SX_CLK_SAI1>,
1007 <&clks 0>, <&clks 0>;
1008 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1009 dma-names = "rx", "tx";
1010 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1011 status = "disabled";
1014 audmux: audmux@021d8000 {
1015 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1016 reg = <0x021d8000 0x4000>;
1017 status = "disabled";
1020 sai2: sai@021dc000 {
1021 compatible = "fsl,imx6sx-sai";
1022 reg = <0x021dc000 0x4000>;
1023 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1025 <&clks IMX6SX_CLK_SAI2>,
1026 <&clks 0>, <&clks 0>;
1027 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1028 dma-names = "rx", "tx";
1029 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1030 status = "disabled";
1033 qspi1: qspi@021e0000 {
1034 #address-cells = <1>;
1036 compatible = "fsl,imx6sx-qspi";
1037 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1038 reg-names = "QuadSPI", "QuadSPI-memory";
1039 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1040 clocks = <&clks IMX6SX_CLK_QSPI1>,
1041 <&clks IMX6SX_CLK_QSPI1>;
1042 clock-names = "qspi_en", "qspi";
1043 status = "disabled";
1046 qspi2: qspi@021e4000 {
1047 #address-cells = <1>;
1049 compatible = "fsl,imx6sx-qspi";
1050 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1051 reg-names = "QuadSPI", "QuadSPI-memory";
1052 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&clks IMX6SX_CLK_QSPI2>,
1054 <&clks IMX6SX_CLK_QSPI2>;
1055 clock-names = "qspi_en", "qspi";
1056 status = "disabled";
1059 uart2: serial@021e8000 {
1060 compatible = "fsl,imx6sx-uart",
1061 "fsl,imx6q-uart", "fsl,imx21-uart";
1062 reg = <0x021e8000 0x4000>;
1063 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1065 <&clks IMX6SX_CLK_UART_SERIAL>;
1066 clock-names = "ipg", "per";
1067 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1068 dma-names = "rx", "tx";
1069 status = "disabled";
1072 uart3: serial@021ec000 {
1073 compatible = "fsl,imx6sx-uart",
1074 "fsl,imx6q-uart", "fsl,imx21-uart";
1075 reg = <0x021ec000 0x4000>;
1076 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1078 <&clks IMX6SX_CLK_UART_SERIAL>;
1079 clock-names = "ipg", "per";
1080 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1081 dma-names = "rx", "tx";
1082 status = "disabled";
1085 uart4: serial@021f0000 {
1086 compatible = "fsl,imx6sx-uart",
1087 "fsl,imx6q-uart", "fsl,imx21-uart";
1088 reg = <0x021f0000 0x4000>;
1089 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1091 <&clks IMX6SX_CLK_UART_SERIAL>;
1092 clock-names = "ipg", "per";
1093 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1094 dma-names = "rx", "tx";
1095 status = "disabled";
1098 uart5: serial@021f4000 {
1099 compatible = "fsl,imx6sx-uart",
1100 "fsl,imx6q-uart", "fsl,imx21-uart";
1101 reg = <0x021f4000 0x4000>;
1102 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1104 <&clks IMX6SX_CLK_UART_SERIAL>;
1105 clock-names = "ipg", "per";
1106 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1107 dma-names = "rx", "tx";
1108 status = "disabled";
1111 i2c4: i2c@021f8000 {
1112 #address-cells = <1>;
1114 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1115 reg = <0x021f8000 0x4000>;
1116 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1117 clocks = <&clks IMX6SX_CLK_I2C4>;
1118 status = "disabled";
1122 aips3: aips-bus@02200000 {
1123 compatible = "fsl,aips-bus", "simple-bus";
1124 #address-cells = <1>;
1126 reg = <0x02200000 0x100000>;
1130 compatible = "fsl,spba-bus", "simple-bus";
1131 #address-cells = <1>;
1133 reg = <0x02240000 0x40000>;
1136 csi1: csi@02214000 {
1137 reg = <0x02214000 0x4000>;
1138 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1139 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1140 <&clks IMX6SX_CLK_CSI>,
1141 <&clks IMX6SX_CLK_DCIC1>;
1142 clock-names = "disp-axi", "csi_mclk", "dcic";
1143 status = "disabled";
1147 reg = <0x02218000 0x4000>;
1148 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1149 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1150 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1151 clock-names = "pxp-axi", "disp-axi";
1152 status = "disabled";
1155 csi2: csi@0221c000 {
1156 reg = <0x0221c000 0x4000>;
1157 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1158 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1159 <&clks IMX6SX_CLK_CSI>,
1160 <&clks IMX6SX_CLK_DCIC2>;
1161 clock-names = "disp-axi", "csi_mclk", "dcic";
1162 status = "disabled";
1165 lcdif1: lcdif@02220000 {
1166 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1167 reg = <0x02220000 0x4000>;
1168 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1169 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1170 <&clks IMX6SX_CLK_LCDIF_APB>,
1171 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1172 clock-names = "pix", "axi", "disp_axi";
1173 status = "disabled";
1176 lcdif2: lcdif@02224000 {
1177 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1178 reg = <0x02224000 0x4000>;
1179 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1180 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1181 <&clks IMX6SX_CLK_LCDIF_APB>,
1182 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1183 clock-names = "pix", "axi", "disp_axi";
1184 status = "disabled";
1187 vadc: vadc@02228000 {
1188 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1189 reg-names = "vadc-vafe", "vadc-vdec";
1190 clocks = <&clks IMX6SX_CLK_VADC>,
1191 <&clks IMX6SX_CLK_CSI>;
1192 clock-names = "vadc", "csi";
1193 status = "disabled";
1197 adc1: adc@02280000 {
1198 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1199 reg = <0x02280000 0x4000>;
1200 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&clks IMX6SX_CLK_IPG>;
1202 clock-names = "adc";
1203 fsl,adck-max-frequency = <30000000>, <40000000>,
1205 status = "disabled";
1208 adc2: adc@02284000 {
1209 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1210 reg = <0x02284000 0x4000>;
1211 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1212 clocks = <&clks IMX6SX_CLK_IPG>;
1213 clock-names = "adc";
1214 fsl,adck-max-frequency = <30000000>, <40000000>,
1216 status = "disabled";
1219 wdog3: wdog@02288000 {
1220 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1221 reg = <0x02288000 0x4000>;
1222 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&clks IMX6SX_CLK_DUMMY>;
1224 status = "disabled";
1227 ecspi5: ecspi@0228c000 {
1228 #address-cells = <1>;
1230 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1231 reg = <0x0228c000 0x4000>;
1232 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1233 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1234 <&clks IMX6SX_CLK_ECSPI5>;
1235 clock-names = "ipg", "per";
1236 status = "disabled";
1239 uart6: serial@022a0000 {
1240 compatible = "fsl,imx6sx-uart",
1241 "fsl,imx6q-uart", "fsl,imx21-uart";
1242 reg = <0x022a0000 0x4000>;
1243 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1245 <&clks IMX6SX_CLK_UART_SERIAL>;
1246 clock-names = "ipg", "per";
1247 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1248 dma-names = "rx", "tx";
1249 status = "disabled";
1252 pwm5: pwm@022a4000 {
1253 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1254 reg = <0x022a4000 0x4000>;
1255 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&clks IMX6SX_CLK_PWM5>,
1257 <&clks IMX6SX_CLK_PWM5>;
1258 clock-names = "ipg", "per";
1262 pwm6: pwm@022a8000 {
1263 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1264 reg = <0x022a8000 0x4000>;
1265 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1266 clocks = <&clks IMX6SX_CLK_PWM6>,
1267 <&clks IMX6SX_CLK_PWM6>;
1268 clock-names = "ipg", "per";
1272 pwm7: pwm@022ac000 {
1273 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1274 reg = <0x022ac000 0x4000>;
1275 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1276 clocks = <&clks IMX6SX_CLK_PWM7>,
1277 <&clks IMX6SX_CLK_PWM7>;
1278 clock-names = "ipg", "per";
1282 pwm8: pwm@0022b0000 {
1283 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1284 reg = <0x0022b0000 0x4000>;
1285 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1286 clocks = <&clks IMX6SX_CLK_PWM8>,
1287 <&clks IMX6SX_CLK_PWM8>;
1288 clock-names = "ipg", "per";
1293 pcie: pcie@8ffc000 {
1294 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1295 reg = <0x08ffc000 0x4000>; /* DBI */
1296 #address-cells = <3>;
1298 device_type = "pci";
1299 /* configuration space */
1300 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1301 /* downstream I/O */
1302 0x81000000 0 0 0x08f80000 0 0x00010000
1303 /* non-prefetchable memory */
1304 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1305 bus-range = <0x00 0xff>;
1307 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1308 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1309 <&clks IMX6SX_CLK_PCIE_AXI>,
1310 <&clks IMX6SX_CLK_LVDS1_OUT>,
1311 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1312 clock-names = "pcie_ref_125m", "pcie_axi",
1313 "lvds_gate", "display_axi";
1314 status = "disabled";
1319 compatible = "fsl,imx-gpu-subsystem";