arch/arm/boot/dts/imx6sx.dtsi

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6sx-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6sx-pinfunc.h"
  14
  15 / {
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         /*
  19          * The decompressor and also some bootloaders rely on a
  20          * pre-existing /chosen node to be available to insert the
  21          * command line and merge other ATAGS info.
  22          * Also for U-Boot there must be a pre-existing /memory node.
  23          */
  24         chosen {};
  25         memory { device_type = "memory"; reg = <0 0>; };
  26
  27         aliases {
  28                 can0 = &flexcan1;
  29                 can1 = &flexcan2;
  30                 ethernet0 = &fec1;
  31                 ethernet1 = &fec2;
  32                 gpio0 = &gpio1;
  33                 gpio1 = &gpio2;
  34                 gpio2 = &gpio3;
  35                 gpio3 = &gpio4;
  36                 gpio4 = &gpio5;
  37                 gpio5 = &gpio6;
  38                 gpio6 = &gpio7;
  39                 i2c0 = &i2c1;
  40                 i2c1 = &i2c2;
  41                 i2c2 = &i2c3;
  42                 i2c3 = &i2c4;
  43                 mmc0 = &usdhc1;
  44                 mmc1 = &usdhc2;
  45                 mmc2 = &usdhc3;
  46                 mmc3 = &usdhc4;
  47                 serial0 = &uart1;
  48                 serial1 = &uart2;
  49                 serial2 = &uart3;
  50                 serial3 = &uart4;
  51                 serial4 = &uart5;
  52                 serial5 = &uart6;
  53                 spi0 = &ecspi1;
  54                 spi1 = &ecspi2;
  55                 spi2 = &ecspi3;
  56                 spi3 = &ecspi4;
  57                 spi4 = &ecspi5;
  58                 usbphy0 = &usbphy1;
  59                 usbphy1 = &usbphy2;
  60         };
  61
  62         cpus {
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65
  66                 cpu0: cpu@0 {
  67                         compatible = "arm,cortex-a9";
  68                         device_type = "cpu";
  69                         reg = <0>;
  70                         next-level-cache = <&L2>;
  71                         operating-points = <
  72                                 /* kHz    uV */
  73                                 996000  1250000
  74                                 792000  1175000
  75                                 396000  1075000
  76                                 198000  975000
  77                         >;
  78                         fsl,soc-operating-points = <
  79                                 /* ARM kHz  SOC uV */
  80                                 996000      1175000
  81                                 792000      1175000
  82                                 396000      1175000
  83                                 198000      1175000
  84                         >;
  85                         clock-latency = <61036>; /* two CLK32 periods */
  86                         clocks = <&clks IMX6SX_CLK_ARM>,
  87                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  88                                  <&clks IMX6SX_CLK_STEP>,
  89                                  <&clks IMX6SX_CLK_PLL1_SW>,
  90                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  91                         clock-names = "arm", "pll2_pfd2_396m", "step",
  92                                       "pll1_sw", "pll1_sys";
  93                         arm-supply = <&reg_arm>;
  94                         soc-supply = <&reg_soc>;
  95                 };
  96         };
  97
  98         intc: interrupt-controller@a01000 {
  99                 compatible = "arm,cortex-a9-gic";
 100                 #interrupt-cells = <3>;
 101                 interrupt-controller;
 102                 reg = <0x00a01000 0x1000>,
 103                       <0x00a00100 0x100>;
 104                 interrupt-parent = <&intc>;
 105         };
 106
 107         clocks {
 108                 #address-cells = <1>;
 109                 #size-cells = <0>;
 110
 111                 ckil: clock@0 {
 112                         compatible = "fixed-clock";
 113                         reg = <0>;
 114                         #clock-cells = <0>;
 115                         clock-frequency = <32768>;
 116                         clock-output-names = "ckil";
 117                 };
 118
 119                 osc: clock@1 {
 120                         compatible = "fixed-clock";
 121                         reg = <1>;
 122                         #clock-cells = <0>;
 123                         clock-frequency = <24000000>;
 124                         clock-output-names = "osc";
 125                 };
 126
 127                 ipp_di0: clock@2 {
 128                         compatible = "fixed-clock";
 129                         reg = <2>;
 130                         #clock-cells = <0>;
 131                         clock-frequency = <0>;
 132                         clock-output-names = "ipp_di0";
 133                 };
 134
 135                 ipp_di1: clock@3 {
 136                         compatible = "fixed-clock";
 137                         reg = <3>;
 138                         #clock-cells = <0>;
 139                         clock-frequency = <0>;
 140                         clock-output-names = "ipp_di1";
 141                 };
 142         };
 143
 144         soc {
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 compatible = "simple-bus";
 148                 interrupt-parent = <&gpc>;
 149                 ranges;
 150
 151                 pmu {
 152                         compatible = "arm,cortex-a9-pmu";
 153                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 154                 };
 155
 156                 ocram: sram@900000 {
 157                         compatible = "mmio-sram";
 158                         reg = <0x00900000 0x20000>;
 159                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 160                 };
 161
 162                 L2: l2-cache@a02000 {
 163                         compatible = "arm,pl310-cache";
 164                         reg = <0x00a02000 0x1000>;
 165                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 166                         cache-unified;
 167                         cache-level = <2>;
 168                         arm,tag-latency = <4 2 3>;
 169                         arm,data-latency = <4 2 3>;
 170                 };
 171
 172                 gpu: gpu@1800000 {
 173                         compatible = "vivante,gc";
 174                         reg = <0x01800000 0x4000>;
 175                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 176                         clocks = <&clks IMX6SX_CLK_GPU>,
 177                                  <&clks IMX6SX_CLK_GPU>,
 178                                  <&clks IMX6SX_CLK_GPU>;
 179                         clock-names = "bus", "core", "shader";
 180                 };
 181
 182                 dma_apbh: dma-apbh@1804000 {
 183                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 184                         reg = <0x01804000 0x2000>;
 185                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 188                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 189                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 190                         #dma-cells = <1>;
 191                         dma-channels = <4>;
 192                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 193                 };
 194
 195                 gpmi: gpmi-nand@1806000{
 196                         compatible = "fsl,imx6sx-gpmi-nand";
 197                         #address-cells = <1>;
 198                         #size-cells = <1>;
 199                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 200                         reg-names = "gpmi-nand", "bch";
 201                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 202                         interrupt-names = "bch";
 203                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 204                                  <&clks IMX6SX_CLK_GPMI_APB>,
 205                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 206                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 207                                  <&clks IMX6SX_CLK_PER1_BCH>;
 208                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 209                                       "gpmi_bch_apb", "per1_bch";
 210                         dmas = <&dma_apbh 0>;
 211                         dma-names = "rx-tx";
 212                         status = "disabled";
 213                 };
 214
 215                 aips1: aips-bus@2000000 {
 216                         compatible = "fsl,aips-bus", "simple-bus";
 217                         #address-cells = <1>;
 218                         #size-cells = <1>;
 219                         reg = <0x02000000 0x100000>;
 220                         ranges;
 221
 222                         spba-bus@2000000 {
 223                                 compatible = "fsl,spba-bus", "simple-bus";
 224                                 #address-cells = <1>;
 225                                 #size-cells = <1>;
 226                                 reg = <0x02000000 0x40000>;
 227                                 ranges;
 228
 229                                 spdif: spdif@2004000 {
 230                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 231                                         reg = <0x02004000 0x4000>;
 232                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 233                                         dmas = <&sdma 14 18 0>,
 234                                                <&sdma 15 18 0>;
 235                                         dma-names = "rx", "tx";
 236                                         clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
 237                                                  <&clks IMX6SX_CLK_OSC>,
 238                                                  <&clks IMX6SX_CLK_SPDIF>,
 239                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 240                                                  <&clks IMX6SX_CLK_IPG>,
 241                                                  <&clks 0>, <&clks 0>,
 242                                                  <&clks IMX6SX_CLK_SPBA>;
 243                                         clock-names = "core", "rxtx0",
 244                                                       "rxtx1", "rxtx2",
 245                                                       "rxtx3", "rxtx4",
 246                                                       "rxtx5", "rxtx6",
 247                                                       "rxtx7", "spba";
 248                                         status = "disabled";
 249                                 };
 250
 251                                 ecspi1: ecspi@2008000 {
 252                                         #address-cells = <1>;
 253                                         #size-cells = <0>;
 254                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 255                                         reg = <0x02008000 0x4000>;
 256                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 257                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 258                                                  <&clks IMX6SX_CLK_ECSPI1>;
 259                                         clock-names = "ipg", "per";
 260                                         status = "disabled";
 261                                 };
 262
 263                                 ecspi2: ecspi@200c000 {
 264                                         #address-cells = <1>;
 265                                         #size-cells = <0>;
 266                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 267                                         reg = <0x0200c000 0x4000>;
 268                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 269                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 270                                                  <&clks IMX6SX_CLK_ECSPI2>;
 271                                         clock-names = "ipg", "per";
 272                                         status = "disabled";
 273                                 };
 274
 275                                 ecspi3: ecspi@2010000 {
 276                                         #address-cells = <1>;
 277                                         #size-cells = <0>;
 278                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 279                                         reg = <0x02010000 0x4000>;
 280                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 281                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 282                                                  <&clks IMX6SX_CLK_ECSPI3>;
 283                                         clock-names = "ipg", "per";
 284                                         status = "disabled";
 285                                 };
 286
 287                                 ecspi4: ecspi@2014000 {
 288                                         #address-cells = <1>;
 289                                         #size-cells = <0>;
 290                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 291                                         reg = <0x02014000 0x4000>;
 292                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 293                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 294                                                  <&clks IMX6SX_CLK_ECSPI4>;
 295                                         clock-names = "ipg", "per";
 296                                         status = "disabled";
 297                                 };
 298
 299                                 uart1: serial@2020000 {
 300                                         compatible = "fsl,imx6sx-uart",
 301                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 302                                         reg = <0x02020000 0x4000>;
 303                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 304                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 305                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 306                                         clock-names = "ipg", "per";
 307                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 308                                         dma-names = "rx", "tx";
 309                                         status = "disabled";
 310                                 };
 311
 312                                 esai: esai@2024000 {
 313                                         reg = <0x02024000 0x4000>;
 314                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 315                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 316                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 317                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 318                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 319                                                  <&clks IMX6SX_CLK_SPBA>;
 320                                         clock-names = "core", "mem", "extal",
 321                                                       "fsys", "spba";
 322                                         status = "disabled";
 323                                 };
 324
 325                                 ssi1: ssi@2028000 {
 326                                         #sound-dai-cells = <0>;
 327                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 328                                         reg = <0x02028000 0x4000>;
 329                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 330                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 331                                                  <&clks IMX6SX_CLK_SSI1>;
 332                                         clock-names = "ipg", "baud";
 333                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 334                                         dma-names = "rx", "tx";
 335                                         fsl,fifo-depth = <15>;
 336                                         status = "disabled";
 337                                 };
 338
 339                                 ssi2: ssi@202c000 {
 340                                         #sound-dai-cells = <0>;
 341                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 342                                         reg = <0x0202c000 0x4000>;
 343                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 344                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 345                                                  <&clks IMX6SX_CLK_SSI2>;
 346                                         clock-names = "ipg", "baud";
 347                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 348                                         dma-names = "rx", "tx";
 349                                         fsl,fifo-depth = <15>;
 350                                         status = "disabled";
 351                                 };
 352
 353                                 ssi3: ssi@2030000 {
 354                                         #sound-dai-cells = <0>;
 355                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 356                                         reg = <0x02030000 0x4000>;
 357                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 358                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 359                                                  <&clks IMX6SX_CLK_SSI3>;
 360                                         clock-names = "ipg", "baud";
 361                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 362                                         dma-names = "rx", "tx";
 363                                         fsl,fifo-depth = <15>;
 364                                         status = "disabled";
 365                                 };
 366
 367                                 asrc: asrc@2034000 {
 368                                         reg = <0x02034000 0x4000>;
 369                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 370                                         clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
 371                                                  <&clks IMX6SX_CLK_ASRC_IPG>,
 372                                                  <&clks IMX6SX_CLK_SPDIF>,
 373                                                  <&clks IMX6SX_CLK_SPBA>;
 374                                         clock-names = "mem", "ipg", "asrck", "spba";
 375                                         dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
 376                                                <&sdma 19 20 1>, <&sdma 20 20 1>,
 377                                                <&sdma 21 20 1>, <&sdma 22 20 1>;
 378                                         dma-names = "rxa", "rxb", "rxc",
 379                                                     "txa", "txb", "txc";
 380                                         status = "okay";
 381                                 };
 382                         };
 383
 384                         pwm1: pwm@2080000 {
 385                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 386                                 reg = <0x02080000 0x4000>;
 387                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 388                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 389                                          <&clks IMX6SX_CLK_PWM1>;
 390                                 clock-names = "ipg", "per";
 391                                 #pwm-cells = <2>;
 392                         };
 393
 394                         pwm2: pwm@2084000 {
 395                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 396                                 reg = <0x02084000 0x4000>;
 397                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 398                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 399                                          <&clks IMX6SX_CLK_PWM2>;
 400                                 clock-names = "ipg", "per";
 401                                 #pwm-cells = <2>;
 402                         };
 403
 404                         pwm3: pwm@2088000 {
 405                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 406                                 reg = <0x02088000 0x4000>;
 407                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 408                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 409                                          <&clks IMX6SX_CLK_PWM3>;
 410                                 clock-names = "ipg", "per";
 411                                 #pwm-cells = <2>;
 412                         };
 413
 414                         pwm4: pwm@208c000 {
 415                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 416                                 reg = <0x0208c000 0x4000>;
 417                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 419                                          <&clks IMX6SX_CLK_PWM4>;
 420                                 clock-names = "ipg", "per";
 421                                 #pwm-cells = <2>;
 422                         };
 423
 424                         flexcan1: can@2090000 {
 425                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 426                                 reg = <0x02090000 0x4000>;
 427                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 428                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 429                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 430                                 clock-names = "ipg", "per";
 431                                 status = "disabled";
 432                         };
 433
 434                         flexcan2: can@2094000 {
 435                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 436                                 reg = <0x02094000 0x4000>;
 437                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 438                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 439                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 440                                 clock-names = "ipg", "per";
 441                                 status = "disabled";
 442                         };
 443
 444                         gpt: gpt@2098000 {
 445                                 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
 446                                 reg = <0x02098000 0x4000>;
 447                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 448                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 449                                          <&clks IMX6SX_CLK_GPT_3M>;
 450                                 clock-names = "ipg", "per";
 451                         };
 452
 453                         gpio1: gpio@209c000 {
 454                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 455                                 reg = <0x0209c000 0x4000>;
 456                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 457                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 458                                 gpio-controller;
 459                                 #gpio-cells = <2>;
 460                                 interrupt-controller;
 461                                 #interrupt-cells = <2>;
 462                                 gpio-ranges = <&iomuxc 0 5 26>;
 463                         };
 464
 465                         gpio2: gpio@20a0000 {
 466                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 467                                 reg = <0x020a0000 0x4000>;
 468                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 469                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 470                                 gpio-controller;
 471                                 #gpio-cells = <2>;
 472                                 interrupt-controller;
 473                                 #interrupt-cells = <2>;
 474                                 gpio-ranges = <&iomuxc 0 31 20>;
 475                         };
 476
 477                         gpio3: gpio@20a4000 {
 478                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 479                                 reg = <0x020a4000 0x4000>;
 480                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 481                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 482                                 gpio-controller;
 483                                 #gpio-cells = <2>;
 484                                 interrupt-controller;
 485                                 #interrupt-cells = <2>;
 486                                 gpio-ranges = <&iomuxc 0 51 29>;
 487                         };
 488
 489                         gpio4: gpio@20a8000 {
 490                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 491                                 reg = <0x020a8000 0x4000>;
 492                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 493                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 494                                 gpio-controller;
 495                                 #gpio-cells = <2>;
 496                                 interrupt-controller;
 497                                 #interrupt-cells = <2>;
 498                                 gpio-ranges = <&iomuxc 0 80 32>;
 499                         };
 500
 501                         gpio5: gpio@20ac000 {
 502                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 503                                 reg = <0x020ac000 0x4000>;
 504                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 505                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 506                                 gpio-controller;
 507                                 #gpio-cells = <2>;
 508                                 interrupt-controller;
 509                                 #interrupt-cells = <2>;
 510                                 gpio-ranges = <&iomuxc 0 112 24>;
 511                         };
 512
 513                         gpio6: gpio@20b0000 {
 514                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 515                                 reg = <0x020b0000 0x4000>;
 516                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 517                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 518                                 gpio-controller;
 519                                 #gpio-cells = <2>;
 520                                 interrupt-controller;
 521                                 #interrupt-cells = <2>;
 522                                 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
 523                         };
 524
 525                         gpio7: gpio@20b4000 {
 526                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 527                                 reg = <0x020b4000 0x4000>;
 528                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 529                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 530                                 gpio-controller;
 531                                 #gpio-cells = <2>;
 532                                 interrupt-controller;
 533                                 #interrupt-cells = <2>;
 534                                 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
 535                         };
 536
 537                         kpp: kpp@20b8000 {
 538                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 539                                 reg = <0x020b8000 0x4000>;
 540                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 541                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 542                                 status = "disabled";
 543                         };
 544
 545                         wdog1: wdog@20bc000 {
 546                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 547                                 reg = <0x020bc000 0x4000>;
 548                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 549                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 550                         };
 551
 552                         wdog2: wdog@20c0000 {
 553                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 554                                 reg = <0x020c0000 0x4000>;
 555                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 556                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 557                                 status = "disabled";
 558                         };
 559
 560                         clks: ccm@20c4000 {
 561                                 compatible = "fsl,imx6sx-ccm";
 562                                 reg = <0x020c4000 0x4000>;
 563                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 564                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 565                                 #clock-cells = <1>;
 566                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 567                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 568                         };
 569
 570                         anatop: anatop@20c8000 {
 571                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 572                                              "syscon", "simple-bus";
 573                                 reg = <0x020c8000 0x1000>;
 574                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 575                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 576                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 577
 578                                 regulator-1p1 {
 579                                         compatible = "fsl,anatop-regulator";
 580                                         regulator-name = "vdd1p1";
 581                                         regulator-min-microvolt = <800000>;
 582                                         regulator-max-microvolt = <1375000>;
 583                                         regulator-always-on;
 584                                         anatop-reg-offset = <0x110>;
 585                                         anatop-vol-bit-shift = <8>;
 586                                         anatop-vol-bit-width = <5>;
 587                                         anatop-min-bit-val = <4>;
 588                                         anatop-min-voltage = <800000>;
 589                                         anatop-max-voltage = <1375000>;
 590                                         anatop-enable-bit = <0>;
 591                                 };
 592
 593                                 regulator-3p0 {
 594                                         compatible = "fsl,anatop-regulator";
 595                                         regulator-name = "vdd3p0";
 596                                         regulator-min-microvolt = <2800000>;
 597                                         regulator-max-microvolt = <3150000>;
 598                                         regulator-always-on;
 599                                         anatop-reg-offset = <0x120>;
 600                                         anatop-vol-bit-shift = <8>;
 601                                         anatop-vol-bit-width = <5>;
 602                                         anatop-min-bit-val = <0>;
 603                                         anatop-min-voltage = <2625000>;
 604                                         anatop-max-voltage = <3400000>;
 605                                         anatop-enable-bit = <0>;
 606                                 };
 607
 608                                 regulator-2p5 {
 609                                         compatible = "fsl,anatop-regulator";
 610                                         regulator-name = "vdd2p5";
 611                                         regulator-min-microvolt = <2100000>;
 612                                         regulator-max-microvolt = <2875000>;
 613                                         regulator-always-on;
 614                                         anatop-reg-offset = <0x130>;
 615                                         anatop-vol-bit-shift = <8>;
 616                                         anatop-vol-bit-width = <5>;
 617                                         anatop-min-bit-val = <0>;
 618                                         anatop-min-voltage = <2100000>;
 619                                         anatop-max-voltage = <2875000>;
 620                                         anatop-enable-bit = <0>;
 621                                 };
 622
 623                                 reg_arm: regulator-vddcore {
 624                                         compatible = "fsl,anatop-regulator";
 625                                         regulator-name = "vddarm";
 626                                         regulator-min-microvolt = <725000>;
 627                                         regulator-max-microvolt = <1450000>;
 628                                         regulator-always-on;
 629                                         anatop-reg-offset = <0x140>;
 630                                         anatop-vol-bit-shift = <0>;
 631                                         anatop-vol-bit-width = <5>;
 632                                         anatop-delay-reg-offset = <0x170>;
 633                                         anatop-delay-bit-shift = <24>;
 634                                         anatop-delay-bit-width = <2>;
 635                                         anatop-min-bit-val = <1>;
 636                                         anatop-min-voltage = <725000>;
 637                                         anatop-max-voltage = <1450000>;
 638                                 };
 639
 640                                 reg_pcie: regulator-vddpcie {
 641                                         compatible = "fsl,anatop-regulator";
 642                                         regulator-name = "vddpcie";
 643                                         regulator-min-microvolt = <725000>;
 644                                         regulator-max-microvolt = <1450000>;
 645                                         anatop-reg-offset = <0x140>;
 646                                         anatop-vol-bit-shift = <9>;
 647                                         anatop-vol-bit-width = <5>;
 648                                         anatop-delay-reg-offset = <0x170>;
 649                                         anatop-delay-bit-shift = <26>;
 650                                         anatop-delay-bit-width = <2>;
 651                                         anatop-min-bit-val = <1>;
 652                                         anatop-min-voltage = <725000>;
 653                                         anatop-max-voltage = <1450000>;
 654                                 };
 655
 656                                 reg_soc: regulator-vddsoc {
 657                                         compatible = "fsl,anatop-regulator";
 658                                         regulator-name = "vddsoc";
 659                                         regulator-min-microvolt = <725000>;
 660                                         regulator-max-microvolt = <1450000>;
 661                                         regulator-always-on;
 662                                         anatop-reg-offset = <0x140>;
 663                                         anatop-vol-bit-shift = <18>;
 664                                         anatop-vol-bit-width = <5>;
 665                                         anatop-delay-reg-offset = <0x170>;
 666                                         anatop-delay-bit-shift = <28>;
 667                                         anatop-delay-bit-width = <2>;
 668                                         anatop-min-bit-val = <1>;
 669                                         anatop-min-voltage = <725000>;
 670                                         anatop-max-voltage = <1450000>;
 671                                 };
 672                         };
 673
 674                         tempmon: tempmon {
 675                                 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
 676                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 677                                 fsl,tempmon = <&anatop>;
 678                                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 679                                 nvmem-cell-names = "calib", "temp_grade";
 680                                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 681                         };
 682
 683                         usbphy1: usbphy@20c9000 {
 684                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 685                                 reg = <0x020c9000 0x1000>;
 686                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 687                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 688                                 fsl,anatop = <&anatop>;
 689                         };
 690
 691                         usbphy2: usbphy@20ca000 {
 692                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 693                                 reg = <0x020ca000 0x1000>;
 694                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 695                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 696                                 fsl,anatop = <&anatop>;
 697                         };
 698
 699                         snvs: snvs@20cc000 {
 700                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 701                                 reg = <0x020cc000 0x4000>;
 702
 703                                 snvs_rtc: snvs-rtc-lp {
 704                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 705                                         regmap = <&snvs>;
 706                                         offset = <0x34>;
 707                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 708                                 };
 709
 710                                 snvs_poweroff: snvs-poweroff {
 711                                         compatible = "syscon-poweroff";
 712                                         regmap = <&snvs>;
 713                                         offset = <0x38>;
 714                                         value = <0x60>;
 715                                         mask = <0x60>;
 716                                         status = "disabled";
 717                                 };
 718
 719                                 snvs_pwrkey: snvs-powerkey {
 720                                         compatible = "fsl,sec-v4.0-pwrkey";
 721                                         regmap = <&snvs>;
 722                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 723                                         linux,keycode = <KEY_POWER>;
 724                                         wakeup-source;
 725                                 };
 726                         };
 727
 728                         epit1: epit@20d0000 {
 729                                 reg = <0x020d0000 0x4000>;
 730                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 731                         };
 732
 733                         epit2: epit@20d4000 {
 734                                 reg = <0x020d4000 0x4000>;
 735                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 736                         };
 737
 738                         src: src@20d8000 {
 739                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 740                                 reg = <0x020d8000 0x4000>;
 741                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 742                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 743                                 #reset-cells = <1>;
 744                         };
 745
 746                         gpc: gpc@20dc000 {
 747                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 748                                 reg = <0x020dc000 0x4000>;
 749                                 interrupt-controller;
 750                                 #interrupt-cells = <3>;
 751                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 752                                 interrupt-parent = <&intc>;
 753                         };
 754
 755                         iomuxc: iomuxc@20e0000 {
 756                                 compatible = "fsl,imx6sx-iomuxc";
 757                                 reg = <0x020e0000 0x4000>;
 758                         };
 759
 760                         gpr: iomuxc-gpr@20e4000 {
 761                                 compatible = "fsl,imx6sx-iomuxc-gpr",
 762                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 763                                 reg = <0x020e4000 0x4000>;
 764                         };
 765
 766                         sdma: sdma@20ec000 {
 767                                 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
 768                                 reg = <0x020ec000 0x4000>;
 769                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 770                                 clocks = <&clks IMX6SX_CLK_SDMA>,
 771                                          <&clks IMX6SX_CLK_SDMA>;
 772                                 clock-names = "ipg", "ahb";
 773                                 #dma-cells = <3>;
 774                                 /* imx6sx reuses imx6q sdma firmware */
 775                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 776                         };
 777                 };
 778
 779                 aips2: aips-bus@2100000 {
 780                         compatible = "fsl,aips-bus", "simple-bus";
 781                         #address-cells = <1>;
 782                         #size-cells = <1>;
 783                         reg = <0x02100000 0x100000>;
 784                         ranges;
 785
 786                         crypto: caam@2100000 {
 787                                 compatible = "fsl,sec-v4.0";
 788                                 fsl,sec-era = <4>;
 789                                 #address-cells = <1>;
 790                                 #size-cells = <1>;
 791                                 reg = <0x2100000 0x10000>;
 792                                 ranges = <0 0x2100000 0x10000>;
 793                                 interrupt-parent = <&intc>;
 794                                 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
 795                                          <&clks IMX6SX_CLK_CAAM_ACLK>,
 796                                          <&clks IMX6SX_CLK_CAAM_IPG>,
 797                                          <&clks IMX6SX_CLK_EIM_SLOW>;
 798                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
 799
 800                                 sec_jr0: jr0@1000 {
 801                                         compatible = "fsl,sec-v4.0-job-ring";
 802                                         reg = <0x1000 0x1000>;
 803                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 804                                 };
 805
 806                                 sec_jr1: jr1@2000 {
 807                                         compatible = "fsl,sec-v4.0-job-ring";
 808                                         reg = <0x2000 0x1000>;
 809                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 810                                 };
 811                         };
 812
 813                         usbotg1: usb@2184000 {
 814                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 815                                 reg = <0x02184000 0x200>;
 816                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 817                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 818                                 fsl,usbphy = <&usbphy1>;
 819                                 fsl,usbmisc = <&usbmisc 0>;
 820                                 fsl,anatop = <&anatop>;
 821                                 ahb-burst-config = <0x0>;
 822                                 tx-burst-size-dword = <0x10>;
 823                                 rx-burst-size-dword = <0x10>;
 824                                 status = "disabled";
 825                         };
 826
 827                         usbotg2: usb@2184200 {
 828                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 829                                 reg = <0x02184200 0x200>;
 830                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 831                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 832                                 fsl,usbphy = <&usbphy2>;
 833                                 fsl,usbmisc = <&usbmisc 1>;
 834                                 ahb-burst-config = <0x0>;
 835                                 tx-burst-size-dword = <0x10>;
 836                                 rx-burst-size-dword = <0x10>;
 837                                 status = "disabled";
 838                         };
 839
 840                         usbh: usb@2184400 {
 841                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 842                                 reg = <0x02184400 0x200>;
 843                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 844                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 845                                 fsl,usbmisc = <&usbmisc 2>;
 846                                 phy_type = "hsic";
 847                                 fsl,anatop = <&anatop>;
 848                                 dr_mode = "host";
 849                                 ahb-burst-config = <0x0>;
 850                                 tx-burst-size-dword = <0x10>;
 851                                 rx-burst-size-dword = <0x10>;
 852                                 status = "disabled";
 853                         };
 854
 855                         usbmisc: usbmisc@2184800 {
 856                                 #index-cells = <1>;
 857                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
 858                                 reg = <0x02184800 0x200>;
 859                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 860                         };
 861
 862                         fec1: ethernet@2188000 {
 863                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 864                                 reg = <0x02188000 0x4000>;
 865                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 866                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 867                                 clocks = <&clks IMX6SX_CLK_ENET>,
 868                                          <&clks IMX6SX_CLK_ENET_AHB>,
 869                                          <&clks IMX6SX_CLK_ENET_PTP>,
 870                                          <&clks IMX6SX_CLK_ENET_REF>,
 871                                          <&clks IMX6SX_CLK_ENET_PTP>;
 872                                 clock-names = "ipg", "ahb", "ptp",
 873                                               "enet_clk_ref", "enet_out";
 874                                 fsl,num-tx-queues=<3>;
 875                                 fsl,num-rx-queues=<3>;
 876                                 status = "disabled";
 877                         };
 878
 879                         mlb: mlb@218c000 {
 880                                 reg = <0x0218c000 0x4000>;
 881                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 882                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 883                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 884                                 clocks = <&clks IMX6SX_CLK_MLB>;
 885                                 status = "disabled";
 886                         };
 887
 888                         usdhc1: usdhc@2190000 {
 889                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 890                                 reg = <0x02190000 0x4000>;
 891                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 892                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 893                                          <&clks IMX6SX_CLK_USDHC1>,
 894                                          <&clks IMX6SX_CLK_USDHC1>;
 895                                 clock-names = "ipg", "ahb", "per";
 896                                 bus-width = <4>;
 897                                 status = "disabled";
 898                         };
 899
 900                         usdhc2: usdhc@2194000 {
 901                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 902                                 reg = <0x02194000 0x4000>;
 903                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 904                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 905                                          <&clks IMX6SX_CLK_USDHC2>,
 906                                          <&clks IMX6SX_CLK_USDHC2>;
 907                                 clock-names = "ipg", "ahb", "per";
 908                                 bus-width = <4>;
 909                                 status = "disabled";
 910                         };
 911
 912                         usdhc3: usdhc@2198000 {
 913                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 914                                 reg = <0x02198000 0x4000>;
 915                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 916                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
 917                                          <&clks IMX6SX_CLK_USDHC3>,
 918                                          <&clks IMX6SX_CLK_USDHC3>;
 919                                 clock-names = "ipg", "ahb", "per";
 920                                 bus-width = <4>;
 921                                 status = "disabled";
 922                         };
 923
 924                         usdhc4: usdhc@219c000 {
 925                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 926                                 reg = <0x0219c000 0x4000>;
 927                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 928                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
 929                                          <&clks IMX6SX_CLK_USDHC4>,
 930                                          <&clks IMX6SX_CLK_USDHC4>;
 931                                 clock-names = "ipg", "ahb", "per";
 932                                 bus-width = <4>;
 933                                 status = "disabled";
 934                         };
 935
 936                         i2c1: i2c@21a0000 {
 937                                 #address-cells = <1>;
 938                                 #size-cells = <0>;
 939                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 940                                 reg = <0x021a0000 0x4000>;
 941                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 942                                 clocks = <&clks IMX6SX_CLK_I2C1>;
 943                                 status = "disabled";
 944                         };
 945
 946                         i2c2: i2c@21a4000 {
 947                                 #address-cells = <1>;
 948                                 #size-cells = <0>;
 949                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 950                                 reg = <0x021a4000 0x4000>;
 951                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 952                                 clocks = <&clks IMX6SX_CLK_I2C2>;
 953                                 status = "disabled";
 954                         };
 955
 956                         i2c3: i2c@21a8000 {
 957                                 #address-cells = <1>;
 958                                 #size-cells = <0>;
 959                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 960                                 reg = <0x021a8000 0x4000>;
 961                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 962                                 clocks = <&clks IMX6SX_CLK_I2C3>;
 963                                 status = "disabled";
 964                         };
 965
 966                         mmdc: mmdc@21b0000 {
 967                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
 968                                 reg = <0x021b0000 0x4000>;
 969                         };
 970
 971                         fec2: ethernet@21b4000 {
 972                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 973                                 reg = <0x021b4000 0x4000>;
 974                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 975                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 976                                 clocks = <&clks IMX6SX_CLK_ENET>,
 977                                          <&clks IMX6SX_CLK_ENET_AHB>,
 978                                          <&clks IMX6SX_CLK_ENET_PTP>,
 979                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
 980                                          <&clks IMX6SX_CLK_ENET_PTP>;
 981                                 clock-names = "ipg", "ahb", "ptp",
 982                                               "enet_clk_ref", "enet_out";
 983                                 status = "disabled";
 984                         };
 985
 986                         weim: weim@21b8000 {
 987                                 #address-cells = <2>;
 988                                 #size-cells = <1>;
 989                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
 990                                 reg = <0x021b8000 0x4000>;
 991                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 992                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
 993                                 fsl,weim-cs-gpr = <&gpr>;
 994                                 status = "disabled";
 995                         };
 996
 997                         ocotp: ocotp@21bc000 {
 998                                 #address-cells = <1>;
 999                                 #size-cells = <1>;
1000                                 compatible = "fsl,imx6sx-ocotp", "syscon";
1001                                 reg = <0x021bc000 0x4000>;
1002                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1003
1004                                 tempmon_calib: calib@38 {
1005                                         reg = <0x38 4>;
1006                                 };
1007
1008                                 tempmon_temp_grade: temp-grade@20 {
1009                                         reg = <0x20 4>;
1010                                 };
1011                         };
1012
1013                         sai1: sai@21d4000 {
1014                                 compatible = "fsl,imx6sx-sai";
1015                                 reg = <0x021d4000 0x4000>;
1016                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1017                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1018                                          <&clks IMX6SX_CLK_SAI1>,
1019                                          <&clks 0>, <&clks 0>;
1020                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1021                                 dma-names = "rx", "tx";
1022                                 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1023                                 status = "disabled";
1024                         };
1025
1026                         audmux: audmux@21d8000 {
1027                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1028                                 reg = <0x021d8000 0x4000>;
1029                                 status = "disabled";
1030                         };
1031
1032                         sai2: sai@21dc000 {
1033                                 compatible = "fsl,imx6sx-sai";
1034                                 reg = <0x021dc000 0x4000>;
1035                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1036                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1037                                          <&clks IMX6SX_CLK_SAI2>,
1038                                          <&clks 0>, <&clks 0>;
1039                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1040                                 dma-names = "rx", "tx";
1041                                 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1042                                 status = "disabled";
1043                         };
1044
1045                         qspi1: qspi@21e0000 {
1046                                 #address-cells = <1>;
1047                                 #size-cells = <0>;
1048                                 compatible = "fsl,imx6sx-qspi";
1049                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1050                                 reg-names = "QuadSPI", "QuadSPI-memory";
1051                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1052                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1053                                          <&clks IMX6SX_CLK_QSPI1>;
1054                                 clock-names = "qspi_en", "qspi";
1055                                 status = "disabled";
1056                         };
1057
1058                         qspi2: qspi@21e4000 {
1059                                 #address-cells = <1>;
1060                                 #size-cells = <0>;
1061                                 compatible = "fsl,imx6sx-qspi";
1062                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1063                                 reg-names = "QuadSPI", "QuadSPI-memory";
1064                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1065                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1066                                          <&clks IMX6SX_CLK_QSPI2>;
1067                                 clock-names = "qspi_en", "qspi";
1068                                 status = "disabled";
1069                         };
1070
1071                         uart2: serial@21e8000 {
1072                                 compatible = "fsl,imx6sx-uart",
1073                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1074                                 reg = <0x021e8000 0x4000>;
1075                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1076                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1077                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1078                                 clock-names = "ipg", "per";
1079                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1080                                 dma-names = "rx", "tx";
1081                                 status = "disabled";
1082                         };
1083
1084                         uart3: serial@21ec000 {
1085                                 compatible = "fsl,imx6sx-uart",
1086                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1087                                 reg = <0x021ec000 0x4000>;
1088                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1089                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1090                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1091                                 clock-names = "ipg", "per";
1092                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1093                                 dma-names = "rx", "tx";
1094                                 status = "disabled";
1095                         };
1096
1097                         uart4: serial@21f0000 {
1098                                 compatible = "fsl,imx6sx-uart",
1099                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1100                                 reg = <0x021f0000 0x4000>;
1101                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1102                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1103                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1104                                 clock-names = "ipg", "per";
1105                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1106                                 dma-names = "rx", "tx";
1107                                 status = "disabled";
1108                         };
1109
1110                         uart5: serial@21f4000 {
1111                                 compatible = "fsl,imx6sx-uart",
1112                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1113                                 reg = <0x021f4000 0x4000>;
1114                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1115                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1116                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1117                                 clock-names = "ipg", "per";
1118                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1119                                 dma-names = "rx", "tx";
1120                                 status = "disabled";
1121                         };
1122
1123                         i2c4: i2c@21f8000 {
1124                                 #address-cells = <1>;
1125                                 #size-cells = <0>;
1126                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1127                                 reg = <0x021f8000 0x4000>;
1128                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1129                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1130                                 status = "disabled";
1131                         };
1132                 };
1133
1134                 aips3: aips-bus@2200000 {
1135                         compatible = "fsl,aips-bus", "simple-bus";
1136                         #address-cells = <1>;
1137                         #size-cells = <1>;
1138                         reg = <0x02200000 0x100000>;
1139                         ranges;
1140
1141                         spba-bus@2200000 {
1142                                 compatible = "fsl,spba-bus", "simple-bus";
1143                                 #address-cells = <1>;
1144                                 #size-cells = <1>;
1145                                 reg = <0x02240000 0x40000>;
1146                                 ranges;
1147
1148                                 csi1: csi@2214000 {
1149                                         reg = <0x02214000 0x4000>;
1150                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1151                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1152                                                  <&clks IMX6SX_CLK_CSI>,
1153                                                  <&clks IMX6SX_CLK_DCIC1>;
1154                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1155                                         status = "disabled";
1156                                 };
1157
1158                                 pxp: pxp@2218000 {
1159                                         reg = <0x02218000 0x4000>;
1160                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1161                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1162                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1163                                         clock-names = "pxp-axi", "disp-axi";
1164                                         status = "disabled";
1165                                 };
1166
1167                                 csi2: csi@221c000 {
1168                                         reg = <0x0221c000 0x4000>;
1169                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1170                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1171                                                  <&clks IMX6SX_CLK_CSI>,
1172                                                  <&clks IMX6SX_CLK_DCIC2>;
1173                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1174                                         status = "disabled";
1175                                 };
1176
1177                                 lcdif1: lcdif@2220000 {
1178                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1179                                         reg = <0x02220000 0x4000>;
1180                                         interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1181                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1182                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1183                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1184                                         clock-names = "pix", "axi", "disp_axi";
1185                                         status = "disabled";
1186                                 };
1187
1188                                 lcdif2: lcdif@2224000 {
1189                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1190                                         reg = <0x02224000 0x4000>;
1191                                         interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1192                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1193                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1194                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1195                                         clock-names = "pix", "axi", "disp_axi";
1196                                         status = "disabled";
1197                                 };
1198
1199                                 vadc: vadc@2228000 {
1200                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1201                                         reg-names = "vadc-vafe", "vadc-vdec";
1202                                         clocks = <&clks IMX6SX_CLK_VADC>,
1203                                                  <&clks IMX6SX_CLK_CSI>;
1204                                         clock-names = "vadc", "csi";
1205                                         status = "disabled";
1206                                 };
1207                         };
1208
1209                         adc1: adc@2280000 {
1210                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1211                                 reg = <0x02280000 0x4000>;
1212                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1213                                 clocks = <&clks IMX6SX_CLK_IPG>;
1214                                 clock-names = "adc";
1215                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1216                                                          <20000000>;
1217                                 status = "disabled";
1218                         };
1219
1220                         adc2: adc@2284000 {
1221                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1222                                 reg = <0x02284000 0x4000>;
1223                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1224                                 clocks = <&clks IMX6SX_CLK_IPG>;
1225                                 clock-names = "adc";
1226                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1227                                                          <20000000>;
1228                                 status = "disabled";
1229                         };
1230
1231                         wdog3: wdog@2288000 {
1232                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1233                                 reg = <0x02288000 0x4000>;
1234                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1235                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1236                                 status = "disabled";
1237                         };
1238
1239                         ecspi5: ecspi@228c000 {
1240                                 #address-cells = <1>;
1241                                 #size-cells = <0>;
1242                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1243                                 reg = <0x0228c000 0x4000>;
1244                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1245                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1246                                          <&clks IMX6SX_CLK_ECSPI5>;
1247                                 clock-names = "ipg", "per";
1248                                 status = "disabled";
1249                         };
1250
1251                         uart6: serial@22a0000 {
1252                                 compatible = "fsl,imx6sx-uart",
1253                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1254                                 reg = <0x022a0000 0x4000>;
1255                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1256                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1257                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1258                                 clock-names = "ipg", "per";
1259                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1260                                 dma-names = "rx", "tx";
1261                                 status = "disabled";
1262                         };
1263
1264                         pwm5: pwm@22a4000 {
1265                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1266                                 reg = <0x022a4000 0x4000>;
1267                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1268                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1269                                          <&clks IMX6SX_CLK_PWM5>;
1270                                 clock-names = "ipg", "per";
1271                                 #pwm-cells = <2>;
1272                         };
1273
1274                         pwm6: pwm@22a8000 {
1275                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1276                                 reg = <0x022a8000 0x4000>;
1277                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1278                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1279                                          <&clks IMX6SX_CLK_PWM6>;
1280                                 clock-names = "ipg", "per";
1281                                 #pwm-cells = <2>;
1282                         };
1283
1284                         pwm7: pwm@22ac000 {
1285                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1286                                 reg = <0x022ac000 0x4000>;
1287                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1288                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1289                                          <&clks IMX6SX_CLK_PWM7>;
1290                                 clock-names = "ipg", "per";
1291                                 #pwm-cells = <2>;
1292                         };
1293
1294                         pwm8: pwm@22b0000 {
1295                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1296                                 reg = <0x0022b0000 0x4000>;
1297                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1298                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1299                                          <&clks IMX6SX_CLK_PWM8>;
1300                                 clock-names = "ipg", "per";
1301                                 #pwm-cells = <2>;
1302                         };
1303                 };
1304
1305                 pcie: pcie@8ffc000 {
1306                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1307                         reg = <0x08ffc000 0x4000>; /* DBI */
1308                         #address-cells = <3>;
1309                         #size-cells = <2>;
1310                         device_type = "pci";
1311                                   /* configuration space */
1312                         ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1313                                   /* downstream I/O */
1314                                   0x81000000 0 0          0x08f80000 0 0x00010000
1315                                   /* non-prefetchable memory */
1316                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1317                         bus-range = <0x00 0xff>;
1318                         num-lanes = <1>;
1319                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1320                         clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1321                                  <&clks IMX6SX_CLK_PCIE_AXI>,
1322                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1323                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1324                         clock-names = "pcie_ref_125m", "pcie_axi",
1325                                       "lvds_gate", "display_axi";
1326                         status = "disabled";
1327                 };
1328         };
1329
1330         gpu-subsystem {
1331                 compatible = "fsl,imx-gpu-subsystem";
1332                 cores = <&gpu>;
1333         };
1334 };