arch/arm/boot/dts/imx6sx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2014 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/clock/imx6sx-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include "imx6sx-pinfunc.h"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         /*
  15          * The decompressor and also some bootloaders rely on a
  16          * pre-existing /chosen node to be available to insert the
  17          * command line and merge other ATAGS info.
  18          * Also for U-Boot there must be a pre-existing /memory node.
  19          */
  20         chosen {};
  21         memory { device_type = "memory"; };
  22
  23         aliases {
  24                 can0 = &flexcan1;
  25                 can1 = &flexcan2;
  26                 ethernet0 = &fec1;
  27                 ethernet1 = &fec2;
  28                 gpio0 = &gpio1;
  29                 gpio1 = &gpio2;
  30                 gpio2 = &gpio3;
  31                 gpio3 = &gpio4;
  32                 gpio4 = &gpio5;
  33                 gpio5 = &gpio6;
  34                 gpio6 = &gpio7;
  35                 i2c0 = &i2c1;
  36                 i2c1 = &i2c2;
  37                 i2c2 = &i2c3;
  38                 i2c3 = &i2c4;
  39                 mmc0 = &usdhc1;
  40                 mmc1 = &usdhc2;
  41                 mmc2 = &usdhc3;
  42                 mmc3 = &usdhc4;
  43                 serial0 = &uart1;
  44                 serial1 = &uart2;
  45                 serial2 = &uart3;
  46                 serial3 = &uart4;
  47                 serial4 = &uart5;
  48                 serial5 = &uart6;
  49                 spi0 = &ecspi1;
  50                 spi1 = &ecspi2;
  51                 spi2 = &ecspi3;
  52                 spi3 = &ecspi4;
  53                 spi4 = &ecspi5;
  54                 usbphy0 = &usbphy1;
  55                 usbphy1 = &usbphy2;
  56         };
  57
  58         cpus {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 cpu0: cpu@0 {
  63                         compatible = "arm,cortex-a9";
  64                         device_type = "cpu";
  65                         reg = <0>;
  66                         next-level-cache = <&L2>;
  67                         operating-points = <
  68                                 /* kHz    uV */
  69                                 996000  1250000
  70                                 792000  1175000
  71                                 396000  1075000
  72                                 198000  975000
  73                         >;
  74                         fsl,soc-operating-points = <
  75                                 /* ARM kHz  SOC uV */
  76                                 996000      1175000
  77                                 792000      1175000
  78                                 396000      1175000
  79                                 198000      1175000
  80                         >;
  81                         clock-latency = <61036>; /* two CLK32 periods */
  82                         clocks = <&clks IMX6SX_CLK_ARM>,
  83                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  84                                  <&clks IMX6SX_CLK_STEP>,
  85                                  <&clks IMX6SX_CLK_PLL1_SW>,
  86                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  87                         clock-names = "arm", "pll2_pfd2_396m", "step",
  88                                       "pll1_sw", "pll1_sys";
  89                         arm-supply = <&reg_arm>;
  90                         soc-supply = <&reg_soc>;
  91                 };
  92         };
  93
  94         intc: interrupt-controller@a01000 {
  95                 compatible = "arm,cortex-a9-gic";
  96                 #interrupt-cells = <3>;
  97                 interrupt-controller;
  98                 reg = <0x00a01000 0x1000>,
  99                       <0x00a00100 0x100>;
 100                 interrupt-parent = <&intc>;
 101         };
 102
 103         ckil: clock-ckil {
 104                 compatible = "fixed-clock";
 105                 #clock-cells = <0>;
 106                 clock-frequency = <32768>;
 107                 clock-output-names = "ckil";
 108         };
 109
 110         osc: clock-osc {
 111                 compatible = "fixed-clock";
 112                 #clock-cells = <0>;
 113                 clock-frequency = <24000000>;
 114                 clock-output-names = "osc";
 115         };
 116
 117         ipp_di0: clock-ipp-di0 {
 118                 compatible = "fixed-clock";
 119                 #clock-cells = <0>;
 120                 clock-frequency = <0>;
 121                 clock-output-names = "ipp_di0";
 122         };
 123
 124         ipp_di1: clock-ipp-di1 {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <0>;
 128                 clock-output-names = "ipp_di1";
 129         };
 130
 131         anaclk1: clock-anaclk1 {
 132                 compatible = "fixed-clock";
 133                 #clock-cells = <0>;
 134                 clock-frequency = <0>;
 135                 clock-output-names = "anaclk1";
 136         };
 137
 138         anaclk2: clock-anaclk2 {
 139                 compatible = "fixed-clock";
 140                 #clock-cells = <0>;
 141                 clock-frequency = <0>;
 142                 clock-output-names = "anaclk2";
 143         };
 144
 145         tempmon: tempmon {
 146                 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
 147                 interrupt-parent = <&gpc>;
 148                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 149                 fsl,tempmon = <&anatop>;
 150                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 151                 nvmem-cell-names = "calib", "temp_grade";
 152                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 153         };
 154
 155         pmu {
 156                 compatible = "arm,cortex-a9-pmu";
 157                 interrupt-parent = <&gpc>;
 158                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 159         };
 160
 161         soc {
 162                 #address-cells = <1>;
 163                 #size-cells = <1>;
 164                 compatible = "simple-bus";
 165                 interrupt-parent = <&gpc>;
 166                 ranges;
 167
 168                 ocram: sram@900000 {
 169                         compatible = "mmio-sram";
 170                         reg = <0x00900000 0x20000>;
 171                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 172                 };
 173
 174                 L2: l2-cache@a02000 {
 175                         compatible = "arm,pl310-cache";
 176                         reg = <0x00a02000 0x1000>;
 177                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 178                         cache-unified;
 179                         cache-level = <2>;
 180                         arm,tag-latency = <4 2 3>;
 181                         arm,data-latency = <4 2 3>;
 182                 };
 183
 184                 gpu: gpu@1800000 {
 185                         compatible = "vivante,gc";
 186                         reg = <0x01800000 0x4000>;
 187                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 188                         clocks = <&clks IMX6SX_CLK_GPU>,
 189                                  <&clks IMX6SX_CLK_GPU>,
 190                                  <&clks IMX6SX_CLK_GPU>;
 191                         clock-names = "bus", "core", "shader";
 192                         power-domains = <&pd_pu>;
 193                 };
 194
 195                 dma_apbh: dma-apbh@1804000 {
 196                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 197                         reg = <0x01804000 0x2000>;
 198                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 202                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 203                         #dma-cells = <1>;
 204                         dma-channels = <4>;
 205                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 206                 };
 207
 208                 gpmi: gpmi-nand@1806000{
 209                         compatible = "fsl,imx6sx-gpmi-nand";
 210                         #address-cells = <1>;
 211                         #size-cells = <1>;
 212                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 213                         reg-names = "gpmi-nand", "bch";
 214                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 215                         interrupt-names = "bch";
 216                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 217                                  <&clks IMX6SX_CLK_GPMI_APB>,
 218                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 219                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 220                                  <&clks IMX6SX_CLK_PER1_BCH>;
 221                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 222                                       "gpmi_bch_apb", "per1_bch";
 223                         dmas = <&dma_apbh 0>;
 224                         dma-names = "rx-tx";
 225                         status = "disabled";
 226                 };
 227
 228                 aips1: aips-bus@2000000 {
 229                         compatible = "fsl,aips-bus", "simple-bus";
 230                         #address-cells = <1>;
 231                         #size-cells = <1>;
 232                         reg = <0x02000000 0x100000>;
 233                         ranges;
 234
 235                         spba-bus@2000000 {
 236                                 compatible = "fsl,spba-bus", "simple-bus";
 237                                 #address-cells = <1>;
 238                                 #size-cells = <1>;
 239                                 reg = <0x02000000 0x40000>;
 240                                 ranges;
 241
 242                                 spdif: spdif@2004000 {
 243                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 244                                         reg = <0x02004000 0x4000>;
 245                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 246                                         dmas = <&sdma 14 18 0>,
 247                                                <&sdma 15 18 0>;
 248                                         dma-names = "rx", "tx";
 249                                         clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
 250                                                  <&clks IMX6SX_CLK_OSC>,
 251                                                  <&clks IMX6SX_CLK_SPDIF>,
 252                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 253                                                  <&clks IMX6SX_CLK_IPG>,
 254                                                  <&clks 0>, <&clks 0>,
 255                                                  <&clks IMX6SX_CLK_SPBA>;
 256                                         clock-names = "core", "rxtx0",
 257                                                       "rxtx1", "rxtx2",
 258                                                       "rxtx3", "rxtx4",
 259                                                       "rxtx5", "rxtx6",
 260                                                       "rxtx7", "spba";
 261                                         status = "disabled";
 262                                 };
 263
 264                                 ecspi1: ecspi@2008000 {
 265                                         #address-cells = <1>;
 266                                         #size-cells = <0>;
 267                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 268                                         reg = <0x02008000 0x4000>;
 269                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 270                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 271                                                  <&clks IMX6SX_CLK_ECSPI1>;
 272                                         clock-names = "ipg", "per";
 273                                         status = "disabled";
 274                                 };
 275
 276                                 ecspi2: ecspi@200c000 {
 277                                         #address-cells = <1>;
 278                                         #size-cells = <0>;
 279                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 280                                         reg = <0x0200c000 0x4000>;
 281                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 282                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 283                                                  <&clks IMX6SX_CLK_ECSPI2>;
 284                                         clock-names = "ipg", "per";
 285                                         status = "disabled";
 286                                 };
 287
 288                                 ecspi3: ecspi@2010000 {
 289                                         #address-cells = <1>;
 290                                         #size-cells = <0>;
 291                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 292                                         reg = <0x02010000 0x4000>;
 293                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 294                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 295                                                  <&clks IMX6SX_CLK_ECSPI3>;
 296                                         clock-names = "ipg", "per";
 297                                         status = "disabled";
 298                                 };
 299
 300                                 ecspi4: ecspi@2014000 {
 301                                         #address-cells = <1>;
 302                                         #size-cells = <0>;
 303                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 304                                         reg = <0x02014000 0x4000>;
 305                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 306                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 307                                                  <&clks IMX6SX_CLK_ECSPI4>;
 308                                         clock-names = "ipg", "per";
 309                                         status = "disabled";
 310                                 };
 311
 312                                 uart1: serial@2020000 {
 313                                         compatible = "fsl,imx6sx-uart",
 314                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 315                                         reg = <0x02020000 0x4000>;
 316                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 317                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 318                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 319                                         clock-names = "ipg", "per";
 320                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 321                                         dma-names = "rx", "tx";
 322                                         status = "disabled";
 323                                 };
 324
 325                                 esai: esai@2024000 {
 326                                         reg = <0x02024000 0x4000>;
 327                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 328                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 329                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 330                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 331                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 332                                                  <&clks IMX6SX_CLK_SPBA>;
 333                                         clock-names = "core", "mem", "extal",
 334                                                       "fsys", "spba";
 335                                         status = "disabled";
 336                                 };
 337
 338                                 ssi1: ssi@2028000 {
 339                                         #sound-dai-cells = <0>;
 340                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 341                                         reg = <0x02028000 0x4000>;
 342                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 343                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 344                                                  <&clks IMX6SX_CLK_SSI1>;
 345                                         clock-names = "ipg", "baud";
 346                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 347                                         dma-names = "rx", "tx";
 348                                         fsl,fifo-depth = <15>;
 349                                         status = "disabled";
 350                                 };
 351
 352                                 ssi2: ssi@202c000 {
 353                                         #sound-dai-cells = <0>;
 354                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 355                                         reg = <0x0202c000 0x4000>;
 356                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 357                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 358                                                  <&clks IMX6SX_CLK_SSI2>;
 359                                         clock-names = "ipg", "baud";
 360                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 361                                         dma-names = "rx", "tx";
 362                                         fsl,fifo-depth = <15>;
 363                                         status = "disabled";
 364                                 };
 365
 366                                 ssi3: ssi@2030000 {
 367                                         #sound-dai-cells = <0>;
 368                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 369                                         reg = <0x02030000 0x4000>;
 370                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 371                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 372                                                  <&clks IMX6SX_CLK_SSI3>;
 373                                         clock-names = "ipg", "baud";
 374                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 375                                         dma-names = "rx", "tx";
 376                                         fsl,fifo-depth = <15>;
 377                                         status = "disabled";
 378                                 };
 379
 380                                 asrc: asrc@2034000 {
 381                                         reg = <0x02034000 0x4000>;
 382                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 383                                         clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
 384                                                  <&clks IMX6SX_CLK_ASRC_IPG>,
 385                                                  <&clks IMX6SX_CLK_SPDIF>,
 386                                                  <&clks IMX6SX_CLK_SPBA>;
 387                                         clock-names = "mem", "ipg", "asrck", "spba";
 388                                         dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
 389                                                <&sdma 19 20 1>, <&sdma 20 20 1>,
 390                                                <&sdma 21 20 1>, <&sdma 22 20 1>;
 391                                         dma-names = "rxa", "rxb", "rxc",
 392                                                     "txa", "txb", "txc";
 393                                         status = "okay";
 394                                 };
 395                         };
 396
 397                         pwm1: pwm@2080000 {
 398                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 399                                 reg = <0x02080000 0x4000>;
 400                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 401                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 402                                          <&clks IMX6SX_CLK_PWM1>;
 403                                 clock-names = "ipg", "per";
 404                                 #pwm-cells = <2>;
 405                         };
 406
 407                         pwm2: pwm@2084000 {
 408                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 409                                 reg = <0x02084000 0x4000>;
 410                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 411                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 412                                          <&clks IMX6SX_CLK_PWM2>;
 413                                 clock-names = "ipg", "per";
 414                                 #pwm-cells = <2>;
 415                         };
 416
 417                         pwm3: pwm@2088000 {
 418                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 419                                 reg = <0x02088000 0x4000>;
 420                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 421                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 422                                          <&clks IMX6SX_CLK_PWM3>;
 423                                 clock-names = "ipg", "per";
 424                                 #pwm-cells = <2>;
 425                         };
 426
 427                         pwm4: pwm@208c000 {
 428                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 429                                 reg = <0x0208c000 0x4000>;
 430                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 431                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 432                                          <&clks IMX6SX_CLK_PWM4>;
 433                                 clock-names = "ipg", "per";
 434                                 #pwm-cells = <2>;
 435                         };
 436
 437                         flexcan1: can@2090000 {
 438                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 439                                 reg = <0x02090000 0x4000>;
 440                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 441                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 442                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 443                                 clock-names = "ipg", "per";
 444                                 status = "disabled";
 445                         };
 446
 447                         flexcan2: can@2094000 {
 448                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 449                                 reg = <0x02094000 0x4000>;
 450                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 451                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 452                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 453                                 clock-names = "ipg", "per";
 454                                 status = "disabled";
 455                         };
 456
 457                         gpt: gpt@2098000 {
 458                                 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
 459                                 reg = <0x02098000 0x4000>;
 460                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 461                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 462                                          <&clks IMX6SX_CLK_GPT_3M>;
 463                                 clock-names = "ipg", "per";
 464                         };
 465
 466                         gpio1: gpio@209c000 {
 467                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 468                                 reg = <0x0209c000 0x4000>;
 469                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 470                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 471                                 gpio-controller;
 472                                 #gpio-cells = <2>;
 473                                 interrupt-controller;
 474                                 #interrupt-cells = <2>;
 475                                 gpio-ranges = <&iomuxc 0 5 26>;
 476                         };
 477
 478                         gpio2: gpio@20a0000 {
 479                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 480                                 reg = <0x020a0000 0x4000>;
 481                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 482                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 483                                 gpio-controller;
 484                                 #gpio-cells = <2>;
 485                                 interrupt-controller;
 486                                 #interrupt-cells = <2>;
 487                                 gpio-ranges = <&iomuxc 0 31 20>;
 488                         };
 489
 490                         gpio3: gpio@20a4000 {
 491                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 492                                 reg = <0x020a4000 0x4000>;
 493                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 494                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 495                                 gpio-controller;
 496                                 #gpio-cells = <2>;
 497                                 interrupt-controller;
 498                                 #interrupt-cells = <2>;
 499                                 gpio-ranges = <&iomuxc 0 51 29>;
 500                         };
 501
 502                         gpio4: gpio@20a8000 {
 503                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 504                                 reg = <0x020a8000 0x4000>;
 505                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 506                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 507                                 gpio-controller;
 508                                 #gpio-cells = <2>;
 509                                 interrupt-controller;
 510                                 #interrupt-cells = <2>;
 511                                 gpio-ranges = <&iomuxc 0 80 32>;
 512                         };
 513
 514                         gpio5: gpio@20ac000 {
 515                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 516                                 reg = <0x020ac000 0x4000>;
 517                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 518                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 519                                 gpio-controller;
 520                                 #gpio-cells = <2>;
 521                                 interrupt-controller;
 522                                 #interrupt-cells = <2>;
 523                                 gpio-ranges = <&iomuxc 0 112 24>;
 524                         };
 525
 526                         gpio6: gpio@20b0000 {
 527                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 528                                 reg = <0x020b0000 0x4000>;
 529                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 530                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 531                                 gpio-controller;
 532                                 #gpio-cells = <2>;
 533                                 interrupt-controller;
 534                                 #interrupt-cells = <2>;
 535                                 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
 536                         };
 537
 538                         gpio7: gpio@20b4000 {
 539                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 540                                 reg = <0x020b4000 0x4000>;
 541                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 542                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 543                                 gpio-controller;
 544                                 #gpio-cells = <2>;
 545                                 interrupt-controller;
 546                                 #interrupt-cells = <2>;
 547                                 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
 548                         };
 549
 550                         kpp: kpp@20b8000 {
 551                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 552                                 reg = <0x020b8000 0x4000>;
 553                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 554                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 555                                 status = "disabled";
 556                         };
 557
 558                         wdog1: wdog@20bc000 {
 559                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 560                                 reg = <0x020bc000 0x4000>;
 561                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 562                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 563                         };
 564
 565                         wdog2: wdog@20c0000 {
 566                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 567                                 reg = <0x020c0000 0x4000>;
 568                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 569                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 570                                 status = "disabled";
 571                         };
 572
 573                         clks: ccm@20c4000 {
 574                                 compatible = "fsl,imx6sx-ccm";
 575                                 reg = <0x020c4000 0x4000>;
 576                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 577                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 578                                 #clock-cells = <1>;
 579                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
 580                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
 581                         };
 582
 583                         anatop: anatop@20c8000 {
 584                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 585                                              "syscon", "simple-bus";
 586                                 reg = <0x020c8000 0x1000>;
 587                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 588                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 589                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 590
 591                                 regulator-1p1 {
 592                                         compatible = "fsl,anatop-regulator";
 593                                         regulator-name = "vdd1p1";
 594                                         regulator-min-microvolt = <800000>;
 595                                         regulator-max-microvolt = <1375000>;
 596                                         regulator-always-on;
 597                                         anatop-reg-offset = <0x110>;
 598                                         anatop-vol-bit-shift = <8>;
 599                                         anatop-vol-bit-width = <5>;
 600                                         anatop-min-bit-val = <4>;
 601                                         anatop-min-voltage = <800000>;
 602                                         anatop-max-voltage = <1375000>;
 603                                         anatop-enable-bit = <0>;
 604                                 };
 605
 606                                 regulator-3p0 {
 607                                         compatible = "fsl,anatop-regulator";
 608                                         regulator-name = "vdd3p0";
 609                                         regulator-min-microvolt = <2800000>;
 610                                         regulator-max-microvolt = <3150000>;
 611                                         regulator-always-on;
 612                                         anatop-reg-offset = <0x120>;
 613                                         anatop-vol-bit-shift = <8>;
 614                                         anatop-vol-bit-width = <5>;
 615                                         anatop-min-bit-val = <0>;
 616                                         anatop-min-voltage = <2625000>;
 617                                         anatop-max-voltage = <3400000>;
 618                                         anatop-enable-bit = <0>;
 619                                 };
 620
 621                                 regulator-2p5 {
 622                                         compatible = "fsl,anatop-regulator";
 623                                         regulator-name = "vdd2p5";
 624                                         regulator-min-microvolt = <2100000>;
 625                                         regulator-max-microvolt = <2875000>;
 626                                         regulator-always-on;
 627                                         anatop-reg-offset = <0x130>;
 628                                         anatop-vol-bit-shift = <8>;
 629                                         anatop-vol-bit-width = <5>;
 630                                         anatop-min-bit-val = <0>;
 631                                         anatop-min-voltage = <2100000>;
 632                                         anatop-max-voltage = <2875000>;
 633                                         anatop-enable-bit = <0>;
 634                                 };
 635
 636                                 reg_arm: regulator-vddcore {
 637                                         compatible = "fsl,anatop-regulator";
 638                                         regulator-name = "vddarm";
 639                                         regulator-min-microvolt = <725000>;
 640                                         regulator-max-microvolt = <1450000>;
 641                                         regulator-always-on;
 642                                         anatop-reg-offset = <0x140>;
 643                                         anatop-vol-bit-shift = <0>;
 644                                         anatop-vol-bit-width = <5>;
 645                                         anatop-delay-reg-offset = <0x170>;
 646                                         anatop-delay-bit-shift = <24>;
 647                                         anatop-delay-bit-width = <2>;
 648                                         anatop-min-bit-val = <1>;
 649                                         anatop-min-voltage = <725000>;
 650                                         anatop-max-voltage = <1450000>;
 651                                 };
 652
 653                                 reg_pcie: regulator-vddpcie {
 654                                         compatible = "fsl,anatop-regulator";
 655                                         regulator-name = "vddpcie";
 656                                         regulator-min-microvolt = <725000>;
 657                                         regulator-max-microvolt = <1450000>;
 658                                         anatop-reg-offset = <0x140>;
 659                                         anatop-vol-bit-shift = <9>;
 660                                         anatop-vol-bit-width = <5>;
 661                                         anatop-delay-reg-offset = <0x170>;
 662                                         anatop-delay-bit-shift = <26>;
 663                                         anatop-delay-bit-width = <2>;
 664                                         anatop-min-bit-val = <1>;
 665                                         anatop-min-voltage = <725000>;
 666                                         anatop-max-voltage = <1450000>;
 667                                 };
 668
 669                                 reg_soc: regulator-vddsoc {
 670                                         compatible = "fsl,anatop-regulator";
 671                                         regulator-name = "vddsoc";
 672                                         regulator-min-microvolt = <725000>;
 673                                         regulator-max-microvolt = <1450000>;
 674                                         regulator-always-on;
 675                                         anatop-reg-offset = <0x140>;
 676                                         anatop-vol-bit-shift = <18>;
 677                                         anatop-vol-bit-width = <5>;
 678                                         anatop-delay-reg-offset = <0x170>;
 679                                         anatop-delay-bit-shift = <28>;
 680                                         anatop-delay-bit-width = <2>;
 681                                         anatop-min-bit-val = <1>;
 682                                         anatop-min-voltage = <725000>;
 683                                         anatop-max-voltage = <1450000>;
 684                                 };
 685                         };
 686
 687                         usbphy1: usbphy@20c9000 {
 688                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 689                                 reg = <0x020c9000 0x1000>;
 690                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 691                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 692                                 fsl,anatop = <&anatop>;
 693                         };
 694
 695                         usbphy2: usbphy@20ca000 {
 696                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 697                                 reg = <0x020ca000 0x1000>;
 698                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 699                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 700                                 fsl,anatop = <&anatop>;
 701                         };
 702
 703                         snvs: snvs@20cc000 {
 704                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 705                                 reg = <0x020cc000 0x4000>;
 706
 707                                 snvs_rtc: snvs-rtc-lp {
 708                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 709                                         regmap = <&snvs>;
 710                                         offset = <0x34>;
 711                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 712                                 };
 713
 714                                 snvs_poweroff: snvs-poweroff {
 715                                         compatible = "syscon-poweroff";
 716                                         regmap = <&snvs>;
 717                                         offset = <0x38>;
 718                                         value = <0x60>;
 719                                         mask = <0x60>;
 720                                         status = "disabled";
 721                                 };
 722
 723                                 snvs_pwrkey: snvs-powerkey {
 724                                         compatible = "fsl,sec-v4.0-pwrkey";
 725                                         regmap = <&snvs>;
 726                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 727                                         linux,keycode = <KEY_POWER>;
 728                                         wakeup-source;
 729                                 };
 730                         };
 731
 732                         epit1: epit@20d0000 {
 733                                 reg = <0x020d0000 0x4000>;
 734                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 735                         };
 736
 737                         epit2: epit@20d4000 {
 738                                 reg = <0x020d4000 0x4000>;
 739                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 740                         };
 741
 742                         src: src@20d8000 {
 743                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 744                                 reg = <0x020d8000 0x4000>;
 745                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 746                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 747                                 #reset-cells = <1>;
 748                         };
 749
 750                         gpc: gpc@20dc000 {
 751                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 752                                 reg = <0x020dc000 0x4000>;
 753                                 interrupt-controller;
 754                                 #interrupt-cells = <3>;
 755                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 756                                 interrupt-parent = <&intc>;
 757                                 clocks = <&clks IMX6SX_CLK_IPG>;
 758                                 clock-names = "ipg";
 759
 760                                 pgc {
 761                                         #address-cells = <1>;
 762                                         #size-cells = <0>;
 763
 764                                         power-domain@0 {
 765                                                 reg = <0>;
 766                                                 #power-domain-cells = <0>;
 767                                         };
 768
 769                                         pd_pu: power-domain@1 {
 770                                                 reg = <1>;
 771                                                 #power-domain-cells = <0>;
 772                                                 power-supply = <&reg_soc>;
 773                                                 clocks = <&clks IMX6SX_CLK_GPU>;
 774                                         };
 775
 776                                         pd_pci: power-domain@3 {
 777                                                 reg = <3>;
 778                                                 #power-domain-cells = <0>;
 779                                                 power-supply = <&reg_pcie>;
 780                                         };
 781                                 };
 782                         };
 783
 784                         iomuxc: iomuxc@20e0000 {
 785                                 compatible = "fsl,imx6sx-iomuxc";
 786                                 reg = <0x020e0000 0x4000>;
 787                         };
 788
 789                         gpr: iomuxc-gpr@20e4000 {
 790                                 compatible = "fsl,imx6sx-iomuxc-gpr",
 791                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 792                                 reg = <0x020e4000 0x4000>;
 793                         };
 794
 795                         sdma: sdma@20ec000 {
 796                                 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
 797                                 reg = <0x020ec000 0x4000>;
 798                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 799                                 clocks = <&clks IMX6SX_CLK_SDMA>,
 800                                          <&clks IMX6SX_CLK_SDMA>;
 801                                 clock-names = "ipg", "ahb";
 802                                 #dma-cells = <3>;
 803                                 /* imx6sx reuses imx6q sdma firmware */
 804                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 805                         };
 806                 };
 807
 808                 aips2: aips-bus@2100000 {
 809                         compatible = "fsl,aips-bus", "simple-bus";
 810                         #address-cells = <1>;
 811                         #size-cells = <1>;
 812                         reg = <0x02100000 0x100000>;
 813                         ranges;
 814
 815                         crypto: caam@2100000 {
 816                                 compatible = "fsl,sec-v4.0";
 817                                 fsl,sec-era = <4>;
 818                                 #address-cells = <1>;
 819                                 #size-cells = <1>;
 820                                 reg = <0x2100000 0x10000>;
 821                                 ranges = <0 0x2100000 0x10000>;
 822                                 interrupt-parent = <&intc>;
 823                                 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
 824                                          <&clks IMX6SX_CLK_CAAM_ACLK>,
 825                                          <&clks IMX6SX_CLK_CAAM_IPG>,
 826                                          <&clks IMX6SX_CLK_EIM_SLOW>;
 827                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
 828
 829                                 sec_jr0: jr0@1000 {
 830                                         compatible = "fsl,sec-v4.0-job-ring";
 831                                         reg = <0x1000 0x1000>;
 832                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 833                                 };
 834
 835                                 sec_jr1: jr1@2000 {
 836                                         compatible = "fsl,sec-v4.0-job-ring";
 837                                         reg = <0x2000 0x1000>;
 838                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 839                                 };
 840                         };
 841
 842                         usbotg1: usb@2184000 {
 843                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 844                                 reg = <0x02184000 0x200>;
 845                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 846                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 847                                 fsl,usbphy = <&usbphy1>;
 848                                 fsl,usbmisc = <&usbmisc 0>;
 849                                 fsl,anatop = <&anatop>;
 850                                 ahb-burst-config = <0x0>;
 851                                 tx-burst-size-dword = <0x10>;
 852                                 rx-burst-size-dword = <0x10>;
 853                                 status = "disabled";
 854                         };
 855
 856                         usbotg2: usb@2184200 {
 857                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 858                                 reg = <0x02184200 0x200>;
 859                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 860                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 861                                 fsl,usbphy = <&usbphy2>;
 862                                 fsl,usbmisc = <&usbmisc 1>;
 863                                 ahb-burst-config = <0x0>;
 864                                 tx-burst-size-dword = <0x10>;
 865                                 rx-burst-size-dword = <0x10>;
 866                                 status = "disabled";
 867                         };
 868
 869                         usbh: usb@2184400 {
 870                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 871                                 reg = <0x02184400 0x200>;
 872                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 873                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 874                                 fsl,usbmisc = <&usbmisc 2>;
 875                                 phy_type = "hsic";
 876                                 fsl,anatop = <&anatop>;
 877                                 dr_mode = "host";
 878                                 ahb-burst-config = <0x0>;
 879                                 tx-burst-size-dword = <0x10>;
 880                                 rx-burst-size-dword = <0x10>;
 881                                 status = "disabled";
 882                         };
 883
 884                         usbmisc: usbmisc@2184800 {
 885                                 #index-cells = <1>;
 886                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
 887                                 reg = <0x02184800 0x200>;
 888                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 889                         };
 890
 891                         fec1: ethernet@2188000 {
 892                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 893                                 reg = <0x02188000 0x4000>;
 894                                 interrupt-names = "int0", "pps";
 895                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 896                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 897                                 clocks = <&clks IMX6SX_CLK_ENET>,
 898                                          <&clks IMX6SX_CLK_ENET_AHB>,
 899                                          <&clks IMX6SX_CLK_ENET_PTP>,
 900                                          <&clks IMX6SX_CLK_ENET_REF>,
 901                                          <&clks IMX6SX_CLK_ENET_PTP>;
 902                                 clock-names = "ipg", "ahb", "ptp",
 903                                               "enet_clk_ref", "enet_out";
 904                                 fsl,num-tx-queues=<3>;
 905                                 fsl,num-rx-queues=<3>;
 906                                 status = "disabled";
 907                         };
 908
 909                         mlb: mlb@218c000 {
 910                                 reg = <0x0218c000 0x4000>;
 911                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 912                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 913                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 914                                 clocks = <&clks IMX6SX_CLK_MLB>;
 915                                 status = "disabled";
 916                         };
 917
 918                         usdhc1: usdhc@2190000 {
 919                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 920                                 reg = <0x02190000 0x4000>;
 921                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 922                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 923                                          <&clks IMX6SX_CLK_USDHC1>,
 924                                          <&clks IMX6SX_CLK_USDHC1>;
 925                                 clock-names = "ipg", "ahb", "per";
 926                                 bus-width = <4>;
 927                                 status = "disabled";
 928                         };
 929
 930                         usdhc2: usdhc@2194000 {
 931                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 932                                 reg = <0x02194000 0x4000>;
 933                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 934                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 935                                          <&clks IMX6SX_CLK_USDHC2>,
 936                                          <&clks IMX6SX_CLK_USDHC2>;
 937                                 clock-names = "ipg", "ahb", "per";
 938                                 bus-width = <4>;
 939                                 status = "disabled";
 940                         };
 941
 942                         usdhc3: usdhc@2198000 {
 943                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 944                                 reg = <0x02198000 0x4000>;
 945                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 946                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
 947                                          <&clks IMX6SX_CLK_USDHC3>,
 948                                          <&clks IMX6SX_CLK_USDHC3>;
 949                                 clock-names = "ipg", "ahb", "per";
 950                                 bus-width = <4>;
 951                                 status = "disabled";
 952                         };
 953
 954                         usdhc4: usdhc@219c000 {
 955                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 956                                 reg = <0x0219c000 0x4000>;
 957                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 958                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
 959                                          <&clks IMX6SX_CLK_USDHC4>,
 960                                          <&clks IMX6SX_CLK_USDHC4>;
 961                                 clock-names = "ipg", "ahb", "per";
 962                                 bus-width = <4>;
 963                                 status = "disabled";
 964                         };
 965
 966                         i2c1: i2c@21a0000 {
 967                                 #address-cells = <1>;
 968                                 #size-cells = <0>;
 969                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 970                                 reg = <0x021a0000 0x4000>;
 971                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 972                                 clocks = <&clks IMX6SX_CLK_I2C1>;
 973                                 status = "disabled";
 974                         };
 975
 976                         i2c2: i2c@21a4000 {
 977                                 #address-cells = <1>;
 978                                 #size-cells = <0>;
 979                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 980                                 reg = <0x021a4000 0x4000>;
 981                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 982                                 clocks = <&clks IMX6SX_CLK_I2C2>;
 983                                 status = "disabled";
 984                         };
 985
 986                         i2c3: i2c@21a8000 {
 987                                 #address-cells = <1>;
 988                                 #size-cells = <0>;
 989                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 990                                 reg = <0x021a8000 0x4000>;
 991                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 992                                 clocks = <&clks IMX6SX_CLK_I2C3>;
 993                                 status = "disabled";
 994                         };
 995
 996                         mmdc: mmdc@21b0000 {
 997                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
 998                                 reg = <0x021b0000 0x4000>;
 999                         };
1000
1001                         fec2: ethernet@21b4000 {
1002                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1003                                 reg = <0x021b4000 0x4000>;
1004                                 interrupt-names = "int0", "pps";
1005                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1006                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1007                                 clocks = <&clks IMX6SX_CLK_ENET>,
1008                                          <&clks IMX6SX_CLK_ENET_AHB>,
1009                                          <&clks IMX6SX_CLK_ENET_PTP>,
1010                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
1011                                          <&clks IMX6SX_CLK_ENET_PTP>;
1012                                 clock-names = "ipg", "ahb", "ptp",
1013                                               "enet_clk_ref", "enet_out";
1014                                 status = "disabled";
1015                         };
1016
1017                         weim: weim@21b8000 {
1018                                 #address-cells = <2>;
1019                                 #size-cells = <1>;
1020                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1021                                 reg = <0x021b8000 0x4000>;
1022                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1023                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1024                                 fsl,weim-cs-gpr = <&gpr>;
1025                                 status = "disabled";
1026                         };
1027
1028                         ocotp: ocotp@21bc000 {
1029                                 #address-cells = <1>;
1030                                 #size-cells = <1>;
1031                                 compatible = "fsl,imx6sx-ocotp", "syscon";
1032                                 reg = <0x021bc000 0x4000>;
1033                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1034
1035                                 tempmon_calib: calib@38 {
1036                                         reg = <0x38 4>;
1037                                 };
1038
1039                                 tempmon_temp_grade: temp-grade@20 {
1040                                         reg = <0x20 4>;
1041                                 };
1042                         };
1043
1044                         sai1: sai@21d4000 {
1045                                 compatible = "fsl,imx6sx-sai";
1046                                 reg = <0x021d4000 0x4000>;
1047                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1048                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1049                                          <&clks IMX6SX_CLK_SAI1>,
1050                                          <&clks 0>, <&clks 0>;
1051                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1052                                 dma-names = "rx", "tx";
1053                                 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1054                                 status = "disabled";
1055                         };
1056
1057                         audmux: audmux@21d8000 {
1058                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1059                                 reg = <0x021d8000 0x4000>;
1060                                 status = "disabled";
1061                         };
1062
1063                         sai2: sai@21dc000 {
1064                                 compatible = "fsl,imx6sx-sai";
1065                                 reg = <0x021dc000 0x4000>;
1066                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1067                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1068                                          <&clks IMX6SX_CLK_SAI2>,
1069                                          <&clks 0>, <&clks 0>;
1070                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1071                                 dma-names = "rx", "tx";
1072                                 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1073                                 status = "disabled";
1074                         };
1075
1076                         qspi1: qspi@21e0000 {
1077                                 #address-cells = <1>;
1078                                 #size-cells = <0>;
1079                                 compatible = "fsl,imx6sx-qspi";
1080                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1081                                 reg-names = "QuadSPI", "QuadSPI-memory";
1082                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1083                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1084                                          <&clks IMX6SX_CLK_QSPI1>;
1085                                 clock-names = "qspi_en", "qspi";
1086                                 status = "disabled";
1087                         };
1088
1089                         qspi2: qspi@21e4000 {
1090                                 #address-cells = <1>;
1091                                 #size-cells = <0>;
1092                                 compatible = "fsl,imx6sx-qspi";
1093                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1094                                 reg-names = "QuadSPI", "QuadSPI-memory";
1095                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1096                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1097                                          <&clks IMX6SX_CLK_QSPI2>;
1098                                 clock-names = "qspi_en", "qspi";
1099                                 status = "disabled";
1100                         };
1101
1102                         uart2: serial@21e8000 {
1103                                 compatible = "fsl,imx6sx-uart",
1104                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1105                                 reg = <0x021e8000 0x4000>;
1106                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1107                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1108                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1109                                 clock-names = "ipg", "per";
1110                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1111                                 dma-names = "rx", "tx";
1112                                 status = "disabled";
1113                         };
1114
1115                         uart3: serial@21ec000 {
1116                                 compatible = "fsl,imx6sx-uart",
1117                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1118                                 reg = <0x021ec000 0x4000>;
1119                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1120                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1121                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1122                                 clock-names = "ipg", "per";
1123                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1124                                 dma-names = "rx", "tx";
1125                                 status = "disabled";
1126                         };
1127
1128                         uart4: serial@21f0000 {
1129                                 compatible = "fsl,imx6sx-uart",
1130                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1131                                 reg = <0x021f0000 0x4000>;
1132                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1133                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1134                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1135                                 clock-names = "ipg", "per";
1136                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1137                                 dma-names = "rx", "tx";
1138                                 status = "disabled";
1139                         };
1140
1141                         uart5: serial@21f4000 {
1142                                 compatible = "fsl,imx6sx-uart",
1143                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1144                                 reg = <0x021f4000 0x4000>;
1145                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1146                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1147                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1148                                 clock-names = "ipg", "per";
1149                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1150                                 dma-names = "rx", "tx";
1151                                 status = "disabled";
1152                         };
1153
1154                         i2c4: i2c@21f8000 {
1155                                 #address-cells = <1>;
1156                                 #size-cells = <0>;
1157                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1158                                 reg = <0x021f8000 0x4000>;
1159                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1160                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1161                                 status = "disabled";
1162                         };
1163                 };
1164
1165                 aips3: aips-bus@2200000 {
1166                         compatible = "fsl,aips-bus", "simple-bus";
1167                         #address-cells = <1>;
1168                         #size-cells = <1>;
1169                         reg = <0x02200000 0x100000>;
1170                         ranges;
1171
1172                         spba-bus@2240000 {
1173                                 compatible = "fsl,spba-bus", "simple-bus";
1174                                 #address-cells = <1>;
1175                                 #size-cells = <1>;
1176                                 reg = <0x02240000 0x40000>;
1177                                 ranges;
1178
1179                                 csi1: csi@2214000 {
1180                                         reg = <0x02214000 0x4000>;
1181                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1182                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1183                                                  <&clks IMX6SX_CLK_CSI>,
1184                                                  <&clks IMX6SX_CLK_DCIC1>;
1185                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1186                                         status = "disabled";
1187                                 };
1188
1189                                 pxp: pxp@2218000 {
1190                                         reg = <0x02218000 0x4000>;
1191                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1192                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1193                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1194                                         clock-names = "pxp-axi", "disp-axi";
1195                                         status = "disabled";
1196                                 };
1197
1198                                 csi2: csi@221c000 {
1199                                         reg = <0x0221c000 0x4000>;
1200                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1201                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1202                                                  <&clks IMX6SX_CLK_CSI>,
1203                                                  <&clks IMX6SX_CLK_DCIC2>;
1204                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1205                                         status = "disabled";
1206                                 };
1207
1208                                 lcdif1: lcdif@2220000 {
1209                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1210                                         reg = <0x02220000 0x4000>;
1211                                         interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1212                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1213                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1214                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1215                                         clock-names = "pix", "axi", "disp_axi";
1216                                         status = "disabled";
1217                                 };
1218
1219                                 lcdif2: lcdif@2224000 {
1220                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1221                                         reg = <0x02224000 0x4000>;
1222                                         interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1223                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1224                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1225                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1226                                         clock-names = "pix", "axi", "disp_axi";
1227                                         status = "disabled";
1228                                 };
1229
1230                                 vadc: vadc@2228000 {
1231                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1232                                         reg-names = "vadc-vafe", "vadc-vdec";
1233                                         clocks = <&clks IMX6SX_CLK_VADC>,
1234                                                  <&clks IMX6SX_CLK_CSI>;
1235                                         clock-names = "vadc", "csi";
1236                                         status = "disabled";
1237                                 };
1238                         };
1239
1240                         adc1: adc@2280000 {
1241                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1242                                 reg = <0x02280000 0x4000>;
1243                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1244                                 clocks = <&clks IMX6SX_CLK_IPG>;
1245                                 clock-names = "adc";
1246                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1247                                                          <20000000>;
1248                                 status = "disabled";
1249                         };
1250
1251                         adc2: adc@2284000 {
1252                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1253                                 reg = <0x02284000 0x4000>;
1254                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1255                                 clocks = <&clks IMX6SX_CLK_IPG>;
1256                                 clock-names = "adc";
1257                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1258                                                          <20000000>;
1259                                 status = "disabled";
1260                         };
1261
1262                         wdog3: wdog@2288000 {
1263                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1264                                 reg = <0x02288000 0x4000>;
1265                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1266                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1267                                 status = "disabled";
1268                         };
1269
1270                         ecspi5: ecspi@228c000 {
1271                                 #address-cells = <1>;
1272                                 #size-cells = <0>;
1273                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1274                                 reg = <0x0228c000 0x4000>;
1275                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1276                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1277                                          <&clks IMX6SX_CLK_ECSPI5>;
1278                                 clock-names = "ipg", "per";
1279                                 status = "disabled";
1280                         };
1281
1282                         uart6: serial@22a0000 {
1283                                 compatible = "fsl,imx6sx-uart",
1284                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1285                                 reg = <0x022a0000 0x4000>;
1286                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1287                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1288                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1289                                 clock-names = "ipg", "per";
1290                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1291                                 dma-names = "rx", "tx";
1292                                 status = "disabled";
1293                         };
1294
1295                         pwm5: pwm@22a4000 {
1296                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1297                                 reg = <0x022a4000 0x4000>;
1298                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1299                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1300                                          <&clks IMX6SX_CLK_PWM5>;
1301                                 clock-names = "ipg", "per";
1302                                 #pwm-cells = <2>;
1303                         };
1304
1305                         pwm6: pwm@22a8000 {
1306                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1307                                 reg = <0x022a8000 0x4000>;
1308                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1309                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1310                                          <&clks IMX6SX_CLK_PWM6>;
1311                                 clock-names = "ipg", "per";
1312                                 #pwm-cells = <2>;
1313                         };
1314
1315                         pwm7: pwm@22ac000 {
1316                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1317                                 reg = <0x022ac000 0x4000>;
1318                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1319                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1320                                          <&clks IMX6SX_CLK_PWM7>;
1321                                 clock-names = "ipg", "per";
1322                                 #pwm-cells = <2>;
1323                         };
1324
1325                         pwm8: pwm@22b0000 {
1326                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1327                                 reg = <0x0022b0000 0x4000>;
1328                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1329                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1330                                          <&clks IMX6SX_CLK_PWM8>;
1331                                 clock-names = "ipg", "per";
1332                                 #pwm-cells = <2>;
1333                         };
1334                 };
1335
1336                 pcie: pcie@8ffc000 {
1337                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1338                         reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1339                         reg-names = "dbi", "config";
1340                         #address-cells = <3>;
1341                         #size-cells = <2>;
1342                         device_type = "pci";
1343                         bus-range = <0x00 0xff>;
1344                         ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
1345                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1346                         num-lanes = <1>;
1347                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1348                         interrupt-names = "msi";
1349                         #interrupt-cells = <1>;
1350                         interrupt-map-mask = <0 0 0 0x7>;
1351                         interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1352                                         <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1353                                         <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1354                                         <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1355                         clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1356                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1357                                  <&clks IMX6SX_CLK_PCIE_REF_125M>,
1358                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1359                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1360                         power-domains = <&pd_pci>;
1361                         status = "disabled";
1362                 };
1363         };
1364 };