arch/arm/boot/dts/imx6sll.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017-2018 NXP.
   5  *
   6  */
   7
   8 #include <dt-bindings/clock/imx6sll-clock.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include "imx6sll-pinfunc.h"
  12
  13 / {
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         aliases {
  18                 gpio0 = &gpio1;
  19                 gpio1 = &gpio2;
  20                 gpio2 = &gpio3;
  21                 gpio3 = &gpio4;
  22                 gpio4 = &gpio5;
  23                 gpio5 = &gpio6;
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 mmc0 = &usdhc1;
  28                 mmc1 = &usdhc2;
  29                 mmc2 = &usdhc3;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 spi0 = &ecspi1;
  36                 spi1 = &ecspi2;
  37                 spi3 = &ecspi3;
  38                 spi4 = &ecspi4;
  39                 usbphy0 = &usbphy1;
  40                 usbphy1 = &usbphy2;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu0: cpu@0 {
  48                         compatible = "arm,cortex-a9";
  49                         device_type = "cpu";
  50                         reg = <0>;
  51                         next-level-cache = <&L2>;
  52                         operating-points = <
  53                                 /* kHz    uV */
  54                                 996000  1275000
  55                                 792000  1175000
  56                                 396000  1075000
  57                                 198000  975000
  58                         >;
  59                         fsl,soc-operating-points = <
  60                                 /* ARM kHz      SOC-PU uV */
  61                                 996000          1175000
  62                                 792000          1175000
  63                                 396000          1175000
  64                                 198000          1175000
  65                         >;
  66                         clock-latency = <61036>; /* two CLK32 periods */
  67                         clocks = <&clks IMX6SLL_CLK_ARM>,
  68                                  <&clks IMX6SLL_CLK_PLL2_PFD2>,
  69                                  <&clks IMX6SLL_CLK_STEP>,
  70                                  <&clks IMX6SLL_CLK_PLL1_SW>,
  71                                  <&clks IMX6SLL_CLK_PLL1_SYS>;
  72                         clock-names = "arm", "pll2_pfd2_396m", "step",
  73                                       "pll1_sw", "pll1_sys";
  74                 };
  75         };
  76
  77         intc: interrupt-controller@a01000 {
  78                 compatible = "arm,cortex-a9-gic";
  79                 #interrupt-cells = <3>;
  80                 interrupt-controller;
  81                 reg = <0x00a01000 0x1000>,
  82                       <0x00a00100 0x100>;
  83                 interrupt-parent = <&intc>;
  84         };
  85
  86         ckil: clock-ckil {
  87                 compatible = "fixed-clock";
  88                 #clock-cells = <0>;
  89                 clock-frequency = <32768>;
  90                 clock-output-names = "ckil";
  91         };
  92
  93         osc: clock-osc-24m {
  94                 compatible = "fixed-clock";
  95                 #clock-cells = <0>;
  96                 clock-frequency = <24000000>;
  97                 clock-output-names = "osc";
  98         };
  99
 100         ipp_di0: clock-ipp-di0 {
 101                 compatible = "fixed-clock";
 102                 #clock-cells = <0>;
 103                 clock-frequency = <0>;
 104                 clock-output-names = "ipp_di0";
 105         };
 106
 107         ipp_di1: clock-ipp-di1 {
 108                 compatible = "fixed-clock";
 109                 #clock-cells = <0>;
 110                 clock-frequency = <0>;
 111                 clock-output-names = "ipp_di1";
 112         };
 113
 114         tempmon: temperature-sensor {
 115                 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
 116                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 117                 interrupt-parent = <&gpc>;
 118                 fsl,tempmon = <&anatop>;
 119                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 120                 nvmem-cell-names = "calib", "temp_grade";
 121                 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
 122         };
 123
 124         soc {
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127                 compatible = "simple-bus";
 128                 interrupt-parent = <&gpc>;
 129                 ranges;
 130
 131                 ocram: sram@900000 {
 132                         compatible = "mmio-sram";
 133                         reg = <0x00900000 0x20000>;
 134                 };
 135
 136                 L2: l2-cache@a02000 {
 137                         compatible = "arm,pl310-cache";
 138                         reg = <0x00a02000 0x1000>;
 139                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 140                         cache-unified;
 141                         cache-level = <2>;
 142                         arm,tag-latency = <4 2 3>;
 143                         arm,data-latency = <4 2 3>;
 144                 };
 145
 146                 aips1: aips-bus@2000000 {
 147                         compatible = "fsl,aips-bus", "simple-bus";
 148                         #address-cells = <1>;
 149                         #size-cells = <1>;
 150                         reg = <0x02000000 0x100000>;
 151                         ranges;
 152
 153                         spba: spba-bus@2000000 {
 154                                 compatible = "fsl,spba-bus", "simple-bus";
 155                                 #address-cells = <1>;
 156                                 #size-cells = <1>;
 157                                 reg = <0x02000000 0x40000>;
 158                                 ranges;
 159
 160                                 spdif: spdif@2004000 {
 161                                         compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
 162                                         reg = <0x02004000 0x4000>;
 163                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 164                                         dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
 165                                         dma-names = "rx", "tx";
 166                                         clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
 167                                                  <&clks IMX6SLL_CLK_OSC>,
 168                                                  <&clks IMX6SLL_CLK_SPDIF>,
 169                                                  <&clks IMX6SLL_CLK_DUMMY>,
 170                                                  <&clks IMX6SLL_CLK_DUMMY>,
 171                                                  <&clks IMX6SLL_CLK_DUMMY>,
 172                                                  <&clks IMX6SLL_CLK_IPG>,
 173                                                  <&clks IMX6SLL_CLK_DUMMY>,
 174                                                  <&clks IMX6SLL_CLK_DUMMY>,
 175                                                  <&clks IMX6SLL_CLK_SPBA>;
 176                                         clock-names = "core", "rxtx0",
 177                                                       "rxtx1", "rxtx2",
 178                                                       "rxtx3", "rxtx4",
 179                                                       "rxtx5", "rxtx6",
 180                                                       "rxtx7", "dma";
 181                                         status = "disabled";
 182                                 };
 183
 184                                 ecspi1: spi@2008000 {
 185                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 186                                         reg = <0x02008000 0x4000>;
 187                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 188                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 189                                         dma-names = "rx", "tx";
 190                                         clocks = <&clks IMX6SLL_CLK_ECSPI1>,
 191                                                  <&clks IMX6SLL_CLK_ECSPI1>;
 192                                         clock-names = "ipg", "per";
 193                                         status = "disabled";
 194                                 };
 195
 196                                 ecspi2: spi@200c000 {
 197                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 198                                         reg = <0x0200c000 0x4000>;
 199                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 200                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 201                                         dma-names = "rx", "tx";
 202                                         clocks = <&clks IMX6SLL_CLK_ECSPI2>,
 203                                                  <&clks IMX6SLL_CLK_ECSPI2>;
 204                                         clock-names = "ipg", "per";
 205                                         status = "disabled";
 206                                 };
 207
 208                                 ecspi3: spi@2010000 {
 209                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 210                                         reg = <0x02010000 0x4000>;
 211                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 212                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 213                                         dma-names = "rx", "tx";
 214                                         clocks = <&clks IMX6SLL_CLK_ECSPI3>,
 215                                                  <&clks IMX6SLL_CLK_ECSPI3>;
 216                                         clock-names = "ipg", "per";
 217                                         status = "disabled";
 218                                 };
 219
 220                                 ecspi4: spi@2014000 {
 221                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 222                                         reg = <0x02014000 0x4000>;
 223                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 224                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 225                                         dma-names = "rx", "tx";
 226                                         clocks = <&clks IMX6SLL_CLK_ECSPI4>,
 227                                                  <&clks IMX6SLL_CLK_ECSPI4>;
 228                                         clock-names = "ipg", "per";
 229                                         status = "disabled";
 230                                 };
 231
 232                                 uart4: serial@2018000 {
 233                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 234                                                      "fsl,imx21-uart";
 235                                         reg = <0x02018000 0x4000>;
 236                                         interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 237                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 238                                         dma-names = "rx", "tx";
 239                                         clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
 240                                                  <&clks IMX6SLL_CLK_UART4_SERIAL>;
 241                                         clock-names = "ipg", "per";
 242                                         status = "disabled";
 243                                 };
 244
 245                                 uart1: serial@2020000 {
 246                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 247                                                      "fsl,imx21-uart";
 248                                         reg = <0x02020000 0x4000>;
 249                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 250                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 251                                         dma-names = "rx", "tx";
 252                                         clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
 253                                                  <&clks IMX6SLL_CLK_UART1_SERIAL>;
 254                                         clock-names = "ipg", "per";
 255                                         status = "disabled";
 256                                 };
 257
 258                                 uart2: serial@2024000 {
 259                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 260                                                      "fsl,imx21-uart";
 261                                         reg = <0x02024000 0x4000>;
 262                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 263                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 264                                         dma-names = "rx", "tx";
 265                                         clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
 266                                                  <&clks IMX6SLL_CLK_UART2_SERIAL>;
 267                                         clock-names = "ipg", "per";
 268                                         status = "disabled";
 269                                 };
 270
 271                                 ssi1: ssi-controller@2028000 {
 272                                         compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 273                                         reg = <0x02028000 0x4000>;
 274                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 275                                         dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
 276                                         dma-names = "rx", "tx";
 277                                         fsl,fifo-depth = <15>;
 278                                         clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
 279                                                  <&clks IMX6SLL_CLK_SSI1>;
 280                                         clock-names = "ipg", "baud";
 281                                         status = "disabled";
 282                                 };
 283
 284                                 ssi2: ssi-controller@202c000 {
 285                                         compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 286                                         reg = <0x0202c000 0x4000>;
 287                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 288                                         dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
 289                                         dma-names = "rx", "tx";
 290                                         fsl,fifo-depth = <15>;
 291                                         clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
 292                                                  <&clks IMX6SLL_CLK_SSI2>;
 293                                         clock-names = "ipg", "baud";
 294                                         status = "disabled";
 295                                 };
 296
 297                                 ssi3: ssi-controller@2030000 {
 298                                         compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 299                                         reg = <0x02030000 0x4000>;
 300                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 301                                         dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
 302                                         dma-names = "rx", "tx";
 303                                         fsl,fifo-depth = <15>;
 304                                         clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
 305                                                  <&clks IMX6SLL_CLK_SSI3>;
 306                                         clock-names = "ipg", "baud";
 307                                         status = "disabled";
 308                                 };
 309
 310                                 uart3: serial@2034000 {
 311                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 312                                                      "fsl,imx21-uart";
 313                                         reg = <0x02034000 0x4000>;
 314                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 315                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 316                                         dma-name = "rx", "tx";
 317                                         clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
 318                                                  <&clks IMX6SLL_CLK_UART3_SERIAL>;
 319                                         clock-names = "ipg", "per";
 320                                         status = "disabled";
 321                                 };
 322                         };
 323
 324                         pwm1: pwm@2080000 {
 325                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 326                                 reg = <0x02080000 0x4000>;
 327                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 328                                 clocks = <&clks IMX6SLL_CLK_PWM1>,
 329                                          <&clks IMX6SLL_CLK_PWM1>;
 330                                 clock-names = "ipg", "per";
 331                                 #pwm-cells = <2>;
 332                         };
 333
 334                         pwm2: pwm@2084000 {
 335                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 336                                 reg = <0x02084000 0x4000>;
 337                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 338                                 clocks = <&clks IMX6SLL_CLK_PWM2>,
 339                                          <&clks IMX6SLL_CLK_PWM2>;
 340                                 clock-names = "ipg", "per";
 341                                 #pwm-cells = <2>;
 342                         };
 343
 344                         pwm3: pwm@2088000 {
 345                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 346                                 reg = <0x02088000 0x4000>;
 347                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 348                                 clocks = <&clks IMX6SLL_CLK_PWM3>,
 349                                          <&clks IMX6SLL_CLK_PWM3>;
 350                                 clock-names = "ipg", "per";
 351                                 #pwm-cells = <2>;
 352                         };
 353
 354                         pwm4: pwm@208c000 {
 355                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 356                                 reg = <0x0208c000 0x4000>;
 357                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 358                                 clocks = <&clks IMX6SLL_CLK_PWM4>,
 359                                          <&clks IMX6SLL_CLK_PWM4>;
 360                                 clock-names = "ipg", "per";
 361                                 #pwm-cells = <2>;
 362                         };
 363
 364                         gpt1: timer@2098000 {
 365                                 compatible = "fsl,imx6sl-gpt";
 366                                 reg = <0x02098000 0x4000>;
 367                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 368                                 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
 369                                          <&clks IMX6SLL_CLK_GPT_SERIAL>;
 370                                 clock-names = "ipg", "per";
 371                         };
 372
 373                         gpio1: gpio@209c000 {
 374                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 375                                 reg = <0x0209c000 0x4000>;
 376                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 377                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 378                                 clocks = <&clks IMX6SLL_CLK_GPIO1>;
 379                                 gpio-controller;
 380                                 #gpio-cells = <2>;
 381                                 interrupt-controller;
 382                                 #interrupt-cells = <2>;
 383                                 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
 384                         };
 385
 386                         gpio2: gpio@20a0000 {
 387                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 388                                 reg = <0x020a0000 0x4000>;
 389                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 390                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 391                                 clocks = <&clks IMX6SLL_CLK_GPIO2>;
 392                                 gpio-controller;
 393                                 #gpio-cells = <2>;
 394                                 interrupt-controller;
 395                                 #interrupt-cells = <2>;
 396                                 gpio-ranges = <&iomuxc 0 50 32>;
 397                         };
 398
 399                         gpio3: gpio@20a4000 {
 400                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 401                                 reg = <0x020a4000 0x4000>;
 402                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 403                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 404                                 clocks = <&clks IMX6SLL_CLK_GPIO3>;
 405                                 gpio-controller;
 406                                 #gpio-cells = <2>;
 407                                 interrupt-controller;
 408                                 #interrupt-cells = <2>;
 409                                 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
 410                                               <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
 411                                               <&iomuxc 21 6 11>;
 412                         };
 413
 414                         gpio4: gpio@20a8000 {
 415                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 416                                 reg = <0x020a8000 0x4000>;
 417                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 418                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 419                                 clocks = <&clks IMX6SLL_CLK_GPIO4>;
 420                                 gpio-controller;
 421                                 #gpio-cells = <2>;
 422                                 interrupt-controller;
 423                                 #interrupt-cells = <2>;
 424                                 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
 425                                               <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
 426                                               <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
 427                                               <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
 428                                               <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
 429                                               <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
 430                                               <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
 431                                               <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
 432                                               <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
 433                         };
 434
 435                         gpio5: gpio@20ac000 {
 436                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 437                                 reg = <0x020ac000 0x4000>;
 438                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 439                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 440                                 clocks = <&clks IMX6SLL_CLK_GPIO5>;
 441                                 gpio-controller;
 442                                 #gpio-cells = <2>;
 443                                 interrupt-controller;
 444                                 #interrupt-cells = <2>;
 445                                 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
 446                                               <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
 447                                               <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
 448                                               <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
 449                                               <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
 450                                               <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
 451                                               <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
 452                                               <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
 453                                               <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
 454                                               <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
 455                                               <&iomuxc 21 137 1>;
 456                         };
 457
 458                         gpio6: gpio@20b0000 {
 459                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 460                                 reg = <0x020b0000 0x4000>;
 461                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 462                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 463                                 clocks = <&clks IMX6SLL_CLK_GPIO6>;
 464                                 gpio-controller;
 465                                 #gpio-cells = <2>;
 466                                 interrupt-controller;
 467                                 #interrupt-cells = <2>;
 468                         };
 469
 470                         kpp: keypad@20b8000 {
 471                                 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
 472                                 reg = <0x020b8000 0x4000>;
 473                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 474                                 clocks = <&clks IMX6SLL_CLK_KPP>;
 475                                 status = "disabled";
 476                         };
 477
 478                         wdog1: watchdog@20bc000 {
 479                                 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
 480                                 reg = <0x020bc000 0x4000>;
 481                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 482                                 clocks = <&clks IMX6SLL_CLK_WDOG1>;
 483                         };
 484
 485                         wdog2: watchdog@20c0000 {
 486                                 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
 487                                 reg = <0x020c0000 0x4000>;
 488                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 489                                 clocks = <&clks IMX6SLL_CLK_WDOG2>;
 490                                 status = "disabled";
 491                         };
 492
 493                         clks: clock-controller@20c4000 {
 494                                 compatible = "fsl,imx6sll-ccm";
 495                                 reg = <0x020c4000 0x4000>;
 496                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 497                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 498                                 #clock-cells = <1>;
 499                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 500                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 501
 502                                 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
 503                                 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
 504                         };
 505
 506                         anatop: anatop@20c8000 {
 507                                 compatible = "fsl,imx6sll-anatop",
 508                                              "fsl,imx6q-anatop",
 509                                              "syscon", "simple-bus";
 510                                 reg = <0x020c8000 0x4000>;
 511                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 512                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 513                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 514                                 #address-cells = <1>;
 515                                 #size-cells = <0>;
 516
 517                                 reg_3p0: regulator-3p0@20c8120 {
 518                                         compatible = "fsl,anatop-regulator";
 519                                         reg = <0x20c8120>;
 520                                         regulator-name = "vdd3p0";
 521                                         regulator-min-microvolt = <2625000>;
 522                                         regulator-max-microvolt = <3400000>;
 523                                         anatop-reg-offset = <0x120>;
 524                                         anatop-vol-bit-shift = <8>;
 525                                         anatop-vol-bit-width = <5>;
 526                                         anatop-min-bit-val = <0>;
 527                                         anatop-min-voltage = <2625000>;
 528                                         anatop-max-voltage = <3400000>;
 529                                         anatop-enable-bit = <0>;
 530                                 };
 531                         };
 532
 533                         usbphy1: usb-phy@20c9000 {
 534                                 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
 535                                                 "fsl,imx23-usbphy";
 536                                 reg = <0x020c9000 0x1000>;
 537                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 538                                 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
 539                                 phy-3p0-supply = <&reg_3p0>;
 540                                 fsl,anatop = <&anatop>;
 541                         };
 542
 543                         usbphy2: usb-phy@20ca000 {
 544                                 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
 545                                                 "fsl,imx23-usbphy";
 546                                 reg = <0x020ca000 0x1000>;
 547                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 548                                 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
 549                                 phy-reg_3p0-supply = <&reg_3p0>;
 550                                 fsl,anatop = <&anatop>;
 551                         };
 552
 553                         snvs: snvs@20cc000 {
 554                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 555                                 reg = <0x020cc000 0x4000>;
 556
 557                                 snvs_rtc: snvs-rtc-lp {
 558                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 559                                         regmap = <&snvs>;
 560                                         offset = <0x34>;
 561                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 562                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 563                                 };
 564
 565                                 snvs_poweroff: snvs-poweroff {
 566                                         compatible = "syscon-poweroff";
 567                                         regmap = <&snvs>;
 568                                         offset = <0x38>;
 569                                         mask = <0x61>;
 570                                 };
 571
 572                                 snvs_pwrkey: snvs-powerkey {
 573                                         compatible = "fsl,sec-v4.0-pwrkey";
 574                                         regmap = <&snvs>;
 575                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 576                                         linux,keycode = <KEY_POWER>;
 577                                         wakeup-source;
 578                                 };
 579                         };
 580
 581                         src: reset-controller@20d8000 {
 582                                 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
 583                                 reg = <0x020d8000 0x4000>;
 584                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 585                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 586                                 #reset-cells = <1>;
 587                         };
 588
 589                         gpc: interrupt-controller@20dc000 {
 590                                 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
 591                                 reg = <0x020dc000 0x4000>;
 592                                 interrupt-controller;
 593                                 #interrupt-cells = <3>;
 594                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 595                                 interrupt-parent = <&intc>;
 596                                 fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>;
 597                         };
 598
 599                         iomuxc: pinctrl@20e0000 {
 600                                 compatible = "fsl,imx6sll-iomuxc";
 601                                 reg = <0x020e0000 0x4000>;
 602                         };
 603
 604                         gpr: iomuxc-gpr@20e4000 {
 605                                 compatible = "fsl,imx6sll-iomuxc-gpr",
 606                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 607                                 reg = <0x020e4000 0x4000>;
 608                         };
 609
 610                         csi: csi@20e8000 {
 611                                 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
 612                                 reg = <0x020e8000 0x4000>;
 613                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 614                                 clocks = <&clks IMX6SLL_CLK_DUMMY>,
 615                                          <&clks IMX6SLL_CLK_CSI>,
 616                                          <&clks IMX6SLL_CLK_DUMMY>;
 617                                 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
 618                                 status = "disabled";
 619                         };
 620
 621                         sdma: dma-controller@20ec000 {
 622                                 compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
 623                                 reg = <0x020ec000 0x4000>;
 624                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 625                                 clocks = <&clks IMX6SLL_CLK_SDMA>,
 626                                          <&clks IMX6SLL_CLK_SDMA>;
 627                                 clock-names = "ipg", "ahb";
 628                                 #dma-cells = <3>;
 629                                 iram = <&ocram>;
 630                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 631                         };
 632
 633                         lcdif: lcd-controller@20f8000 {
 634                                 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
 635                                 reg = <0x020f8000 0x4000>;
 636                                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 637                                 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
 638                                          <&clks IMX6SLL_CLK_LCDIF_APB>,
 639                                          <&clks IMX6SLL_CLK_DUMMY>;
 640                                 clock-names = "pix", "axi", "disp_axi";
 641                                 status = "disabled";
 642                         };
 643
 644                         dcp: dcp@20fc000 {
 645                                 compatible = "fsl,imx28-dcp";
 646                                 reg = <0x020fc000 0x4000>;
 647                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 648                                              <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 649                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 650                                 clocks = <&clks IMX6SLL_CLK_DCP>;
 651                                 clock-names = "dcp";
 652                         };
 653                 };
 654
 655                 aips2: aips-bus@2100000 {
 656                         compatible = "fsl,aips-bus", "simple-bus";
 657                         #address-cells = <1>;
 658                         #size-cells = <1>;
 659                         reg = <0x02100000 0x100000>;
 660                         ranges;
 661
 662                         usbotg1: usb@2184000 {
 663                                 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
 664                                                 "fsl,imx27-usb";
 665                                 reg = <0x02184000 0x200>;
 666                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 667                                 clocks = <&clks IMX6SLL_CLK_USBOH3>;
 668                                 fsl,usbphy = <&usbphy1>;
 669                                 fsl,usbmisc = <&usbmisc 0>;
 670                                 fsl,anatop = <&anatop>;
 671                                 ahb-burst-config = <0x0>;
 672                                 tx-burst-size-dword = <0x10>;
 673                                 rx-burst-size-dword = <0x10>;
 674                                 status = "disabled";
 675                         };
 676
 677                         usbotg2: usb@2184200 {
 678                                 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
 679                                                 "fsl,imx27-usb";
 680                                 reg = <0x02184200 0x200>;
 681                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 682                                 clocks = <&clks IMX6SLL_CLK_USBOH3>;
 683                                 fsl,usbphy = <&usbphy2>;
 684                                 fsl,usbmisc = <&usbmisc 1>;
 685                                 ahb-burst-config = <0x0>;
 686                                 tx-burst-size-dword = <0x10>;
 687                                 rx-burst-size-dword = <0x10>;
 688                                 status = "disabled";
 689                         };
 690
 691                         usbmisc: usbmisc@2184800 {
 692                                 #index-cells = <1>;
 693                                 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
 694                                                 "fsl,imx6q-usbmisc";
 695                                 reg = <0x02184800 0x200>;
 696                         };
 697
 698                         usdhc1: mmc@2190000 {
 699                                 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 700                                 reg = <0x02190000 0x4000>;
 701                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 702                                 clocks = <&clks IMX6SLL_CLK_USDHC1>,
 703                                          <&clks IMX6SLL_CLK_USDHC1>,
 704                                          <&clks IMX6SLL_CLK_USDHC1>;
 705                                 clock-names = "ipg", "ahb", "per";
 706                                 bus-width = <4>;
 707                                 fsl,tuning-step = <2>;
 708                                 fsl,tuning-start-tap = <20>;
 709                                 status = "disabled";
 710                         };
 711
 712                         usdhc2: mmc@2194000 {
 713                                 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 714                                 reg = <0x02194000 0x4000>;
 715                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 716                                 clocks = <&clks IMX6SLL_CLK_USDHC2>,
 717                                          <&clks IMX6SLL_CLK_USDHC2>,
 718                                          <&clks IMX6SLL_CLK_USDHC2>;
 719                                 clock-names = "ipg", "ahb", "per";
 720                                 bus-width = <4>;
 721                                 fsl,tuning-step = <2>;
 722                                 fsl,tuning-start-tap = <20>;
 723                                 status = "disabled";
 724                         };
 725
 726                         usdhc3: mmc@2198000 {
 727                                 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 728                                 reg = <0x02198000 0x4000>;
 729                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 730                                 clocks = <&clks IMX6SLL_CLK_USDHC3>,
 731                                          <&clks IMX6SLL_CLK_USDHC3>,
 732                                          <&clks IMX6SLL_CLK_USDHC3>;
 733                                 clock-names = "ipg", "ahb", "per";
 734                                 bus-width = <4>;
 735                                 fsl,tuning-step = <2>;
 736                                 fsl,tuning-start-tap = <20>;
 737                                 status = "disabled";
 738                         };
 739
 740                         i2c1: i2c@21a0000 {
 741                                 #address-cells = <1>;
 742                                 #size-cells = <0>;
 743                                 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
 744                                 reg = <0x021a0000 0x4000>;
 745                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 746                                 clocks = <&clks IMX6SLL_CLK_I2C1>;
 747                                 status = "disabled";
 748                         };
 749
 750                         i2c2: i2c@21a4000 {
 751                                 #address-cells = <1>;
 752                                 #size-cells = <0>;
 753                                 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
 754                                 reg = <0x021a4000 0x4000>;
 755                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 756                                 clocks = <&clks IMX6SLL_CLK_I2C2>;
 757                                 status = "disabled";
 758                         };
 759
 760                         i2c3: i2c@21a8000 {
 761                                 #address-cells = <1>;
 762                                 #size-cells = <0>;
 763                                 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
 764                                 reg = <0x021a8000 0x4000>;
 765                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 766                                 clocks = <&clks IMX6SLL_CLK_I2C3>;
 767                                 status = "disabled";
 768                         };
 769
 770                         mmdc: memory-controller@21b0000 {
 771                                 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
 772                                 reg = <0x021b0000 0x4000>;
 773                         };
 774
 775                         ocotp: ocotp-ctrl@21bc000 {
 776                                 #address-cells = <1>;
 777                                 #size-cells = <1>;
 778                                 compatible = "fsl,imx6sll-ocotp", "syscon";
 779                                 reg = <0x021bc000 0x4000>;
 780                                 clocks = <&clks IMX6SLL_CLK_OCOTP>;
 781
 782                                 tempmon_calib: calib@38 {
 783                                         reg = <0x38 4>;
 784                                 };
 785
 786                                 tempmon_temp_grade: temp-grade@20 {
 787                                         reg = <0x20 4>;
 788                                 };
 789                         };
 790
 791                         audmux: audmux@21d8000 {
 792                                 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
 793                                 reg = <0x021d8000 0x4000>;
 794                                 status = "disabled";
 795                         };
 796
 797                         uart5: serial@21f4000 {
 798                                 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
 799                                              "fsl,imx21-uart";
 800                                 reg = <0x021f4000 0x4000>;
 801                                 interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 802                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 803                                 dma-names = "rx", "tx";
 804                                 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
 805                                          <&clks IMX6SLL_CLK_UART5_SERIAL>;
 806                                 clock-names = "ipg", "per";
 807                                 status = "disabled";
 808                         };
 809                 };
 810         };
 811 };