arch/arm/boot/dts/imx6sll.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017-2018 NXP.
   5  *
   6  */
   7
   8 #include <dt-bindings/clock/imx6sll-clock.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include "imx6sll-pinfunc.h"
  12
  13 / {
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         aliases {
  18                 gpio0 = &gpio1;
  19                 gpio1 = &gpio2;
  20                 gpio2 = &gpio3;
  21                 gpio3 = &gpio4;
  22                 gpio4 = &gpio5;
  23                 gpio5 = &gpio6;
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 mmc0 = &usdhc1;
  28                 mmc1 = &usdhc2;
  29                 mmc2 = &usdhc3;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 spi0 = &ecspi1;
  36                 spi1 = &ecspi2;
  37                 spi3 = &ecspi3;
  38                 spi4 = &ecspi4;
  39                 usbphy0 = &usbphy1;
  40                 usbphy1 = &usbphy2;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu0: cpu@0 {
  48                         compatible = "arm,cortex-a9";
  49                         device_type = "cpu";
  50                         reg = <0>;
  51                         next-level-cache = <&L2>;
  52                         operating-points = <
  53                                 /* kHz    uV */
  54                                 996000  1275000
  55                                 792000  1175000
  56                                 396000  1075000
  57                                 198000  975000
  58                         >;
  59                         fsl,soc-operating-points = <
  60                                 /* ARM kHz      SOC-PU uV */
  61                                 996000          1175000
  62                                 792000          1175000
  63                                 396000          1175000
  64                                 198000          1175000
  65                         >;
  66                         clock-latency = <61036>; /* two CLK32 periods */
  67                         #cooling-cells = <2>;
  68                         clocks = <&clks IMX6SLL_CLK_ARM>,
  69                                  <&clks IMX6SLL_CLK_PLL2_PFD2>,
  70                                  <&clks IMX6SLL_CLK_STEP>,
  71                                  <&clks IMX6SLL_CLK_PLL1_SW>,
  72                                  <&clks IMX6SLL_CLK_PLL1_SYS>;
  73                         clock-names = "arm", "pll2_pfd2_396m", "step",
  74                                       "pll1_sw", "pll1_sys";
  75                 };
  76         };
  77
  78         ckil: clock-ckil {
  79                 compatible = "fixed-clock";
  80                 #clock-cells = <0>;
  81                 clock-frequency = <32768>;
  82                 clock-output-names = "ckil";
  83         };
  84
  85         osc: clock-osc-24m {
  86                 compatible = "fixed-clock";
  87                 #clock-cells = <0>;
  88                 clock-frequency = <24000000>;
  89                 clock-output-names = "osc";
  90         };
  91
  92         ipp_di0: clock-ipp-di0 {
  93                 compatible = "fixed-clock";
  94                 #clock-cells = <0>;
  95                 clock-frequency = <0>;
  96                 clock-output-names = "ipp_di0";
  97         };
  98
  99         ipp_di1: clock-ipp-di1 {
 100                 compatible = "fixed-clock";
 101                 #clock-cells = <0>;
 102                 clock-frequency = <0>;
 103                 clock-output-names = "ipp_di1";
 104         };
 105
 106         tempmon: temperature-sensor {
 107                 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
 108                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 109                 interrupt-parent = <&gpc>;
 110                 fsl,tempmon = <&anatop>;
 111                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 112                 nvmem-cell-names = "calib", "temp_grade";
 113                 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
 114         };
 115
 116         soc {
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 compatible = "simple-bus";
 120                 interrupt-parent = <&gpc>;
 121                 ranges;
 122
 123                 ocram: sram@900000 {
 124                         compatible = "mmio-sram";
 125                         reg = <0x00900000 0x20000>;
 126                 };
 127
 128                 intc: interrupt-controller@a01000 {
 129                         compatible = "arm,cortex-a9-gic";
 130                         #interrupt-cells = <3>;
 131                         interrupt-controller;
 132                         reg = <0x00a01000 0x1000>,
 133                               <0x00a00100 0x100>;
 134                         interrupt-parent = <&intc>;
 135                 };
 136
 137                 L2: l2-cache@a02000 {
 138                         compatible = "arm,pl310-cache";
 139                         reg = <0x00a02000 0x1000>;
 140                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 141                         cache-unified;
 142                         cache-level = <2>;
 143                         arm,tag-latency = <4 2 3>;
 144                         arm,data-latency = <4 2 3>;
 145                 };
 146
 147                 aips1: aips-bus@2000000 {
 148                         compatible = "fsl,aips-bus", "simple-bus";
 149                         #address-cells = <1>;
 150                         #size-cells = <1>;
 151                         reg = <0x02000000 0x100000>;
 152                         ranges;
 153
 154                         spba: spba-bus@2000000 {
 155                                 compatible = "fsl,spba-bus", "simple-bus";
 156                                 #address-cells = <1>;
 157                                 #size-cells = <1>;
 158                                 reg = <0x02000000 0x40000>;
 159                                 ranges;
 160
 161                                 spdif: spdif@2004000 {
 162                                         compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
 163                                         reg = <0x02004000 0x4000>;
 164                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 165                                         dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
 166                                         dma-names = "rx", "tx";
 167                                         clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
 168                                                  <&clks IMX6SLL_CLK_OSC>,
 169                                                  <&clks IMX6SLL_CLK_SPDIF>,
 170                                                  <&clks IMX6SLL_CLK_DUMMY>,
 171                                                  <&clks IMX6SLL_CLK_DUMMY>,
 172                                                  <&clks IMX6SLL_CLK_DUMMY>,
 173                                                  <&clks IMX6SLL_CLK_IPG>,
 174                                                  <&clks IMX6SLL_CLK_DUMMY>,
 175                                                  <&clks IMX6SLL_CLK_DUMMY>,
 176                                                  <&clks IMX6SLL_CLK_SPBA>;
 177                                         clock-names = "core", "rxtx0",
 178                                                       "rxtx1", "rxtx2",
 179                                                       "rxtx3", "rxtx4",
 180                                                       "rxtx5", "rxtx6",
 181                                                       "rxtx7", "dma";
 182                                         status = "disabled";
 183                                 };
 184
 185                                 ecspi1: spi@2008000 {
 186                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 187                                         reg = <0x02008000 0x4000>;
 188                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 189                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 190                                         dma-names = "rx", "tx";
 191                                         clocks = <&clks IMX6SLL_CLK_ECSPI1>,
 192                                                  <&clks IMX6SLL_CLK_ECSPI1>;
 193                                         clock-names = "ipg", "per";
 194                                         status = "disabled";
 195                                 };
 196
 197                                 ecspi2: spi@200c000 {
 198                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 199                                         reg = <0x0200c000 0x4000>;
 200                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 201                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 202                                         dma-names = "rx", "tx";
 203                                         clocks = <&clks IMX6SLL_CLK_ECSPI2>,
 204                                                  <&clks IMX6SLL_CLK_ECSPI2>;
 205                                         clock-names = "ipg", "per";
 206                                         status = "disabled";
 207                                 };
 208
 209                                 ecspi3: spi@2010000 {
 210                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 211                                         reg = <0x02010000 0x4000>;
 212                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 213                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 214                                         dma-names = "rx", "tx";
 215                                         clocks = <&clks IMX6SLL_CLK_ECSPI3>,
 216                                                  <&clks IMX6SLL_CLK_ECSPI3>;
 217                                         clock-names = "ipg", "per";
 218                                         status = "disabled";
 219                                 };
 220
 221                                 ecspi4: spi@2014000 {
 222                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 223                                         reg = <0x02014000 0x4000>;
 224                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 225                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 226                                         dma-names = "rx", "tx";
 227                                         clocks = <&clks IMX6SLL_CLK_ECSPI4>,
 228                                                  <&clks IMX6SLL_CLK_ECSPI4>;
 229                                         clock-names = "ipg", "per";
 230                                         status = "disabled";
 231                                 };
 232
 233                                 uart4: serial@2018000 {
 234                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 235                                                      "fsl,imx21-uart";
 236                                         reg = <0x02018000 0x4000>;
 237                                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 238                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 239                                         dma-names = "rx", "tx";
 240                                         clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
 241                                                  <&clks IMX6SLL_CLK_UART4_SERIAL>;
 242                                         clock-names = "ipg", "per";
 243                                         status = "disabled";
 244                                 };
 245
 246                                 uart1: serial@2020000 {
 247                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 248                                                      "fsl,imx21-uart";
 249                                         reg = <0x02020000 0x4000>;
 250                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 251                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 252                                         dma-names = "rx", "tx";
 253                                         clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
 254                                                  <&clks IMX6SLL_CLK_UART1_SERIAL>;
 255                                         clock-names = "ipg", "per";
 256                                         status = "disabled";
 257                                 };
 258
 259                                 uart2: serial@2024000 {
 260                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 261                                                      "fsl,imx21-uart";
 262                                         reg = <0x02024000 0x4000>;
 263                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 264                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 265                                         dma-names = "rx", "tx";
 266                                         clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
 267                                                  <&clks IMX6SLL_CLK_UART2_SERIAL>;
 268                                         clock-names = "ipg", "per";
 269                                         status = "disabled";
 270                                 };
 271
 272                                 ssi1: ssi-controller@2028000 {
 273                                         compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 274                                         reg = <0x02028000 0x4000>;
 275                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 276                                         dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
 277                                         dma-names = "rx", "tx";
 278                                         fsl,fifo-depth = <15>;
 279                                         clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
 280                                                  <&clks IMX6SLL_CLK_SSI1>;
 281                                         clock-names = "ipg", "baud";
 282                                         status = "disabled";
 283                                 };
 284
 285                                 ssi2: ssi-controller@202c000 {
 286                                         compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 287                                         reg = <0x0202c000 0x4000>;
 288                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 289                                         dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
 290                                         dma-names = "rx", "tx";
 291                                         fsl,fifo-depth = <15>;
 292                                         clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
 293                                                  <&clks IMX6SLL_CLK_SSI2>;
 294                                         clock-names = "ipg", "baud";
 295                                         status = "disabled";
 296                                 };
 297
 298                                 ssi3: ssi-controller@2030000 {
 299                                         compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 300                                         reg = <0x02030000 0x4000>;
 301                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 302                                         dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
 303                                         dma-names = "rx", "tx";
 304                                         fsl,fifo-depth = <15>;
 305                                         clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
 306                                                  <&clks IMX6SLL_CLK_SSI3>;
 307                                         clock-names = "ipg", "baud";
 308                                         status = "disabled";
 309                                 };
 310
 311                                 uart3: serial@2034000 {
 312                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 313                                                      "fsl,imx21-uart";
 314                                         reg = <0x02034000 0x4000>;
 315                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 316                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 317                                         dma-name = "rx", "tx";
 318                                         clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
 319                                                  <&clks IMX6SLL_CLK_UART3_SERIAL>;
 320                                         clock-names = "ipg", "per";
 321                                         status = "disabled";
 322                                 };
 323                         };
 324
 325                         pwm1: pwm@2080000 {
 326                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 327                                 reg = <0x02080000 0x4000>;
 328                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 329                                 clocks = <&clks IMX6SLL_CLK_PWM1>,
 330                                          <&clks IMX6SLL_CLK_PWM1>;
 331                                 clock-names = "ipg", "per";
 332                                 #pwm-cells = <2>;
 333                         };
 334
 335                         pwm2: pwm@2084000 {
 336                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 337                                 reg = <0x02084000 0x4000>;
 338                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 339                                 clocks = <&clks IMX6SLL_CLK_PWM2>,
 340                                          <&clks IMX6SLL_CLK_PWM2>;
 341                                 clock-names = "ipg", "per";
 342                                 #pwm-cells = <2>;
 343                         };
 344
 345                         pwm3: pwm@2088000 {
 346                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 347                                 reg = <0x02088000 0x4000>;
 348                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 349                                 clocks = <&clks IMX6SLL_CLK_PWM3>,
 350                                          <&clks IMX6SLL_CLK_PWM3>;
 351                                 clock-names = "ipg", "per";
 352                                 #pwm-cells = <2>;
 353                         };
 354
 355                         pwm4: pwm@208c000 {
 356                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 357                                 reg = <0x0208c000 0x4000>;
 358                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 359                                 clocks = <&clks IMX6SLL_CLK_PWM4>,
 360                                          <&clks IMX6SLL_CLK_PWM4>;
 361                                 clock-names = "ipg", "per";
 362                                 #pwm-cells = <2>;
 363                         };
 364
 365                         gpt1: timer@2098000 {
 366                                 compatible = "fsl,imx6sl-gpt";
 367                                 reg = <0x02098000 0x4000>;
 368                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 369                                 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
 370                                          <&clks IMX6SLL_CLK_GPT_SERIAL>;
 371                                 clock-names = "ipg", "per";
 372                         };
 373
 374                         gpio1: gpio@209c000 {
 375                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 376                                 reg = <0x0209c000 0x4000>;
 377                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 378                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 379                                 clocks = <&clks IMX6SLL_CLK_GPIO1>;
 380                                 gpio-controller;
 381                                 #gpio-cells = <2>;
 382                                 interrupt-controller;
 383                                 #interrupt-cells = <2>;
 384                                 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
 385                         };
 386
 387                         gpio2: gpio@20a0000 {
 388                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 389                                 reg = <0x020a0000 0x4000>;
 390                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 391                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 392                                 clocks = <&clks IMX6SLL_CLK_GPIO2>;
 393                                 gpio-controller;
 394                                 #gpio-cells = <2>;
 395                                 interrupt-controller;
 396                                 #interrupt-cells = <2>;
 397                                 gpio-ranges = <&iomuxc 0 50 32>;
 398                         };
 399
 400                         gpio3: gpio@20a4000 {
 401                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 402                                 reg = <0x020a4000 0x4000>;
 403                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 404                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 405                                 clocks = <&clks IMX6SLL_CLK_GPIO3>;
 406                                 gpio-controller;
 407                                 #gpio-cells = <2>;
 408                                 interrupt-controller;
 409                                 #interrupt-cells = <2>;
 410                                 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
 411                                               <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
 412                                               <&iomuxc 21 6 11>;
 413                         };
 414
 415                         gpio4: gpio@20a8000 {
 416                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 417                                 reg = <0x020a8000 0x4000>;
 418                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 419                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 420                                 clocks = <&clks IMX6SLL_CLK_GPIO4>;
 421                                 gpio-controller;
 422                                 #gpio-cells = <2>;
 423                                 interrupt-controller;
 424                                 #interrupt-cells = <2>;
 425                                 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
 426                                               <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
 427                                               <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
 428                                               <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
 429                                               <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
 430                                               <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
 431                                               <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
 432                                               <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
 433                                               <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
 434                         };
 435
 436                         gpio5: gpio@20ac000 {
 437                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 438                                 reg = <0x020ac000 0x4000>;
 439                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 440                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 441                                 clocks = <&clks IMX6SLL_CLK_GPIO5>;
 442                                 gpio-controller;
 443                                 #gpio-cells = <2>;
 444                                 interrupt-controller;
 445                                 #interrupt-cells = <2>;
 446                                 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
 447                                               <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
 448                                               <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
 449                                               <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
 450                                               <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
 451                                               <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
 452                                               <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
 453                                               <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
 454                                               <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
 455                                               <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
 456                                               <&iomuxc 21 137 1>;
 457                         };
 458
 459                         gpio6: gpio@20b0000 {
 460                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 461                                 reg = <0x020b0000 0x4000>;
 462                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 463                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 464                                 clocks = <&clks IMX6SLL_CLK_GPIO6>;
 465                                 gpio-controller;
 466                                 #gpio-cells = <2>;
 467                                 interrupt-controller;
 468                                 #interrupt-cells = <2>;
 469                         };
 470
 471                         kpp: keypad@20b8000 {
 472                                 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
 473                                 reg = <0x020b8000 0x4000>;
 474                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 475                                 clocks = <&clks IMX6SLL_CLK_KPP>;
 476                                 status = "disabled";
 477                         };
 478
 479                         wdog1: watchdog@20bc000 {
 480                                 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
 481                                 reg = <0x020bc000 0x4000>;
 482                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 483                                 clocks = <&clks IMX6SLL_CLK_WDOG1>;
 484                         };
 485
 486                         wdog2: watchdog@20c0000 {
 487                                 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
 488                                 reg = <0x020c0000 0x4000>;
 489                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 490                                 clocks = <&clks IMX6SLL_CLK_WDOG2>;
 491                                 status = "disabled";
 492                         };
 493
 494                         clks: clock-controller@20c4000 {
 495                                 compatible = "fsl,imx6sll-ccm";
 496                                 reg = <0x020c4000 0x4000>;
 497                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 498                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 499                                 #clock-cells = <1>;
 500                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 501                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 502
 503                                 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
 504                                 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
 505                         };
 506
 507                         anatop: anatop@20c8000 {
 508                                 compatible = "fsl,imx6sll-anatop",
 509                                              "fsl,imx6q-anatop",
 510                                              "syscon", "simple-bus";
 511                                 reg = <0x020c8000 0x4000>;
 512                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 513                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 514                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 515                                 #address-cells = <1>;
 516                                 #size-cells = <0>;
 517
 518                                 reg_3p0: regulator-3p0@20c8120 {
 519                                         compatible = "fsl,anatop-regulator";
 520                                         reg = <0x20c8120>;
 521                                         regulator-name = "vdd3p0";
 522                                         regulator-min-microvolt = <2625000>;
 523                                         regulator-max-microvolt = <3400000>;
 524                                         anatop-reg-offset = <0x120>;
 525                                         anatop-vol-bit-shift = <8>;
 526                                         anatop-vol-bit-width = <5>;
 527                                         anatop-min-bit-val = <0>;
 528                                         anatop-min-voltage = <2625000>;
 529                                         anatop-max-voltage = <3400000>;
 530                                         anatop-enable-bit = <0>;
 531                                 };
 532                         };
 533
 534                         usbphy1: usb-phy@20c9000 {
 535                                 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
 536                                                 "fsl,imx23-usbphy";
 537                                 reg = <0x020c9000 0x1000>;
 538                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 539                                 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
 540                                 phy-3p0-supply = <&reg_3p0>;
 541                                 fsl,anatop = <&anatop>;
 542                         };
 543
 544                         usbphy2: usb-phy@20ca000 {
 545                                 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
 546                                                 "fsl,imx23-usbphy";
 547                                 reg = <0x020ca000 0x1000>;
 548                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 549                                 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
 550                                 phy-reg_3p0-supply = <&reg_3p0>;
 551                                 fsl,anatop = <&anatop>;
 552                         };
 553
 554                         snvs: snvs@20cc000 {
 555                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 556                                 reg = <0x020cc000 0x4000>;
 557
 558                                 snvs_rtc: snvs-rtc-lp {
 559                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 560                                         regmap = <&snvs>;
 561                                         offset = <0x34>;
 562                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 563                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 564                                 };
 565
 566                                 snvs_poweroff: snvs-poweroff {
 567                                         compatible = "syscon-poweroff";
 568                                         regmap = <&snvs>;
 569                                         offset = <0x38>;
 570                                         mask = <0x61>;
 571                                         status = "disabled";
 572                                 };
 573
 574                                 snvs_pwrkey: snvs-powerkey {
 575                                         compatible = "fsl,sec-v4.0-pwrkey";
 576                                         regmap = <&snvs>;
 577                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 578                                         linux,keycode = <KEY_POWER>;
 579                                         wakeup-source;
 580                                         status = "disabled";
 581                                 };
 582                         };
 583
 584                         src: reset-controller@20d8000 {
 585                                 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
 586                                 reg = <0x020d8000 0x4000>;
 587                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 588                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 589                                 #reset-cells = <1>;
 590                         };
 591
 592                         gpc: interrupt-controller@20dc000 {
 593                                 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
 594                                 reg = <0x020dc000 0x4000>;
 595                                 interrupt-controller;
 596                                 #interrupt-cells = <3>;
 597                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 598                                 interrupt-parent = <&intc>;
 599                         };
 600
 601                         iomuxc: pinctrl@20e0000 {
 602                                 compatible = "fsl,imx6sll-iomuxc";
 603                                 reg = <0x020e0000 0x4000>;
 604                         };
 605
 606                         gpr: iomuxc-gpr@20e4000 {
 607                                 compatible = "fsl,imx6sll-iomuxc-gpr",
 608                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 609                                 reg = <0x020e4000 0x4000>;
 610                         };
 611
 612                         csi: csi@20e8000 {
 613                                 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
 614                                 reg = <0x020e8000 0x4000>;
 615                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 616                                 clocks = <&clks IMX6SLL_CLK_DUMMY>,
 617                                          <&clks IMX6SLL_CLK_CSI>,
 618                                          <&clks IMX6SLL_CLK_DUMMY>;
 619                                 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
 620                                 status = "disabled";
 621                         };
 622
 623                         sdma: dma-controller@20ec000 {
 624                                 compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
 625                                 reg = <0x020ec000 0x4000>;
 626                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 627                                 clocks = <&clks IMX6SLL_CLK_IPG>,
 628                                          <&clks IMX6SLL_CLK_SDMA>;
 629                                 clock-names = "ipg", "ahb";
 630                                 #dma-cells = <3>;
 631                                 iram = <&ocram>;
 632                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 633                         };
 634
 635                         lcdif: lcd-controller@20f8000 {
 636                                 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
 637                                 reg = <0x020f8000 0x4000>;
 638                                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 639                                 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
 640                                          <&clks IMX6SLL_CLK_LCDIF_APB>,
 641                                          <&clks IMX6SLL_CLK_DUMMY>;
 642                                 clock-names = "pix", "axi", "disp_axi";
 643                                 status = "disabled";
 644                         };
 645
 646                         dcp: dcp@20fc000 {
 647                                 compatible = "fsl,imx28-dcp";
 648                                 reg = <0x020fc000 0x4000>;
 649                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 650                                              <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 651                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 652                                 clocks = <&clks IMX6SLL_CLK_DCP>;
 653                                 clock-names = "dcp";
 654                         };
 655                 };
 656
 657                 aips2: aips-bus@2100000 {
 658                         compatible = "fsl,aips-bus", "simple-bus";
 659                         #address-cells = <1>;
 660                         #size-cells = <1>;
 661                         reg = <0x02100000 0x100000>;
 662                         ranges;
 663
 664                         usbotg1: usb@2184000 {
 665                                 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
 666                                                 "fsl,imx27-usb";
 667                                 reg = <0x02184000 0x200>;
 668                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 669                                 clocks = <&clks IMX6SLL_CLK_USBOH3>;
 670                                 fsl,usbphy = <&usbphy1>;
 671                                 fsl,usbmisc = <&usbmisc 0>;
 672                                 fsl,anatop = <&anatop>;
 673                                 ahb-burst-config = <0x0>;
 674                                 tx-burst-size-dword = <0x10>;
 675                                 rx-burst-size-dword = <0x10>;
 676                                 status = "disabled";
 677                         };
 678
 679                         usbotg2: usb@2184200 {
 680                                 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
 681                                                 "fsl,imx27-usb";
 682                                 reg = <0x02184200 0x200>;
 683                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 684                                 clocks = <&clks IMX6SLL_CLK_USBOH3>;
 685                                 fsl,usbphy = <&usbphy2>;
 686                                 fsl,usbmisc = <&usbmisc 1>;
 687                                 ahb-burst-config = <0x0>;
 688                                 tx-burst-size-dword = <0x10>;
 689                                 rx-burst-size-dword = <0x10>;
 690                                 status = "disabled";
 691                         };
 692
 693                         usbmisc: usbmisc@2184800 {
 694                                 #index-cells = <1>;
 695                                 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
 696                                                 "fsl,imx6q-usbmisc";
 697                                 reg = <0x02184800 0x200>;
 698                         };
 699
 700                         usdhc1: mmc@2190000 {
 701                                 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 702                                 reg = <0x02190000 0x4000>;
 703                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 704                                 clocks = <&clks IMX6SLL_CLK_USDHC1>,
 705                                          <&clks IMX6SLL_CLK_USDHC1>,
 706                                          <&clks IMX6SLL_CLK_USDHC1>;
 707                                 clock-names = "ipg", "ahb", "per";
 708                                 bus-width = <4>;
 709                                 fsl,tuning-step = <2>;
 710                                 fsl,tuning-start-tap = <20>;
 711                                 status = "disabled";
 712                         };
 713
 714                         usdhc2: mmc@2194000 {
 715                                 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 716                                 reg = <0x02194000 0x4000>;
 717                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 718                                 clocks = <&clks IMX6SLL_CLK_USDHC2>,
 719                                          <&clks IMX6SLL_CLK_USDHC2>,
 720                                          <&clks IMX6SLL_CLK_USDHC2>;
 721                                 clock-names = "ipg", "ahb", "per";
 722                                 bus-width = <4>;
 723                                 fsl,tuning-step = <2>;
 724                                 fsl,tuning-start-tap = <20>;
 725                                 status = "disabled";
 726                         };
 727
 728                         usdhc3: mmc@2198000 {
 729                                 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 730                                 reg = <0x02198000 0x4000>;
 731                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 732                                 clocks = <&clks IMX6SLL_CLK_USDHC3>,
 733                                          <&clks IMX6SLL_CLK_USDHC3>,
 734                                          <&clks IMX6SLL_CLK_USDHC3>;
 735                                 clock-names = "ipg", "ahb", "per";
 736                                 bus-width = <4>;
 737                                 fsl,tuning-step = <2>;
 738                                 fsl,tuning-start-tap = <20>;
 739                                 status = "disabled";
 740                         };
 741
 742                         i2c1: i2c@21a0000 {
 743                                 #address-cells = <1>;
 744                                 #size-cells = <0>;
 745                                 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
 746                                 reg = <0x021a0000 0x4000>;
 747                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 748                                 clocks = <&clks IMX6SLL_CLK_I2C1>;
 749                                 status = "disabled";
 750                         };
 751
 752                         i2c2: i2c@21a4000 {
 753                                 #address-cells = <1>;
 754                                 #size-cells = <0>;
 755                                 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
 756                                 reg = <0x021a4000 0x4000>;
 757                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 758                                 clocks = <&clks IMX6SLL_CLK_I2C2>;
 759                                 status = "disabled";
 760                         };
 761
 762                         i2c3: i2c@21a8000 {
 763                                 #address-cells = <1>;
 764                                 #size-cells = <0>;
 765                                 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
 766                                 reg = <0x021a8000 0x4000>;
 767                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 768                                 clocks = <&clks IMX6SLL_CLK_I2C3>;
 769                                 status = "disabled";
 770                         };
 771
 772                         mmdc: memory-controller@21b0000 {
 773                                 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
 774                                 reg = <0x021b0000 0x4000>;
 775                                 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
 776                         };
 777
 778                         ocotp: ocotp-ctrl@21bc000 {
 779                                 #address-cells = <1>;
 780                                 #size-cells = <1>;
 781                                 compatible = "fsl,imx6sll-ocotp", "syscon";
 782                                 reg = <0x021bc000 0x4000>;
 783                                 clocks = <&clks IMX6SLL_CLK_OCOTP>;
 784
 785                                 tempmon_calib: calib@38 {
 786                                         reg = <0x38 4>;
 787                                 };
 788
 789                                 tempmon_temp_grade: temp-grade@20 {
 790                                         reg = <0x20 4>;
 791                                 };
 792                         };
 793
 794                         audmux: audmux@21d8000 {
 795                                 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
 796                                 reg = <0x021d8000 0x4000>;
 797                                 status = "disabled";
 798                         };
 799
 800                         uart5: serial@21f4000 {
 801                                 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
 802                                              "fsl,imx21-uart";
 803                                 reg = <0x021f4000 0x4000>;
 804                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 805                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 806                                 dma-names = "rx", "tx";
 807                                 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
 808                                          <&clks IMX6SLL_CLK_UART5_SERIAL>;
 809                                 clock-names = "ipg", "per";
 810                                 status = "disabled";
 811                         };
 812                 };
 813         };
 814 };