arch/arm/boot/dts/imx6sl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6sl-pinfunc.h"
   7 #include <dt-bindings/clock/imx6sl-clock.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         /*
  13          * The decompressor and also some bootloaders rely on a
  14          * pre-existing /chosen node to be available to insert the
  15          * command line and merge other ATAGS info.
  16          * Also for U-Boot there must be a pre-existing /memory node.
  17          */
  18         chosen {};
  19         memory { device_type = "memory"; };
  20
  21         aliases {
  22                 ethernet0 = &fec;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 spi0 = &ecspi1;
  34                 spi1 = &ecspi2;
  35                 spi2 = &ecspi3;
  36                 spi3 = &ecspi4;
  37                 usbphy0 = &usbphy1;
  38                 usbphy1 = &usbphy2;
  39         };
  40
  41         cpus {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 cpu@0 {
  46                         compatible = "arm,cortex-a9";
  47                         device_type = "cpu";
  48                         reg = <0x0>;
  49                         next-level-cache = <&L2>;
  50                         operating-points = <
  51                                 /* kHz    uV */
  52                                 996000  1275000
  53                                 792000  1175000
  54                                 396000  975000
  55                         >;
  56                         fsl,soc-operating-points = <
  57                                 /* ARM kHz      SOC-PU uV */
  58                                 996000          1225000
  59                                 792000          1175000
  60                                 396000          1175000
  61                         >;
  62                         clock-latency = <61036>; /* two CLK32 periods */
  63                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  64                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  65                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  66                         clock-names = "arm", "pll2_pfd2_396m", "step",
  67                                       "pll1_sw", "pll1_sys";
  68                         arm-supply = <&reg_arm>;
  69                         pu-supply = <&reg_pu>;
  70                         soc-supply = <&reg_soc>;
  71                 };
  72         };
  73
  74         intc: interrupt-controller@a01000 {
  75                 compatible = "arm,cortex-a9-gic";
  76                 #interrupt-cells = <3>;
  77                 interrupt-controller;
  78                 reg = <0x00a01000 0x1000>,
  79                       <0x00a00100 0x100>;
  80                 interrupt-parent = <&intc>;
  81         };
  82
  83         clocks {
  84                 ckil {
  85                         compatible = "fixed-clock";
  86                         #clock-cells = <0>;
  87                         clock-frequency = <32768>;
  88                 };
  89
  90                 osc {
  91                         compatible = "fixed-clock";
  92                         #clock-cells = <0>;
  93                         clock-frequency = <24000000>;
  94                 };
  95         };
  96
  97         tempmon: tempmon {
  98                 compatible = "fsl,imx6q-tempmon";
  99                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 100                 interrupt-parent = <&gpc>;
 101                 fsl,tempmon = <&anatop>;
 102                 fsl,tempmon-data = <&ocotp>;
 103                 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 104         };
 105
 106         pmu {
 107                 compatible = "arm,cortex-a9-pmu";
 108                 interrupt-parent = <&gpc>;
 109                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 110         };
 111
 112         soc {
 113                 #address-cells = <1>;
 114                 #size-cells = <1>;
 115                 compatible = "simple-bus";
 116                 interrupt-parent = <&gpc>;
 117                 ranges;
 118
 119                 ocram: sram@900000 {
 120                         compatible = "mmio-sram";
 121                         reg = <0x00900000 0x20000>;
 122                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 123                 };
 124
 125                 L2: l2-cache@a02000 {
 126                         compatible = "arm,pl310-cache";
 127                         reg = <0x00a02000 0x1000>;
 128                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 129                         cache-unified;
 130                         cache-level = <2>;
 131                         arm,tag-latency = <4 2 3>;
 132                         arm,data-latency = <4 2 3>;
 133                 };
 134
 135                 aips1: aips-bus@2000000 {
 136                         compatible = "fsl,aips-bus", "simple-bus";
 137                         #address-cells = <1>;
 138                         #size-cells = <1>;
 139                         reg = <0x02000000 0x100000>;
 140                         ranges;
 141
 142                         spba: spba-bus@2000000 {
 143                                 compatible = "fsl,spba-bus", "simple-bus";
 144                                 #address-cells = <1>;
 145                                 #size-cells = <1>;
 146                                 reg = <0x02000000 0x40000>;
 147                                 ranges;
 148
 149                                 spdif: spdif@2004000 {
 150                                         compatible = "fsl,imx6sl-spdif",
 151                                                 "fsl,imx35-spdif";
 152                                         reg = <0x02004000 0x4000>;
 153                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 154                                         dmas = <&sdma 14 18 0>,
 155                                                 <&sdma 15 18 0>;
 156                                         dma-names = "rx", "tx";
 157                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 158                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 159                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 160                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 161                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 162                                         clock-names = "core", "rxtx0",
 163                                                 "rxtx1", "rxtx2",
 164                                                 "rxtx3", "rxtx4",
 165                                                 "rxtx5", "rxtx6",
 166                                                 "rxtx7", "spba";
 167                                         status = "disabled";
 168                                 };
 169
 170                                 ecspi1: ecspi@2008000 {
 171                                         #address-cells = <1>;
 172                                         #size-cells = <0>;
 173                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 174                                         reg = <0x02008000 0x4000>;
 175                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 176                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 177                                                  <&clks IMX6SL_CLK_ECSPI1>;
 178                                         clock-names = "ipg", "per";
 179                                         status = "disabled";
 180                                 };
 181
 182                                 ecspi2: ecspi@200c000 {
 183                                         #address-cells = <1>;
 184                                         #size-cells = <0>;
 185                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 186                                         reg = <0x0200c000 0x4000>;
 187                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 188                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 189                                                  <&clks IMX6SL_CLK_ECSPI2>;
 190                                         clock-names = "ipg", "per";
 191                                         status = "disabled";
 192                                 };
 193
 194                                 ecspi3: ecspi@2010000 {
 195                                         #address-cells = <1>;
 196                                         #size-cells = <0>;
 197                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 198                                         reg = <0x02010000 0x4000>;
 199                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 200                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 201                                                  <&clks IMX6SL_CLK_ECSPI3>;
 202                                         clock-names = "ipg", "per";
 203                                         status = "disabled";
 204                                 };
 205
 206                                 ecspi4: ecspi@2014000 {
 207                                         #address-cells = <1>;
 208                                         #size-cells = <0>;
 209                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 210                                         reg = <0x02014000 0x4000>;
 211                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 212                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 213                                                  <&clks IMX6SL_CLK_ECSPI4>;
 214                                         clock-names = "ipg", "per";
 215                                         status = "disabled";
 216                                 };
 217
 218                                 uart5: serial@2018000 {
 219                                         compatible = "fsl,imx6sl-uart",
 220                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 221                                         reg = <0x02018000 0x4000>;
 222                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 223                                         clocks = <&clks IMX6SL_CLK_UART>,
 224                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 225                                         clock-names = "ipg", "per";
 226                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 227                                         dma-names = "rx", "tx";
 228                                         status = "disabled";
 229                                 };
 230
 231                                 uart1: serial@2020000 {
 232                                         compatible = "fsl,imx6sl-uart",
 233                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 234                                         reg = <0x02020000 0x4000>;
 235                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 236                                         clocks = <&clks IMX6SL_CLK_UART>,
 237                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 238                                         clock-names = "ipg", "per";
 239                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 240                                         dma-names = "rx", "tx";
 241                                         status = "disabled";
 242                                 };
 243
 244                                 uart2: serial@2024000 {
 245                                         compatible = "fsl,imx6sl-uart",
 246                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 247                                         reg = <0x02024000 0x4000>;
 248                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 249                                         clocks = <&clks IMX6SL_CLK_UART>,
 250                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 251                                         clock-names = "ipg", "per";
 252                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 253                                         dma-names = "rx", "tx";
 254                                         status = "disabled";
 255                                 };
 256
 257                                 ssi1: ssi@2028000 {
 258                                         #sound-dai-cells = <0>;
 259                                         compatible = "fsl,imx6sl-ssi",
 260                                                         "fsl,imx51-ssi";
 261                                         reg = <0x02028000 0x4000>;
 262                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 263                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 264                                                  <&clks IMX6SL_CLK_SSI1>;
 265                                         clock-names = "ipg", "baud";
 266                                         dmas = <&sdma 37 1 0>,
 267                                                <&sdma 38 1 0>;
 268                                         dma-names = "rx", "tx";
 269                                         fsl,fifo-depth = <15>;
 270                                         status = "disabled";
 271                                 };
 272
 273                                 ssi2: ssi@202c000 {
 274                                         #sound-dai-cells = <0>;
 275                                         compatible = "fsl,imx6sl-ssi",
 276                                                         "fsl,imx51-ssi";
 277                                         reg = <0x0202c000 0x4000>;
 278                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 279                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 280                                                  <&clks IMX6SL_CLK_SSI2>;
 281                                         clock-names = "ipg", "baud";
 282                                         dmas = <&sdma 41 1 0>,
 283                                                <&sdma 42 1 0>;
 284                                         dma-names = "rx", "tx";
 285                                         fsl,fifo-depth = <15>;
 286                                         status = "disabled";
 287                                 };
 288
 289                                 ssi3: ssi@2030000 {
 290                                         #sound-dai-cells = <0>;
 291                                         compatible = "fsl,imx6sl-ssi",
 292                                                         "fsl,imx51-ssi";
 293                                         reg = <0x02030000 0x4000>;
 294                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 295                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 296                                                  <&clks IMX6SL_CLK_SSI3>;
 297                                         clock-names = "ipg", "baud";
 298                                         dmas = <&sdma 45 1 0>,
 299                                                <&sdma 46 1 0>;
 300                                         dma-names = "rx", "tx";
 301                                         fsl,fifo-depth = <15>;
 302                                         status = "disabled";
 303                                 };
 304
 305                                 uart3: serial@2034000 {
 306                                         compatible = "fsl,imx6sl-uart",
 307                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 308                                         reg = <0x02034000 0x4000>;
 309                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 310                                         clocks = <&clks IMX6SL_CLK_UART>,
 311                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 312                                         clock-names = "ipg", "per";
 313                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 314                                         dma-names = "rx", "tx";
 315                                         status = "disabled";
 316                                 };
 317
 318                                 uart4: serial@2038000 {
 319                                         compatible = "fsl,imx6sl-uart",
 320                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 321                                         reg = <0x02038000 0x4000>;
 322                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 323                                         clocks = <&clks IMX6SL_CLK_UART>,
 324                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 325                                         clock-names = "ipg", "per";
 326                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 327                                         dma-names = "rx", "tx";
 328                                         status = "disabled";
 329                                 };
 330                         };
 331
 332                         pwm1: pwm@2080000 {
 333                                 #pwm-cells = <2>;
 334                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 335                                 reg = <0x02080000 0x4000>;
 336                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 337                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 338                                          <&clks IMX6SL_CLK_PWM1>;
 339                                 clock-names = "ipg", "per";
 340                         };
 341
 342                         pwm2: pwm@2084000 {
 343                                 #pwm-cells = <2>;
 344                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 345                                 reg = <0x02084000 0x4000>;
 346                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 347                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 348                                          <&clks IMX6SL_CLK_PWM2>;
 349                                 clock-names = "ipg", "per";
 350                         };
 351
 352                         pwm3: pwm@2088000 {
 353                                 #pwm-cells = <2>;
 354                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 355                                 reg = <0x02088000 0x4000>;
 356                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 357                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 358                                          <&clks IMX6SL_CLK_PWM3>;
 359                                 clock-names = "ipg", "per";
 360                         };
 361
 362                         pwm4: pwm@208c000 {
 363                                 #pwm-cells = <2>;
 364                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 365                                 reg = <0x0208c000 0x4000>;
 366                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 367                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 368                                          <&clks IMX6SL_CLK_PWM4>;
 369                                 clock-names = "ipg", "per";
 370                         };
 371
 372                         gpt: gpt@2098000 {
 373                                 compatible = "fsl,imx6sl-gpt";
 374                                 reg = <0x02098000 0x4000>;
 375                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 376                                 clocks = <&clks IMX6SL_CLK_GPT>,
 377                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 378                                 clock-names = "ipg", "per";
 379                         };
 380
 381                         gpio1: gpio@209c000 {
 382                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 383                                 reg = <0x0209c000 0x4000>;
 384                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 385                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 386                                 gpio-controller;
 387                                 #gpio-cells = <2>;
 388                                 interrupt-controller;
 389                                 #interrupt-cells = <2>;
 390                                 gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
 391                                               <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
 392                                               <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
 393                                               <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
 394                                               <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
 395                                               <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
 396                         };
 397
 398                         gpio2: gpio@20a0000 {
 399                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 400                                 reg = <0x020a0000 0x4000>;
 401                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 402                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 403                                 gpio-controller;
 404                                 #gpio-cells = <2>;
 405                                 interrupt-controller;
 406                                 #interrupt-cells = <2>;
 407                                 gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
 408                                               <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
 409                                               <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
 410                                               <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
 411                                               <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
 412                                               <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
 413                                               <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
 414                         };
 415
 416                         gpio3: gpio@20a4000 {
 417                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 418                                 reg = <0x020a4000 0x4000>;
 419                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 420                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 421                                 gpio-controller;
 422                                 #gpio-cells = <2>;
 423                                 interrupt-controller;
 424                                 #interrupt-cells = <2>;
 425                                 gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
 426                                               <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
 427                                               <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
 428                                               <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
 429                                               <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
 430                                               <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
 431                                               <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
 432                                               <&iomuxc 31 102 1>;
 433                         };
 434
 435                         gpio4: gpio@20a8000 {
 436                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 437                                 reg = <0x020a8000 0x4000>;
 438                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 439                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 440                                 gpio-controller;
 441                                 #gpio-cells = <2>;
 442                                 interrupt-controller;
 443                                 #interrupt-cells = <2>;
 444                                 gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
 445                                               <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
 446                                               <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
 447                                               <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
 448                                               <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
 449                                               <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
 450                                               <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
 451                                               <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
 452                                               <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
 453                                               <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
 454                                               <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
 455                                               <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
 456                                               <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
 457                                               <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
 458                                               <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
 459                         };
 460
 461                         gpio5: gpio@20ac000 {
 462                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 463                                 reg = <0x020ac000 0x4000>;
 464                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 465                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 466                                 gpio-controller;
 467                                 #gpio-cells = <2>;
 468                                 interrupt-controller;
 469                                 #interrupt-cells = <2>;
 470                                 gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
 471                                               <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
 472                                               <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
 473                                               <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
 474                                               <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
 475                                               <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
 476                                               <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
 477                                               <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
 478                                               <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
 479                                               <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
 480                                               <&iomuxc 21 161 1>;
 481                         };
 482
 483                         kpp: kpp@20b8000 {
 484                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 485                                 reg = <0x020b8000 0x4000>;
 486                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 487                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 488                                 status = "disabled";
 489                         };
 490
 491                         wdog1: wdog@20bc000 {
 492                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 493                                 reg = <0x020bc000 0x4000>;
 494                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 495                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 496                         };
 497
 498                         wdog2: wdog@20c0000 {
 499                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 500                                 reg = <0x020c0000 0x4000>;
 501                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 502                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 503                                 status = "disabled";
 504                         };
 505
 506                         clks: ccm@20c4000 {
 507                                 compatible = "fsl,imx6sl-ccm";
 508                                 reg = <0x020c4000 0x4000>;
 509                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 510                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 511                                 #clock-cells = <1>;
 512                         };
 513
 514                         anatop: anatop@20c8000 {
 515                                 compatible = "fsl,imx6sl-anatop",
 516                                              "fsl,imx6q-anatop",
 517                                              "syscon", "simple-bus";
 518                                 reg = <0x020c8000 0x1000>;
 519                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 520                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 521                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 522
 523                                 regulator-1p1 {
 524                                         compatible = "fsl,anatop-regulator";
 525                                         regulator-name = "vdd1p1";
 526                                         regulator-min-microvolt = <800000>;
 527                                         regulator-max-microvolt = <1375000>;
 528                                         regulator-always-on;
 529                                         anatop-reg-offset = <0x110>;
 530                                         anatop-vol-bit-shift = <8>;
 531                                         anatop-vol-bit-width = <5>;
 532                                         anatop-min-bit-val = <4>;
 533                                         anatop-min-voltage = <800000>;
 534                                         anatop-max-voltage = <1375000>;
 535                                         anatop-enable-bit = <0>;
 536                                 };
 537
 538                                 regulator-3p0 {
 539                                         compatible = "fsl,anatop-regulator";
 540                                         regulator-name = "vdd3p0";
 541                                         regulator-min-microvolt = <2800000>;
 542                                         regulator-max-microvolt = <3150000>;
 543                                         regulator-always-on;
 544                                         anatop-reg-offset = <0x120>;
 545                                         anatop-vol-bit-shift = <8>;
 546                                         anatop-vol-bit-width = <5>;
 547                                         anatop-min-bit-val = <0>;
 548                                         anatop-min-voltage = <2625000>;
 549                                         anatop-max-voltage = <3400000>;
 550                                         anatop-enable-bit = <0>;
 551                                 };
 552
 553                                 regulator-2p5 {
 554                                         compatible = "fsl,anatop-regulator";
 555                                         regulator-name = "vdd2p5";
 556                                         regulator-min-microvolt = <2100000>;
 557                                         regulator-max-microvolt = <2850000>;
 558                                         regulator-always-on;
 559                                         anatop-reg-offset = <0x130>;
 560                                         anatop-vol-bit-shift = <8>;
 561                                         anatop-vol-bit-width = <5>;
 562                                         anatop-min-bit-val = <0>;
 563                                         anatop-min-voltage = <2100000>;
 564                                         anatop-max-voltage = <2850000>;
 565                                         anatop-enable-bit = <0>;
 566                                 };
 567
 568                                 reg_arm: regulator-vddcore {
 569                                         compatible = "fsl,anatop-regulator";
 570                                         regulator-name = "vddarm";
 571                                         regulator-min-microvolt = <725000>;
 572                                         regulator-max-microvolt = <1450000>;
 573                                         regulator-always-on;
 574                                         anatop-reg-offset = <0x140>;
 575                                         anatop-vol-bit-shift = <0>;
 576                                         anatop-vol-bit-width = <5>;
 577                                         anatop-delay-reg-offset = <0x170>;
 578                                         anatop-delay-bit-shift = <24>;
 579                                         anatop-delay-bit-width = <2>;
 580                                         anatop-min-bit-val = <1>;
 581                                         anatop-min-voltage = <725000>;
 582                                         anatop-max-voltage = <1450000>;
 583                                 };
 584
 585                                 reg_pu: regulator-vddpu {
 586                                         compatible = "fsl,anatop-regulator";
 587                                         regulator-name = "vddpu";
 588                                         regulator-min-microvolt = <725000>;
 589                                         regulator-max-microvolt = <1450000>;
 590                                         regulator-always-on;
 591                                         anatop-reg-offset = <0x140>;
 592                                         anatop-vol-bit-shift = <9>;
 593                                         anatop-vol-bit-width = <5>;
 594                                         anatop-delay-reg-offset = <0x170>;
 595                                         anatop-delay-bit-shift = <26>;
 596                                         anatop-delay-bit-width = <2>;
 597                                         anatop-min-bit-val = <1>;
 598                                         anatop-min-voltage = <725000>;
 599                                         anatop-max-voltage = <1450000>;
 600                                 };
 601
 602                                 reg_soc: regulator-vddsoc {
 603                                         compatible = "fsl,anatop-regulator";
 604                                         regulator-name = "vddsoc";
 605                                         regulator-min-microvolt = <725000>;
 606                                         regulator-max-microvolt = <1450000>;
 607                                         regulator-always-on;
 608                                         anatop-reg-offset = <0x140>;
 609                                         anatop-vol-bit-shift = <18>;
 610                                         anatop-vol-bit-width = <5>;
 611                                         anatop-delay-reg-offset = <0x170>;
 612                                         anatop-delay-bit-shift = <28>;
 613                                         anatop-delay-bit-width = <2>;
 614                                         anatop-min-bit-val = <1>;
 615                                         anatop-min-voltage = <725000>;
 616                                         anatop-max-voltage = <1450000>;
 617                                 };
 618                         };
 619
 620                         usbphy1: usbphy@20c9000 {
 621                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 622                                 reg = <0x020c9000 0x1000>;
 623                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 624                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 625                                 fsl,anatop = <&anatop>;
 626                         };
 627
 628                         usbphy2: usbphy@20ca000 {
 629                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 630                                 reg = <0x020ca000 0x1000>;
 631                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 632                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 633                                 fsl,anatop = <&anatop>;
 634                         };
 635
 636                         snvs: snvs@20cc000 {
 637                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 638                                 reg = <0x020cc000 0x4000>;
 639
 640                                 snvs_rtc: snvs-rtc-lp {
 641                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 642                                         regmap = <&snvs>;
 643                                         offset = <0x34>;
 644                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 645                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 646                                 };
 647
 648                                 snvs_poweroff: snvs-poweroff {
 649                                         compatible = "syscon-poweroff";
 650                                         regmap = <&snvs>;
 651                                         offset = <0x38>;
 652                                         value = <0x60>;
 653                                         mask = <0x60>;
 654                                         status = "disabled";
 655                                 };
 656                         };
 657
 658                         epit1: epit@20d0000 {
 659                                 reg = <0x020d0000 0x4000>;
 660                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 661                         };
 662
 663                         epit2: epit@20d4000 {
 664                                 reg = <0x020d4000 0x4000>;
 665                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 666                         };
 667
 668                         src: src@20d8000 {
 669                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 670                                 reg = <0x020d8000 0x4000>;
 671                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 672                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 673                                 #reset-cells = <1>;
 674                         };
 675
 676                         gpc: gpc@20dc000 {
 677                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 678                                 reg = <0x020dc000 0x4000>;
 679                                 interrupt-controller;
 680                                 #interrupt-cells = <3>;
 681                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 682                                 interrupt-parent = <&intc>;
 683                                 pu-supply = <&reg_pu>;
 684                                 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
 685                                          <&clks IMX6SL_CLK_GPU2D_PODF>;
 686                                 #power-domain-cells = <1>;
 687                         };
 688
 689                         gpr: iomuxc-gpr@20e0000 {
 690                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 691                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 692                                 reg = <0x020e0000 0x38>;
 693                         };
 694
 695                         iomuxc: iomuxc@20e0000 {
 696                                 compatible = "fsl,imx6sl-iomuxc";
 697                                 reg = <0x020e0000 0x4000>;
 698                         };
 699
 700                         csi: csi@20e4000 {
 701                                 reg = <0x020e4000 0x4000>;
 702                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 703                         };
 704
 705                         spdc: spdc@20e8000 {
 706                                 reg = <0x020e8000 0x4000>;
 707                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 708                         };
 709
 710                         sdma: sdma@20ec000 {
 711                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 712                                 reg = <0x020ec000 0x4000>;
 713                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 714                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 715                                          <&clks IMX6SL_CLK_SDMA>;
 716                                 clock-names = "ipg", "ahb";
 717                                 #dma-cells = <3>;
 718                                 /* imx6sl reuses imx6q sdma firmware */
 719                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 720                         };
 721
 722                         pxp: pxp@20f0000 {
 723                                 reg = <0x020f0000 0x4000>;
 724                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 725                         };
 726
 727                         epdc: epdc@20f4000 {
 728                                 reg = <0x020f4000 0x4000>;
 729                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 730                         };
 731
 732                         lcdif: lcdif@20f8000 {
 733                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 734                                 reg = <0x020f8000 0x4000>;
 735                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 736                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 737                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 738                                          <&clks IMX6SL_CLK_DUMMY>;
 739                                 clock-names = "pix", "axi", "disp_axi";
 740                                 status = "disabled";
 741                         };
 742
 743                         dcp: dcp@20fc000 {
 744                                 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
 745                                 reg = <0x020fc000 0x4000>;
 746                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 747                                              <0 100 IRQ_TYPE_LEVEL_HIGH>,
 748                                              <0 101 IRQ_TYPE_LEVEL_HIGH>;
 749                         };
 750                 };
 751
 752                 aips2: aips-bus@2100000 {
 753                         compatible = "fsl,aips-bus", "simple-bus";
 754                         #address-cells = <1>;
 755                         #size-cells = <1>;
 756                         reg = <0x02100000 0x100000>;
 757                         ranges;
 758
 759                         usbotg1: usb@2184000 {
 760                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 761                                 reg = <0x02184000 0x200>;
 762                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 763                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 764                                 fsl,usbphy = <&usbphy1>;
 765                                 fsl,usbmisc = <&usbmisc 0>;
 766                                 ahb-burst-config = <0x0>;
 767                                 tx-burst-size-dword = <0x10>;
 768                                 rx-burst-size-dword = <0x10>;
 769                                 status = "disabled";
 770                         };
 771
 772                         usbotg2: usb@2184200 {
 773                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 774                                 reg = <0x02184200 0x200>;
 775                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 776                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 777                                 fsl,usbphy = <&usbphy2>;
 778                                 fsl,usbmisc = <&usbmisc 1>;
 779                                 ahb-burst-config = <0x0>;
 780                                 tx-burst-size-dword = <0x10>;
 781                                 rx-burst-size-dword = <0x10>;
 782                                 status = "disabled";
 783                         };
 784
 785                         usbh: usb@2184400 {
 786                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 787                                 reg = <0x02184400 0x200>;
 788                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 789                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 790                                 fsl,usbmisc = <&usbmisc 2>;
 791                                 dr_mode = "host";
 792                                 ahb-burst-config = <0x0>;
 793                                 tx-burst-size-dword = <0x10>;
 794                                 rx-burst-size-dword = <0x10>;
 795                                 status = "disabled";
 796                         };
 797
 798                         usbmisc: usbmisc@2184800 {
 799                                 #index-cells = <1>;
 800                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 801                                 reg = <0x02184800 0x200>;
 802                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 803                         };
 804
 805                         fec: ethernet@2188000 {
 806                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 807                                 reg = <0x02188000 0x4000>;
 808                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 809                                 clocks = <&clks IMX6SL_CLK_ENET>,
 810                                          <&clks IMX6SL_CLK_ENET_REF>;
 811                                 clock-names = "ipg", "ahb";
 812                                 status = "disabled";
 813                         };
 814
 815                         usdhc1: usdhc@2190000 {
 816                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 817                                 reg = <0x02190000 0x4000>;
 818                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 819                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 820                                          <&clks IMX6SL_CLK_USDHC1>,
 821                                          <&clks IMX6SL_CLK_USDHC1>;
 822                                 clock-names = "ipg", "ahb", "per";
 823                                 bus-width = <4>;
 824                                 status = "disabled";
 825                         };
 826
 827                         usdhc2: usdhc@2194000 {
 828                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 829                                 reg = <0x02194000 0x4000>;
 830                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 831                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 832                                          <&clks IMX6SL_CLK_USDHC2>,
 833                                          <&clks IMX6SL_CLK_USDHC2>;
 834                                 clock-names = "ipg", "ahb", "per";
 835                                 bus-width = <4>;
 836                                 status = "disabled";
 837                         };
 838
 839                         usdhc3: usdhc@2198000 {
 840                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 841                                 reg = <0x02198000 0x4000>;
 842                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 843                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 844                                          <&clks IMX6SL_CLK_USDHC3>,
 845                                          <&clks IMX6SL_CLK_USDHC3>;
 846                                 clock-names = "ipg", "ahb", "per";
 847                                 bus-width = <4>;
 848                                 status = "disabled";
 849                         };
 850
 851                         usdhc4: usdhc@219c000 {
 852                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 853                                 reg = <0x0219c000 0x4000>;
 854                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 855                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 856                                          <&clks IMX6SL_CLK_USDHC4>,
 857                                          <&clks IMX6SL_CLK_USDHC4>;
 858                                 clock-names = "ipg", "ahb", "per";
 859                                 bus-width = <4>;
 860                                 status = "disabled";
 861                         };
 862
 863                         i2c1: i2c@21a0000 {
 864                                 #address-cells = <1>;
 865                                 #size-cells = <0>;
 866                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 867                                 reg = <0x021a0000 0x4000>;
 868                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 869                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 870                                 status = "disabled";
 871                         };
 872
 873                         i2c2: i2c@21a4000 {
 874                                 #address-cells = <1>;
 875                                 #size-cells = <0>;
 876                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 877                                 reg = <0x021a4000 0x4000>;
 878                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 879                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 880                                 status = "disabled";
 881                         };
 882
 883                         i2c3: i2c@21a8000 {
 884                                 #address-cells = <1>;
 885                                 #size-cells = <0>;
 886                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 887                                 reg = <0x021a8000 0x4000>;
 888                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 889                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 890                                 status = "disabled";
 891                         };
 892
 893                         mmdc: mmdc@21b0000 {
 894                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 895                                 reg = <0x021b0000 0x4000>;
 896                         };
 897
 898                         rngb: rngb@21b4000 {
 899                                 reg = <0x021b4000 0x4000>;
 900                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 901                         };
 902
 903                         weim: weim@21b8000 {
 904                                 #address-cells = <2>;
 905                                 #size-cells = <1>;
 906                                 reg = <0x021b8000 0x4000>;
 907                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 908                                 fsl,weim-cs-gpr = <&gpr>;
 909                                 status = "disabled";
 910                         };
 911
 912                         ocotp: ocotp@21bc000 {
 913                                 compatible = "fsl,imx6sl-ocotp", "syscon";
 914                                 reg = <0x021bc000 0x4000>;
 915                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 916                         };
 917
 918                         audmux: audmux@21d8000 {
 919                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 920                                 reg = <0x021d8000 0x4000>;
 921                                 status = "disabled";
 922                         };
 923                 };
 924         };
 925 };