arch/arm/boot/dts/imx6sl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6sl-pinfunc.h"
   7 #include <dt-bindings/clock/imx6sl-clock.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         /*
  13          * The decompressor and also some bootloaders rely on a
  14          * pre-existing /chosen node to be available to insert the
  15          * command line and merge other ATAGS info.
  16          */
  17         chosen {};
  18
  19         aliases {
  20                 ethernet0 = &fec;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 serial4 = &uart5;
  31                 spi0 = &ecspi1;
  32                 spi1 = &ecspi2;
  33                 spi2 = &ecspi3;
  34                 spi3 = &ecspi4;
  35                 usbphy0 = &usbphy1;
  36                 usbphy1 = &usbphy2;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 cpu@0 {
  44                         compatible = "arm,cortex-a9";
  45                         device_type = "cpu";
  46                         reg = <0x0>;
  47                         next-level-cache = <&L2>;
  48                         operating-points = <
  49                                 /* kHz    uV */
  50                                 996000  1275000
  51                                 792000  1175000
  52                                 396000  975000
  53                         >;
  54                         fsl,soc-operating-points = <
  55                                 /* ARM kHz      SOC-PU uV */
  56                                 996000          1225000
  57                                 792000          1175000
  58                                 396000          1175000
  59                         >;
  60                         clock-latency = <61036>; /* two CLK32 periods */
  61                         #cooling-cells = <2>;
  62                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  63                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  64                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  65                         clock-names = "arm", "pll2_pfd2_396m", "step",
  66                                       "pll1_sw", "pll1_sys";
  67                         arm-supply = <&reg_arm>;
  68                         pu-supply = <&reg_pu>;
  69                         soc-supply = <&reg_soc>;
  70                 };
  71         };
  72
  73         intc: interrupt-controller@a01000 {
  74                 compatible = "arm,cortex-a9-gic";
  75                 #interrupt-cells = <3>;
  76                 interrupt-controller;
  77                 reg = <0x00a01000 0x1000>,
  78                       <0x00a00100 0x100>;
  79                 interrupt-parent = <&intc>;
  80         };
  81
  82         clocks {
  83                 ckil {
  84                         compatible = "fixed-clock";
  85                         #clock-cells = <0>;
  86                         clock-frequency = <32768>;
  87                 };
  88
  89                 osc {
  90                         compatible = "fixed-clock";
  91                         #clock-cells = <0>;
  92                         clock-frequency = <24000000>;
  93                 };
  94         };
  95
  96         tempmon: tempmon {
  97                 compatible = "fsl,imx6q-tempmon";
  98                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
  99                 interrupt-parent = <&gpc>;
 100                 fsl,tempmon = <&anatop>;
 101                 fsl,tempmon-data = <&ocotp>;
 102                 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 103         };
 104
 105         pmu {
 106                 compatible = "arm,cortex-a9-pmu";
 107                 interrupt-parent = <&gpc>;
 108                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 109         };
 110
 111         usbphynop1: usbphynop1 {
 112                 compatible = "usb-nop-xceiv";
 113                 #phy-cells = <0>;
 114         };
 115
 116         soc {
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 compatible = "simple-bus";
 120                 interrupt-parent = <&gpc>;
 121                 ranges;
 122
 123                 ocram: sram@900000 {
 124                         compatible = "mmio-sram";
 125                         reg = <0x00900000 0x20000>;
 126                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 127                 };
 128
 129                 L2: l2-cache@a02000 {
 130                         compatible = "arm,pl310-cache";
 131                         reg = <0x00a02000 0x1000>;
 132                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 133                         cache-unified;
 134                         cache-level = <2>;
 135                         arm,tag-latency = <4 2 3>;
 136                         arm,data-latency = <4 2 3>;
 137                 };
 138
 139                 aips1: aips-bus@2000000 {
 140                         compatible = "fsl,aips-bus", "simple-bus";
 141                         #address-cells = <1>;
 142                         #size-cells = <1>;
 143                         reg = <0x02000000 0x100000>;
 144                         ranges;
 145
 146                         spba: spba-bus@2000000 {
 147                                 compatible = "fsl,spba-bus", "simple-bus";
 148                                 #address-cells = <1>;
 149                                 #size-cells = <1>;
 150                                 reg = <0x02000000 0x40000>;
 151                                 ranges;
 152
 153                                 spdif: spdif@2004000 {
 154                                         compatible = "fsl,imx6sl-spdif",
 155                                                 "fsl,imx35-spdif";
 156                                         reg = <0x02004000 0x4000>;
 157                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 158                                         dmas = <&sdma 14 18 0>,
 159                                                 <&sdma 15 18 0>;
 160                                         dma-names = "rx", "tx";
 161                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 162                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 163                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 164                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 165                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 166                                         clock-names = "core", "rxtx0",
 167                                                 "rxtx1", "rxtx2",
 168                                                 "rxtx3", "rxtx4",
 169                                                 "rxtx5", "rxtx6",
 170                                                 "rxtx7", "spba";
 171                                         status = "disabled";
 172                                 };
 173
 174                                 ecspi1: spi@2008000 {
 175                                         #address-cells = <1>;
 176                                         #size-cells = <0>;
 177                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 178                                         reg = <0x02008000 0x4000>;
 179                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 180                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 181                                                  <&clks IMX6SL_CLK_ECSPI1>;
 182                                         clock-names = "ipg", "per";
 183                                         status = "disabled";
 184                                 };
 185
 186                                 ecspi2: spi@200c000 {
 187                                         #address-cells = <1>;
 188                                         #size-cells = <0>;
 189                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 190                                         reg = <0x0200c000 0x4000>;
 191                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 192                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 193                                                  <&clks IMX6SL_CLK_ECSPI2>;
 194                                         clock-names = "ipg", "per";
 195                                         status = "disabled";
 196                                 };
 197
 198                                 ecspi3: spi@2010000 {
 199                                         #address-cells = <1>;
 200                                         #size-cells = <0>;
 201                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 202                                         reg = <0x02010000 0x4000>;
 203                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 204                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 205                                                  <&clks IMX6SL_CLK_ECSPI3>;
 206                                         clock-names = "ipg", "per";
 207                                         status = "disabled";
 208                                 };
 209
 210                                 ecspi4: spi@2014000 {
 211                                         #address-cells = <1>;
 212                                         #size-cells = <0>;
 213                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 214                                         reg = <0x02014000 0x4000>;
 215                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 216                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 217                                                  <&clks IMX6SL_CLK_ECSPI4>;
 218                                         clock-names = "ipg", "per";
 219                                         status = "disabled";
 220                                 };
 221
 222                                 uart5: serial@2018000 {
 223                                         compatible = "fsl,imx6sl-uart",
 224                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 225                                         reg = <0x02018000 0x4000>;
 226                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 227                                         clocks = <&clks IMX6SL_CLK_UART>,
 228                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 229                                         clock-names = "ipg", "per";
 230                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 231                                         dma-names = "rx", "tx";
 232                                         status = "disabled";
 233                                 };
 234
 235                                 uart1: serial@2020000 {
 236                                         compatible = "fsl,imx6sl-uart",
 237                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 238                                         reg = <0x02020000 0x4000>;
 239                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 240                                         clocks = <&clks IMX6SL_CLK_UART>,
 241                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 242                                         clock-names = "ipg", "per";
 243                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 244                                         dma-names = "rx", "tx";
 245                                         status = "disabled";
 246                                 };
 247
 248                                 uart2: serial@2024000 {
 249                                         compatible = "fsl,imx6sl-uart",
 250                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 251                                         reg = <0x02024000 0x4000>;
 252                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 253                                         clocks = <&clks IMX6SL_CLK_UART>,
 254                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 255                                         clock-names = "ipg", "per";
 256                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 257                                         dma-names = "rx", "tx";
 258                                         status = "disabled";
 259                                 };
 260
 261                                 ssi1: ssi@2028000 {
 262                                         #sound-dai-cells = <0>;
 263                                         compatible = "fsl,imx6sl-ssi",
 264                                                         "fsl,imx51-ssi";
 265                                         reg = <0x02028000 0x4000>;
 266                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 267                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 268                                                  <&clks IMX6SL_CLK_SSI1>;
 269                                         clock-names = "ipg", "baud";
 270                                         dmas = <&sdma 37 1 0>,
 271                                                <&sdma 38 1 0>;
 272                                         dma-names = "rx", "tx";
 273                                         fsl,fifo-depth = <15>;
 274                                         status = "disabled";
 275                                 };
 276
 277                                 ssi2: ssi@202c000 {
 278                                         #sound-dai-cells = <0>;
 279                                         compatible = "fsl,imx6sl-ssi",
 280                                                         "fsl,imx51-ssi";
 281                                         reg = <0x0202c000 0x4000>;
 282                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 283                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 284                                                  <&clks IMX6SL_CLK_SSI2>;
 285                                         clock-names = "ipg", "baud";
 286                                         dmas = <&sdma 41 1 0>,
 287                                                <&sdma 42 1 0>;
 288                                         dma-names = "rx", "tx";
 289                                         fsl,fifo-depth = <15>;
 290                                         status = "disabled";
 291                                 };
 292
 293                                 ssi3: ssi@2030000 {
 294                                         #sound-dai-cells = <0>;
 295                                         compatible = "fsl,imx6sl-ssi",
 296                                                         "fsl,imx51-ssi";
 297                                         reg = <0x02030000 0x4000>;
 298                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 299                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 300                                                  <&clks IMX6SL_CLK_SSI3>;
 301                                         clock-names = "ipg", "baud";
 302                                         dmas = <&sdma 45 1 0>,
 303                                                <&sdma 46 1 0>;
 304                                         dma-names = "rx", "tx";
 305                                         fsl,fifo-depth = <15>;
 306                                         status = "disabled";
 307                                 };
 308
 309                                 uart3: serial@2034000 {
 310                                         compatible = "fsl,imx6sl-uart",
 311                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 312                                         reg = <0x02034000 0x4000>;
 313                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 314                                         clocks = <&clks IMX6SL_CLK_UART>,
 315                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 316                                         clock-names = "ipg", "per";
 317                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 318                                         dma-names = "rx", "tx";
 319                                         status = "disabled";
 320                                 };
 321
 322                                 uart4: serial@2038000 {
 323                                         compatible = "fsl,imx6sl-uart",
 324                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 325                                         reg = <0x02038000 0x4000>;
 326                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 327                                         clocks = <&clks IMX6SL_CLK_UART>,
 328                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 329                                         clock-names = "ipg", "per";
 330                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 331                                         dma-names = "rx", "tx";
 332                                         status = "disabled";
 333                                 };
 334                         };
 335
 336                         pwm1: pwm@2080000 {
 337                                 #pwm-cells = <2>;
 338                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 339                                 reg = <0x02080000 0x4000>;
 340                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 341                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 342                                          <&clks IMX6SL_CLK_PWM1>;
 343                                 clock-names = "ipg", "per";
 344                         };
 345
 346                         pwm2: pwm@2084000 {
 347                                 #pwm-cells = <2>;
 348                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 349                                 reg = <0x02084000 0x4000>;
 350                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 351                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 352                                          <&clks IMX6SL_CLK_PWM2>;
 353                                 clock-names = "ipg", "per";
 354                         };
 355
 356                         pwm3: pwm@2088000 {
 357                                 #pwm-cells = <2>;
 358                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 359                                 reg = <0x02088000 0x4000>;
 360                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 361                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 362                                          <&clks IMX6SL_CLK_PWM3>;
 363                                 clock-names = "ipg", "per";
 364                         };
 365
 366                         pwm4: pwm@208c000 {
 367                                 #pwm-cells = <2>;
 368                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 369                                 reg = <0x0208c000 0x4000>;
 370                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 371                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 372                                          <&clks IMX6SL_CLK_PWM4>;
 373                                 clock-names = "ipg", "per";
 374                         };
 375
 376                         gpt: gpt@2098000 {
 377                                 compatible = "fsl,imx6sl-gpt";
 378                                 reg = <0x02098000 0x4000>;
 379                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 380                                 clocks = <&clks IMX6SL_CLK_GPT>,
 381                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 382                                 clock-names = "ipg", "per";
 383                         };
 384
 385                         gpio1: gpio@209c000 {
 386                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 387                                 reg = <0x0209c000 0x4000>;
 388                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 389                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 390                                 gpio-controller;
 391                                 #gpio-cells = <2>;
 392                                 interrupt-controller;
 393                                 #interrupt-cells = <2>;
 394                                 gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
 395                                               <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
 396                                               <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
 397                                               <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
 398                                               <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
 399                                               <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
 400                         };
 401
 402                         gpio2: gpio@20a0000 {
 403                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 404                                 reg = <0x020a0000 0x4000>;
 405                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 406                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 407                                 gpio-controller;
 408                                 #gpio-cells = <2>;
 409                                 interrupt-controller;
 410                                 #interrupt-cells = <2>;
 411                                 gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
 412                                               <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
 413                                               <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
 414                                               <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
 415                                               <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
 416                                               <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
 417                                               <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
 418                         };
 419
 420                         gpio3: gpio@20a4000 {
 421                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 422                                 reg = <0x020a4000 0x4000>;
 423                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 424                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 425                                 gpio-controller;
 426                                 #gpio-cells = <2>;
 427                                 interrupt-controller;
 428                                 #interrupt-cells = <2>;
 429                                 gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
 430                                               <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
 431                                               <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
 432                                               <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
 433                                               <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
 434                                               <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
 435                                               <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
 436                                               <&iomuxc 31 102 1>;
 437                         };
 438
 439                         gpio4: gpio@20a8000 {
 440                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 441                                 reg = <0x020a8000 0x4000>;
 442                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 443                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 444                                 gpio-controller;
 445                                 #gpio-cells = <2>;
 446                                 interrupt-controller;
 447                                 #interrupt-cells = <2>;
 448                                 gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
 449                                               <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
 450                                               <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
 451                                               <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
 452                                               <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
 453                                               <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
 454                                               <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
 455                                               <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
 456                                               <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
 457                                               <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
 458                                               <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
 459                                               <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
 460                                               <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
 461                                               <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
 462                                               <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
 463                         };
 464
 465                         gpio5: gpio@20ac000 {
 466                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 467                                 reg = <0x020ac000 0x4000>;
 468                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 469                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 470                                 gpio-controller;
 471                                 #gpio-cells = <2>;
 472                                 interrupt-controller;
 473                                 #interrupt-cells = <2>;
 474                                 gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
 475                                               <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
 476                                               <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
 477                                               <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
 478                                               <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
 479                                               <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
 480                                               <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
 481                                               <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
 482                                               <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
 483                                               <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
 484                                               <&iomuxc 21 161 1>;
 485                         };
 486
 487                         kpp: kpp@20b8000 {
 488                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 489                                 reg = <0x020b8000 0x4000>;
 490                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 491                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 492                                 status = "disabled";
 493                         };
 494
 495                         wdog1: wdog@20bc000 {
 496                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 497                                 reg = <0x020bc000 0x4000>;
 498                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 499                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 500                         };
 501
 502                         wdog2: wdog@20c0000 {
 503                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 504                                 reg = <0x020c0000 0x4000>;
 505                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 506                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 507                                 status = "disabled";
 508                         };
 509
 510                         clks: ccm@20c4000 {
 511                                 compatible = "fsl,imx6sl-ccm";
 512                                 reg = <0x020c4000 0x4000>;
 513                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 514                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 515                                 #clock-cells = <1>;
 516                         };
 517
 518                         anatop: anatop@20c8000 {
 519                                 compatible = "fsl,imx6sl-anatop",
 520                                              "fsl,imx6q-anatop",
 521                                              "syscon", "simple-bus";
 522                                 reg = <0x020c8000 0x1000>;
 523                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 524                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 525                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 526
 527                                 regulator-1p1 {
 528                                         compatible = "fsl,anatop-regulator";
 529                                         regulator-name = "vdd1p1";
 530                                         regulator-min-microvolt = <1000000>;
 531                                         regulator-max-microvolt = <1200000>;
 532                                         regulator-always-on;
 533                                         anatop-reg-offset = <0x110>;
 534                                         anatop-vol-bit-shift = <8>;
 535                                         anatop-vol-bit-width = <5>;
 536                                         anatop-min-bit-val = <4>;
 537                                         anatop-min-voltage = <800000>;
 538                                         anatop-max-voltage = <1375000>;
 539                                         anatop-enable-bit = <0>;
 540                                 };
 541
 542                                 regulator-3p0 {
 543                                         compatible = "fsl,anatop-regulator";
 544                                         regulator-name = "vdd3p0";
 545                                         regulator-min-microvolt = <2800000>;
 546                                         regulator-max-microvolt = <3150000>;
 547                                         regulator-always-on;
 548                                         anatop-reg-offset = <0x120>;
 549                                         anatop-vol-bit-shift = <8>;
 550                                         anatop-vol-bit-width = <5>;
 551                                         anatop-min-bit-val = <0>;
 552                                         anatop-min-voltage = <2625000>;
 553                                         anatop-max-voltage = <3400000>;
 554                                         anatop-enable-bit = <0>;
 555                                 };
 556
 557                                 regulator-2p5 {
 558                                         compatible = "fsl,anatop-regulator";
 559                                         regulator-name = "vdd2p5";
 560                                         regulator-min-microvolt = <2250000>;
 561                                         regulator-max-microvolt = <2750000>;
 562                                         regulator-always-on;
 563                                         anatop-reg-offset = <0x130>;
 564                                         anatop-vol-bit-shift = <8>;
 565                                         anatop-vol-bit-width = <5>;
 566                                         anatop-min-bit-val = <0>;
 567                                         anatop-min-voltage = <2100000>;
 568                                         anatop-max-voltage = <2850000>;
 569                                         anatop-enable-bit = <0>;
 570                                 };
 571
 572                                 reg_arm: regulator-vddcore {
 573                                         compatible = "fsl,anatop-regulator";
 574                                         regulator-name = "vddarm";
 575                                         regulator-min-microvolt = <725000>;
 576                                         regulator-max-microvolt = <1450000>;
 577                                         regulator-always-on;
 578                                         anatop-reg-offset = <0x140>;
 579                                         anatop-vol-bit-shift = <0>;
 580                                         anatop-vol-bit-width = <5>;
 581                                         anatop-delay-reg-offset = <0x170>;
 582                                         anatop-delay-bit-shift = <24>;
 583                                         anatop-delay-bit-width = <2>;
 584                                         anatop-min-bit-val = <1>;
 585                                         anatop-min-voltage = <725000>;
 586                                         anatop-max-voltage = <1450000>;
 587                                 };
 588
 589                                 reg_pu: regulator-vddpu {
 590                                         compatible = "fsl,anatop-regulator";
 591                                         regulator-name = "vddpu";
 592                                         regulator-min-microvolt = <725000>;
 593                                         regulator-max-microvolt = <1450000>;
 594                                         anatop-reg-offset = <0x140>;
 595                                         anatop-vol-bit-shift = <9>;
 596                                         anatop-vol-bit-width = <5>;
 597                                         anatop-delay-reg-offset = <0x170>;
 598                                         anatop-delay-bit-shift = <26>;
 599                                         anatop-delay-bit-width = <2>;
 600                                         anatop-min-bit-val = <1>;
 601                                         anatop-min-voltage = <725000>;
 602                                         anatop-max-voltage = <1450000>;
 603                                 };
 604
 605                                 reg_soc: regulator-vddsoc {
 606                                         compatible = "fsl,anatop-regulator";
 607                                         regulator-name = "vddsoc";
 608                                         regulator-min-microvolt = <725000>;
 609                                         regulator-max-microvolt = <1450000>;
 610                                         regulator-always-on;
 611                                         anatop-reg-offset = <0x140>;
 612                                         anatop-vol-bit-shift = <18>;
 613                                         anatop-vol-bit-width = <5>;
 614                                         anatop-delay-reg-offset = <0x170>;
 615                                         anatop-delay-bit-shift = <28>;
 616                                         anatop-delay-bit-width = <2>;
 617                                         anatop-min-bit-val = <1>;
 618                                         anatop-min-voltage = <725000>;
 619                                         anatop-max-voltage = <1450000>;
 620                                 };
 621                         };
 622
 623                         usbphy1: usbphy@20c9000 {
 624                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 625                                 reg = <0x020c9000 0x1000>;
 626                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 627                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 628                                 fsl,anatop = <&anatop>;
 629                         };
 630
 631                         usbphy2: usbphy@20ca000 {
 632                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 633                                 reg = <0x020ca000 0x1000>;
 634                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 635                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 636                                 fsl,anatop = <&anatop>;
 637                         };
 638
 639                         snvs: snvs@20cc000 {
 640                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 641                                 reg = <0x020cc000 0x4000>;
 642
 643                                 snvs_rtc: snvs-rtc-lp {
 644                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 645                                         regmap = <&snvs>;
 646                                         offset = <0x34>;
 647                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 648                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 649                                 };
 650
 651                                 snvs_poweroff: snvs-poweroff {
 652                                         compatible = "syscon-poweroff";
 653                                         regmap = <&snvs>;
 654                                         offset = <0x38>;
 655                                         value = <0x60>;
 656                                         mask = <0x60>;
 657                                         status = "disabled";
 658                                 };
 659                         };
 660
 661                         epit1: epit@20d0000 {
 662                                 reg = <0x020d0000 0x4000>;
 663                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 664                         };
 665
 666                         epit2: epit@20d4000 {
 667                                 reg = <0x020d4000 0x4000>;
 668                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 669                         };
 670
 671                         src: src@20d8000 {
 672                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 673                                 reg = <0x020d8000 0x4000>;
 674                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 675                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 676                                 #reset-cells = <1>;
 677                         };
 678
 679                         gpc: gpc@20dc000 {
 680                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 681                                 reg = <0x020dc000 0x4000>;
 682                                 interrupt-controller;
 683                                 #interrupt-cells = <3>;
 684                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 685                                 interrupt-parent = <&intc>;
 686                                 clocks = <&clks IMX6SL_CLK_IPG>;
 687                                 clock-names = "ipg";
 688
 689                                 pgc {
 690                                         #address-cells = <1>;
 691                                         #size-cells = <0>;
 692
 693                                         power-domain@0 {
 694                                                 reg = <0>;
 695                                                 #power-domain-cells = <0>;
 696                                         };
 697
 698                                         pd_pu: power-domain@1 {
 699                                                 reg = <1>;
 700                                                 #power-domain-cells = <0>;
 701                                                 power-supply = <&reg_pu>;
 702                                                 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
 703                                                          <&clks IMX6SL_CLK_GPU2D_PODF>;
 704                                         };
 705
 706                                         pd_disp: power-domain@2 {
 707                                                 reg = <2>;
 708                                                 #power-domain-cells = <0>;
 709                                                 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
 710                                                          <&clks IMX6SL_CLK_LCDIF_PIX>,
 711                                                          <&clks IMX6SL_CLK_EPDC_AXI>,
 712                                                          <&clks IMX6SL_CLK_EPDC_PIX>,
 713                                                          <&clks IMX6SL_CLK_PXP_AXI>;
 714                                         };
 715                                 };
 716                         };
 717
 718                         gpr: iomuxc-gpr@20e0000 {
 719                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 720                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 721                                 reg = <0x020e0000 0x38>;
 722                         };
 723
 724                         iomuxc: iomuxc@20e0000 {
 725                                 compatible = "fsl,imx6sl-iomuxc";
 726                                 reg = <0x020e0000 0x4000>;
 727                         };
 728
 729                         csi: csi@20e4000 {
 730                                 reg = <0x020e4000 0x4000>;
 731                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 732                         };
 733
 734                         spdc: spdc@20e8000 {
 735                                 reg = <0x020e8000 0x4000>;
 736                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 737                         };
 738
 739                         sdma: sdma@20ec000 {
 740                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 741                                 reg = <0x020ec000 0x4000>;
 742                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 743                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 744                                          <&clks IMX6SL_CLK_SDMA>;
 745                                 clock-names = "ipg", "ahb";
 746                                 #dma-cells = <3>;
 747                                 /* imx6sl reuses imx6q sdma firmware */
 748                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 749                         };
 750
 751                         pxp: pxp@20f0000 {
 752                                 reg = <0x020f0000 0x4000>;
 753                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 754                         };
 755
 756                         epdc: epdc@20f4000 {
 757                                 reg = <0x020f4000 0x4000>;
 758                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 759                         };
 760
 761                         lcdif: lcdif@20f8000 {
 762                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 763                                 reg = <0x020f8000 0x4000>;
 764                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 765                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 766                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 767                                          <&clks IMX6SL_CLK_DUMMY>;
 768                                 clock-names = "pix", "axi", "disp_axi";
 769                                 status = "disabled";
 770                                 power-domains = <&pd_disp>;
 771                         };
 772
 773                         dcp: dcp@20fc000 {
 774                                 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
 775                                 reg = <0x020fc000 0x4000>;
 776                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 777                                              <0 100 IRQ_TYPE_LEVEL_HIGH>,
 778                                              <0 101 IRQ_TYPE_LEVEL_HIGH>;
 779                         };
 780                 };
 781
 782                 aips2: aips-bus@2100000 {
 783                         compatible = "fsl,aips-bus", "simple-bus";
 784                         #address-cells = <1>;
 785                         #size-cells = <1>;
 786                         reg = <0x02100000 0x100000>;
 787                         ranges;
 788
 789                         usbotg1: usb@2184000 {
 790                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 791                                 reg = <0x02184000 0x200>;
 792                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 793                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 794                                 fsl,usbphy = <&usbphy1>;
 795                                 fsl,usbmisc = <&usbmisc 0>;
 796                                 ahb-burst-config = <0x0>;
 797                                 tx-burst-size-dword = <0x10>;
 798                                 rx-burst-size-dword = <0x10>;
 799                                 status = "disabled";
 800                         };
 801
 802                         usbotg2: usb@2184200 {
 803                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 804                                 reg = <0x02184200 0x200>;
 805                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 806                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 807                                 fsl,usbphy = <&usbphy2>;
 808                                 fsl,usbmisc = <&usbmisc 1>;
 809                                 ahb-burst-config = <0x0>;
 810                                 tx-burst-size-dword = <0x10>;
 811                                 rx-burst-size-dword = <0x10>;
 812                                 status = "disabled";
 813                         };
 814
 815                         usbh: usb@2184400 {
 816                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 817                                 reg = <0x02184400 0x200>;
 818                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 819                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 820                                 fsl,usbphy = <&usbphynop1>;
 821                                 phy_type = "hsic";
 822                                 fsl,usbmisc = <&usbmisc 2>;
 823                                 dr_mode = "host";
 824                                 ahb-burst-config = <0x0>;
 825                                 tx-burst-size-dword = <0x10>;
 826                                 rx-burst-size-dword = <0x10>;
 827                                 status = "disabled";
 828                         };
 829
 830                         usbmisc: usbmisc@2184800 {
 831                                 #index-cells = <1>;
 832                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 833                                 reg = <0x02184800 0x200>;
 834                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 835                         };
 836
 837                         fec: ethernet@2188000 {
 838                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 839                                 reg = <0x02188000 0x4000>;
 840                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 841                                 clocks = <&clks IMX6SL_CLK_ENET>,
 842                                          <&clks IMX6SL_CLK_ENET_REF>;
 843                                 clock-names = "ipg", "ahb";
 844                                 status = "disabled";
 845                         };
 846
 847                         usdhc1: usdhc@2190000 {
 848                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 849                                 reg = <0x02190000 0x4000>;
 850                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 851                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 852                                          <&clks IMX6SL_CLK_USDHC1>,
 853                                          <&clks IMX6SL_CLK_USDHC1>;
 854                                 clock-names = "ipg", "ahb", "per";
 855                                 bus-width = <4>;
 856                                 status = "disabled";
 857                         };
 858
 859                         usdhc2: usdhc@2194000 {
 860                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 861                                 reg = <0x02194000 0x4000>;
 862                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 863                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 864                                          <&clks IMX6SL_CLK_USDHC2>,
 865                                          <&clks IMX6SL_CLK_USDHC2>;
 866                                 clock-names = "ipg", "ahb", "per";
 867                                 bus-width = <4>;
 868                                 status = "disabled";
 869                         };
 870
 871                         usdhc3: usdhc@2198000 {
 872                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 873                                 reg = <0x02198000 0x4000>;
 874                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 875                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 876                                          <&clks IMX6SL_CLK_USDHC3>,
 877                                          <&clks IMX6SL_CLK_USDHC3>;
 878                                 clock-names = "ipg", "ahb", "per";
 879                                 bus-width = <4>;
 880                                 status = "disabled";
 881                         };
 882
 883                         usdhc4: usdhc@219c000 {
 884                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 885                                 reg = <0x0219c000 0x4000>;
 886                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 887                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 888                                          <&clks IMX6SL_CLK_USDHC4>,
 889                                          <&clks IMX6SL_CLK_USDHC4>;
 890                                 clock-names = "ipg", "ahb", "per";
 891                                 bus-width = <4>;
 892                                 status = "disabled";
 893                         };
 894
 895                         i2c1: i2c@21a0000 {
 896                                 #address-cells = <1>;
 897                                 #size-cells = <0>;
 898                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 899                                 reg = <0x021a0000 0x4000>;
 900                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 901                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 902                                 status = "disabled";
 903                         };
 904
 905                         i2c2: i2c@21a4000 {
 906                                 #address-cells = <1>;
 907                                 #size-cells = <0>;
 908                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 909                                 reg = <0x021a4000 0x4000>;
 910                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 911                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 912                                 status = "disabled";
 913                         };
 914
 915                         i2c3: i2c@21a8000 {
 916                                 #address-cells = <1>;
 917                                 #size-cells = <0>;
 918                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 919                                 reg = <0x021a8000 0x4000>;
 920                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 921                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 922                                 status = "disabled";
 923                         };
 924
 925                         mmdc: mmdc@21b0000 {
 926                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 927                                 reg = <0x021b0000 0x4000>;
 928                                 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
 929                         };
 930
 931                         rngb: rngb@21b4000 {
 932                                 reg = <0x021b4000 0x4000>;
 933                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 934                         };
 935
 936                         weim: weim@21b8000 {
 937                                 #address-cells = <2>;
 938                                 #size-cells = <1>;
 939                                 reg = <0x021b8000 0x4000>;
 940                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 941                                 fsl,weim-cs-gpr = <&gpr>;
 942                                 status = "disabled";
 943                         };
 944
 945                         ocotp: ocotp@21bc000 {
 946                                 compatible = "fsl,imx6sl-ocotp", "syscon";
 947                                 reg = <0x021bc000 0x4000>;
 948                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 949                         };
 950
 951                         audmux: audmux@21d8000 {
 952                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 953                                 reg = <0x021d8000 0x4000>;
 954                                 status = "disabled";
 955                         };
 956                 };
 957
 958                 gpu_2d: gpu@2200000 {
 959                         compatible = "vivante,gc";
 960                         reg = <0x02200000 0x4000>;
 961                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 962                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 963                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
 964                         clock-names = "bus", "core";
 965                         power-domains = <&pd_pu>;
 966                 };
 967
 968                 gpu_vg: gpu@2204000 {
 969                         compatible = "vivante,gc";
 970                         reg = <0x02204000 0x4000>;
 971                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 972                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 973                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
 974                         clock-names = "bus", "core";
 975                         power-domains = <&pd_pu>;
 976                 };
 977         };
 978 };