arch/arm/boot/dts/imx6sl.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include "imx6sl-pinfunc.h"
  12 #include <dt-bindings/clock/imx6sl-clock.h>
  13
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17         /*
  18          * The decompressor and also some bootloaders rely on a
  19          * pre-existing /chosen node to be available to insert the
  20          * command line and merge other ATAGS info.
  21          * Also for U-Boot there must be a pre-existing /memory node.
  22          */
  23         chosen {};
  24         memory { device_type = "memory"; reg = <0 0>; };
  25
  26         aliases {
  27                 ethernet0 = &fec;
  28                 gpio0 = &gpio1;
  29                 gpio1 = &gpio2;
  30                 gpio2 = &gpio3;
  31                 gpio3 = &gpio4;
  32                 gpio4 = &gpio5;
  33                 serial0 = &uart1;
  34                 serial1 = &uart2;
  35                 serial2 = &uart3;
  36                 serial3 = &uart4;
  37                 serial4 = &uart5;
  38                 spi0 = &ecspi1;
  39                 spi1 = &ecspi2;
  40                 spi2 = &ecspi3;
  41                 spi3 = &ecspi4;
  42                 usbphy0 = &usbphy1;
  43                 usbphy1 = &usbphy2;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu@0 {
  51                         compatible = "arm,cortex-a9";
  52                         device_type = "cpu";
  53                         reg = <0x0>;
  54                         next-level-cache = <&L2>;
  55                         operating-points = <
  56                                 /* kHz    uV */
  57                                 996000  1275000
  58                                 792000  1175000
  59                                 396000  975000
  60                         >;
  61                         fsl,soc-operating-points = <
  62                                 /* ARM kHz      SOC-PU uV */
  63                                 996000          1225000
  64                                 792000          1175000
  65                                 396000          1175000
  66                         >;
  67                         clock-latency = <61036>; /* two CLK32 periods */
  68                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  69                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  70                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  71                         clock-names = "arm", "pll2_pfd2_396m", "step",
  72                                       "pll1_sw", "pll1_sys";
  73                         arm-supply = <&reg_arm>;
  74                         pu-supply = <&reg_pu>;
  75                         soc-supply = <&reg_soc>;
  76                 };
  77         };
  78
  79         intc: interrupt-controller@a01000 {
  80                 compatible = "arm,cortex-a9-gic";
  81                 #interrupt-cells = <3>;
  82                 interrupt-controller;
  83                 reg = <0x00a01000 0x1000>,
  84                       <0x00a00100 0x100>;
  85                 interrupt-parent = <&intc>;
  86         };
  87
  88         clocks {
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91
  92                 ckil {
  93                         compatible = "fixed-clock";
  94                         #clock-cells = <0>;
  95                         clock-frequency = <32768>;
  96                 };
  97
  98                 osc {
  99                         compatible = "fixed-clock";
 100                         #clock-cells = <0>;
 101                         clock-frequency = <24000000>;
 102                 };
 103         };
 104
 105         soc {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 compatible = "simple-bus";
 109                 interrupt-parent = <&gpc>;
 110                 ranges;
 111
 112                 ocram: sram@900000 {
 113                         compatible = "mmio-sram";
 114                         reg = <0x00900000 0x20000>;
 115                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 116                 };
 117
 118                 L2: l2-cache@a02000 {
 119                         compatible = "arm,pl310-cache";
 120                         reg = <0x00a02000 0x1000>;
 121                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 122                         cache-unified;
 123                         cache-level = <2>;
 124                         arm,tag-latency = <4 2 3>;
 125                         arm,data-latency = <4 2 3>;
 126                 };
 127
 128                 pmu {
 129                         compatible = "arm,cortex-a9-pmu";
 130                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 131                 };
 132
 133                 aips1: aips-bus@2000000 {
 134                         compatible = "fsl,aips-bus", "simple-bus";
 135                         #address-cells = <1>;
 136                         #size-cells = <1>;
 137                         reg = <0x02000000 0x100000>;
 138                         ranges;
 139
 140                         spba: spba-bus@2000000 {
 141                                 compatible = "fsl,spba-bus", "simple-bus";
 142                                 #address-cells = <1>;
 143                                 #size-cells = <1>;
 144                                 reg = <0x02000000 0x40000>;
 145                                 ranges;
 146
 147                                 spdif: spdif@2004000 {
 148                                         compatible = "fsl,imx6sl-spdif",
 149                                                 "fsl,imx35-spdif";
 150                                         reg = <0x02004000 0x4000>;
 151                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 152                                         dmas = <&sdma 14 18 0>,
 153                                                 <&sdma 15 18 0>;
 154                                         dma-names = "rx", "tx";
 155                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 156                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 157                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 158                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 159                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 160                                         clock-names = "core", "rxtx0",
 161                                                 "rxtx1", "rxtx2",
 162                                                 "rxtx3", "rxtx4",
 163                                                 "rxtx5", "rxtx6",
 164                                                 "rxtx7", "spba";
 165                                         status = "disabled";
 166                                 };
 167
 168                                 ecspi1: ecspi@2008000 {
 169                                         #address-cells = <1>;
 170                                         #size-cells = <0>;
 171                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 172                                         reg = <0x02008000 0x4000>;
 173                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 174                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 175                                                  <&clks IMX6SL_CLK_ECSPI1>;
 176                                         clock-names = "ipg", "per";
 177                                         status = "disabled";
 178                                 };
 179
 180                                 ecspi2: ecspi@200c000 {
 181                                         #address-cells = <1>;
 182                                         #size-cells = <0>;
 183                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 184                                         reg = <0x0200c000 0x4000>;
 185                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 186                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 187                                                  <&clks IMX6SL_CLK_ECSPI2>;
 188                                         clock-names = "ipg", "per";
 189                                         status = "disabled";
 190                                 };
 191
 192                                 ecspi3: ecspi@2010000 {
 193                                         #address-cells = <1>;
 194                                         #size-cells = <0>;
 195                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 196                                         reg = <0x02010000 0x4000>;
 197                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 198                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 199                                                  <&clks IMX6SL_CLK_ECSPI3>;
 200                                         clock-names = "ipg", "per";
 201                                         status = "disabled";
 202                                 };
 203
 204                                 ecspi4: ecspi@2014000 {
 205                                         #address-cells = <1>;
 206                                         #size-cells = <0>;
 207                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 208                                         reg = <0x02014000 0x4000>;
 209                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 210                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 211                                                  <&clks IMX6SL_CLK_ECSPI4>;
 212                                         clock-names = "ipg", "per";
 213                                         status = "disabled";
 214                                 };
 215
 216                                 uart5: serial@2018000 {
 217                                         compatible = "fsl,imx6sl-uart",
 218                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 219                                         reg = <0x02018000 0x4000>;
 220                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 221                                         clocks = <&clks IMX6SL_CLK_UART>,
 222                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 223                                         clock-names = "ipg", "per";
 224                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 225                                         dma-names = "rx", "tx";
 226                                         status = "disabled";
 227                                 };
 228
 229                                 uart1: serial@2020000 {
 230                                         compatible = "fsl,imx6sl-uart",
 231                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 232                                         reg = <0x02020000 0x4000>;
 233                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 234                                         clocks = <&clks IMX6SL_CLK_UART>,
 235                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 236                                         clock-names = "ipg", "per";
 237                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 238                                         dma-names = "rx", "tx";
 239                                         status = "disabled";
 240                                 };
 241
 242                                 uart2: serial@2024000 {
 243                                         compatible = "fsl,imx6sl-uart",
 244                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 245                                         reg = <0x02024000 0x4000>;
 246                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 247                                         clocks = <&clks IMX6SL_CLK_UART>,
 248                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 249                                         clock-names = "ipg", "per";
 250                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 251                                         dma-names = "rx", "tx";
 252                                         status = "disabled";
 253                                 };
 254
 255                                 ssi1: ssi@2028000 {
 256                                         #sound-dai-cells = <0>;
 257                                         compatible = "fsl,imx6sl-ssi",
 258                                                         "fsl,imx51-ssi";
 259                                         reg = <0x02028000 0x4000>;
 260                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 261                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 262                                                  <&clks IMX6SL_CLK_SSI1>;
 263                                         clock-names = "ipg", "baud";
 264                                         dmas = <&sdma 37 1 0>,
 265                                                <&sdma 38 1 0>;
 266                                         dma-names = "rx", "tx";
 267                                         fsl,fifo-depth = <15>;
 268                                         status = "disabled";
 269                                 };
 270
 271                                 ssi2: ssi@202c000 {
 272                                         #sound-dai-cells = <0>;
 273                                         compatible = "fsl,imx6sl-ssi",
 274                                                         "fsl,imx51-ssi";
 275                                         reg = <0x0202c000 0x4000>;
 276                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 277                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 278                                                  <&clks IMX6SL_CLK_SSI2>;
 279                                         clock-names = "ipg", "baud";
 280                                         dmas = <&sdma 41 1 0>,
 281                                                <&sdma 42 1 0>;
 282                                         dma-names = "rx", "tx";
 283                                         fsl,fifo-depth = <15>;
 284                                         status = "disabled";
 285                                 };
 286
 287                                 ssi3: ssi@2030000 {
 288                                         #sound-dai-cells = <0>;
 289                                         compatible = "fsl,imx6sl-ssi",
 290                                                         "fsl,imx51-ssi";
 291                                         reg = <0x02030000 0x4000>;
 292                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 293                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 294                                                  <&clks IMX6SL_CLK_SSI3>;
 295                                         clock-names = "ipg", "baud";
 296                                         dmas = <&sdma 45 1 0>,
 297                                                <&sdma 46 1 0>;
 298                                         dma-names = "rx", "tx";
 299                                         fsl,fifo-depth = <15>;
 300                                         status = "disabled";
 301                                 };
 302
 303                                 uart3: serial@2034000 {
 304                                         compatible = "fsl,imx6sl-uart",
 305                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 306                                         reg = <0x02034000 0x4000>;
 307                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 308                                         clocks = <&clks IMX6SL_CLK_UART>,
 309                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 310                                         clock-names = "ipg", "per";
 311                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 312                                         dma-names = "rx", "tx";
 313                                         status = "disabled";
 314                                 };
 315
 316                                 uart4: serial@2038000 {
 317                                         compatible = "fsl,imx6sl-uart",
 318                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 319                                         reg = <0x02038000 0x4000>;
 320                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 321                                         clocks = <&clks IMX6SL_CLK_UART>,
 322                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 323                                         clock-names = "ipg", "per";
 324                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 325                                         dma-names = "rx", "tx";
 326                                         status = "disabled";
 327                                 };
 328                         };
 329
 330                         pwm1: pwm@2080000 {
 331                                 #pwm-cells = <2>;
 332                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 333                                 reg = <0x02080000 0x4000>;
 334                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 335                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 336                                          <&clks IMX6SL_CLK_PWM1>;
 337                                 clock-names = "ipg", "per";
 338                         };
 339
 340                         pwm2: pwm@2084000 {
 341                                 #pwm-cells = <2>;
 342                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 343                                 reg = <0x02084000 0x4000>;
 344                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 345                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 346                                          <&clks IMX6SL_CLK_PWM2>;
 347                                 clock-names = "ipg", "per";
 348                         };
 349
 350                         pwm3: pwm@2088000 {
 351                                 #pwm-cells = <2>;
 352                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 353                                 reg = <0x02088000 0x4000>;
 354                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 355                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 356                                          <&clks IMX6SL_CLK_PWM3>;
 357                                 clock-names = "ipg", "per";
 358                         };
 359
 360                         pwm4: pwm@208c000 {
 361                                 #pwm-cells = <2>;
 362                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 363                                 reg = <0x0208c000 0x4000>;
 364                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 365                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 366                                          <&clks IMX6SL_CLK_PWM4>;
 367                                 clock-names = "ipg", "per";
 368                         };
 369
 370                         gpt: gpt@2098000 {
 371                                 compatible = "fsl,imx6sl-gpt";
 372                                 reg = <0x02098000 0x4000>;
 373                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 374                                 clocks = <&clks IMX6SL_CLK_GPT>,
 375                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 376                                 clock-names = "ipg", "per";
 377                         };
 378
 379                         gpio1: gpio@209c000 {
 380                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 381                                 reg = <0x0209c000 0x4000>;
 382                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 383                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 384                                 gpio-controller;
 385                                 #gpio-cells = <2>;
 386                                 interrupt-controller;
 387                                 #interrupt-cells = <2>;
 388                                 gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
 389                                               <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
 390                                               <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
 391                                               <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
 392                                               <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
 393                                               <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
 394                         };
 395
 396                         gpio2: gpio@20a0000 {
 397                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 398                                 reg = <0x020a0000 0x4000>;
 399                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 400                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 401                                 gpio-controller;
 402                                 #gpio-cells = <2>;
 403                                 interrupt-controller;
 404                                 #interrupt-cells = <2>;
 405                                 gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
 406                                               <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
 407                                               <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
 408                                               <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
 409                                               <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
 410                                               <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
 411                                               <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
 412                         };
 413
 414                         gpio3: gpio@20a4000 {
 415                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 416                                 reg = <0x020a4000 0x4000>;
 417                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 418                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 419                                 gpio-controller;
 420                                 #gpio-cells = <2>;
 421                                 interrupt-controller;
 422                                 #interrupt-cells = <2>;
 423                                 gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
 424                                               <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
 425                                               <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
 426                                               <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
 427                                               <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
 428                                               <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
 429                                               <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
 430                                               <&iomuxc 31 102 1>;
 431                         };
 432
 433                         gpio4: gpio@20a8000 {
 434                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 435                                 reg = <0x020a8000 0x4000>;
 436                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 437                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 438                                 gpio-controller;
 439                                 #gpio-cells = <2>;
 440                                 interrupt-controller;
 441                                 #interrupt-cells = <2>;
 442                                 gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
 443                                               <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
 444                                               <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
 445                                               <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
 446                                               <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
 447                                               <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
 448                                               <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
 449                                               <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
 450                                               <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
 451                                               <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
 452                                               <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
 453                                               <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
 454                                               <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
 455                                               <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
 456                                               <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
 457                         };
 458
 459                         gpio5: gpio@20ac000 {
 460                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 461                                 reg = <0x020ac000 0x4000>;
 462                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 463                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 464                                 gpio-controller;
 465                                 #gpio-cells = <2>;
 466                                 interrupt-controller;
 467                                 #interrupt-cells = <2>;
 468                                 gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
 469                                               <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
 470                                               <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
 471                                               <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
 472                                               <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
 473                                               <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
 474                                               <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
 475                                               <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
 476                                               <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
 477                                               <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
 478                                               <&iomuxc 21 161 1>;
 479                         };
 480
 481                         kpp: kpp@20b8000 {
 482                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 483                                 reg = <0x020b8000 0x4000>;
 484                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 485                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 486                                 status = "disabled";
 487                         };
 488
 489                         wdog1: wdog@20bc000 {
 490                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 491                                 reg = <0x020bc000 0x4000>;
 492                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 493                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 494                         };
 495
 496                         wdog2: wdog@20c0000 {
 497                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 498                                 reg = <0x020c0000 0x4000>;
 499                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 500                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 501                                 status = "disabled";
 502                         };
 503
 504                         clks: ccm@20c4000 {
 505                                 compatible = "fsl,imx6sl-ccm";
 506                                 reg = <0x020c4000 0x4000>;
 507                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 508                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 509                                 #clock-cells = <1>;
 510                         };
 511
 512                         anatop: anatop@20c8000 {
 513                                 compatible = "fsl,imx6sl-anatop",
 514                                              "fsl,imx6q-anatop",
 515                                              "syscon", "simple-bus";
 516                                 reg = <0x020c8000 0x1000>;
 517                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 518                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 519                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 520
 521                                 regulator-1p1 {
 522                                         compatible = "fsl,anatop-regulator";
 523                                         regulator-name = "vdd1p1";
 524                                         regulator-min-microvolt = <800000>;
 525                                         regulator-max-microvolt = <1375000>;
 526                                         regulator-always-on;
 527                                         anatop-reg-offset = <0x110>;
 528                                         anatop-vol-bit-shift = <8>;
 529                                         anatop-vol-bit-width = <5>;
 530                                         anatop-min-bit-val = <4>;
 531                                         anatop-min-voltage = <800000>;
 532                                         anatop-max-voltage = <1375000>;
 533                                         anatop-enable-bit = <0>;
 534                                 };
 535
 536                                 regulator-3p0 {
 537                                         compatible = "fsl,anatop-regulator";
 538                                         regulator-name = "vdd3p0";
 539                                         regulator-min-microvolt = <2800000>;
 540                                         regulator-max-microvolt = <3150000>;
 541                                         regulator-always-on;
 542                                         anatop-reg-offset = <0x120>;
 543                                         anatop-vol-bit-shift = <8>;
 544                                         anatop-vol-bit-width = <5>;
 545                                         anatop-min-bit-val = <0>;
 546                                         anatop-min-voltage = <2625000>;
 547                                         anatop-max-voltage = <3400000>;
 548                                         anatop-enable-bit = <0>;
 549                                 };
 550
 551                                 regulator-2p5 {
 552                                         compatible = "fsl,anatop-regulator";
 553                                         regulator-name = "vdd2p5";
 554                                         regulator-min-microvolt = <2100000>;
 555                                         regulator-max-microvolt = <2850000>;
 556                                         regulator-always-on;
 557                                         anatop-reg-offset = <0x130>;
 558                                         anatop-vol-bit-shift = <8>;
 559                                         anatop-vol-bit-width = <5>;
 560                                         anatop-min-bit-val = <0>;
 561                                         anatop-min-voltage = <2100000>;
 562                                         anatop-max-voltage = <2850000>;
 563                                         anatop-enable-bit = <0>;
 564                                 };
 565
 566                                 reg_arm: regulator-vddcore {
 567                                         compatible = "fsl,anatop-regulator";
 568                                         regulator-name = "vddarm";
 569                                         regulator-min-microvolt = <725000>;
 570                                         regulator-max-microvolt = <1450000>;
 571                                         regulator-always-on;
 572                                         anatop-reg-offset = <0x140>;
 573                                         anatop-vol-bit-shift = <0>;
 574                                         anatop-vol-bit-width = <5>;
 575                                         anatop-delay-reg-offset = <0x170>;
 576                                         anatop-delay-bit-shift = <24>;
 577                                         anatop-delay-bit-width = <2>;
 578                                         anatop-min-bit-val = <1>;
 579                                         anatop-min-voltage = <725000>;
 580                                         anatop-max-voltage = <1450000>;
 581                                 };
 582
 583                                 reg_pu: regulator-vddpu {
 584                                         compatible = "fsl,anatop-regulator";
 585                                         regulator-name = "vddpu";
 586                                         regulator-min-microvolt = <725000>;
 587                                         regulator-max-microvolt = <1450000>;
 588                                         regulator-always-on;
 589                                         anatop-reg-offset = <0x140>;
 590                                         anatop-vol-bit-shift = <9>;
 591                                         anatop-vol-bit-width = <5>;
 592                                         anatop-delay-reg-offset = <0x170>;
 593                                         anatop-delay-bit-shift = <26>;
 594                                         anatop-delay-bit-width = <2>;
 595                                         anatop-min-bit-val = <1>;
 596                                         anatop-min-voltage = <725000>;
 597                                         anatop-max-voltage = <1450000>;
 598                                 };
 599
 600                                 reg_soc: regulator-vddsoc {
 601                                         compatible = "fsl,anatop-regulator";
 602                                         regulator-name = "vddsoc";
 603                                         regulator-min-microvolt = <725000>;
 604                                         regulator-max-microvolt = <1450000>;
 605                                         regulator-always-on;
 606                                         anatop-reg-offset = <0x140>;
 607                                         anatop-vol-bit-shift = <18>;
 608                                         anatop-vol-bit-width = <5>;
 609                                         anatop-delay-reg-offset = <0x170>;
 610                                         anatop-delay-bit-shift = <28>;
 611                                         anatop-delay-bit-width = <2>;
 612                                         anatop-min-bit-val = <1>;
 613                                         anatop-min-voltage = <725000>;
 614                                         anatop-max-voltage = <1450000>;
 615                                 };
 616                         };
 617
 618                         tempmon: tempmon {
 619                                 compatible = "fsl,imx6q-tempmon";
 620                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 621                                 fsl,tempmon = <&anatop>;
 622                                 fsl,tempmon-data = <&ocotp>;
 623                                 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 624                         };
 625
 626                         usbphy1: usbphy@20c9000 {
 627                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 628                                 reg = <0x020c9000 0x1000>;
 629                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 630                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 631                                 fsl,anatop = <&anatop>;
 632                         };
 633
 634                         usbphy2: usbphy@20ca000 {
 635                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 636                                 reg = <0x020ca000 0x1000>;
 637                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 638                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 639                                 fsl,anatop = <&anatop>;
 640                         };
 641
 642                         snvs: snvs@20cc000 {
 643                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 644                                 reg = <0x020cc000 0x4000>;
 645
 646                                 snvs_rtc: snvs-rtc-lp {
 647                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 648                                         regmap = <&snvs>;
 649                                         offset = <0x34>;
 650                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 651                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 652                                 };
 653
 654                                 snvs_poweroff: snvs-poweroff {
 655                                         compatible = "syscon-poweroff";
 656                                         regmap = <&snvs>;
 657                                         offset = <0x38>;
 658                                         value = <0x60>;
 659                                         mask = <0x60>;
 660                                         status = "disabled";
 661                                 };
 662                         };
 663
 664                         epit1: epit@20d0000 {
 665                                 reg = <0x020d0000 0x4000>;
 666                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 667                         };
 668
 669                         epit2: epit@20d4000 {
 670                                 reg = <0x020d4000 0x4000>;
 671                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 672                         };
 673
 674                         src: src@20d8000 {
 675                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 676                                 reg = <0x020d8000 0x4000>;
 677                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 678                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 679                                 #reset-cells = <1>;
 680                         };
 681
 682                         gpc: gpc@20dc000 {
 683                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 684                                 reg = <0x020dc000 0x4000>;
 685                                 interrupt-controller;
 686                                 #interrupt-cells = <3>;
 687                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 688                                 interrupt-parent = <&intc>;
 689                                 pu-supply = <&reg_pu>;
 690                                 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
 691                                          <&clks IMX6SL_CLK_GPU2D_PODF>;
 692                                 #power-domain-cells = <1>;
 693                         };
 694
 695                         gpr: iomuxc-gpr@20e0000 {
 696                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 697                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 698                                 reg = <0x020e0000 0x38>;
 699                         };
 700
 701                         iomuxc: iomuxc@20e0000 {
 702                                 compatible = "fsl,imx6sl-iomuxc";
 703                                 reg = <0x020e0000 0x4000>;
 704                         };
 705
 706                         csi: csi@20e4000 {
 707                                 reg = <0x020e4000 0x4000>;
 708                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 709                         };
 710
 711                         spdc: spdc@20e8000 {
 712                                 reg = <0x020e8000 0x4000>;
 713                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 714                         };
 715
 716                         sdma: sdma@20ec000 {
 717                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 718                                 reg = <0x020ec000 0x4000>;
 719                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 720                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 721                                          <&clks IMX6SL_CLK_SDMA>;
 722                                 clock-names = "ipg", "ahb";
 723                                 #dma-cells = <3>;
 724                                 /* imx6sl reuses imx6q sdma firmware */
 725                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 726                         };
 727
 728                         pxp: pxp@20f0000 {
 729                                 reg = <0x020f0000 0x4000>;
 730                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 731                         };
 732
 733                         epdc: epdc@20f4000 {
 734                                 reg = <0x020f4000 0x4000>;
 735                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 736                         };
 737
 738                         lcdif: lcdif@20f8000 {
 739                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 740                                 reg = <0x020f8000 0x4000>;
 741                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 742                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 743                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 744                                          <&clks IMX6SL_CLK_DUMMY>;
 745                                 clock-names = "pix", "axi", "disp_axi";
 746                                 status = "disabled";
 747                         };
 748
 749                         dcp: dcp@20fc000 {
 750                                 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
 751                                 reg = <0x020fc000 0x4000>;
 752                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 753                                              <0 100 IRQ_TYPE_LEVEL_HIGH>,
 754                                              <0 101 IRQ_TYPE_LEVEL_HIGH>;
 755                         };
 756                 };
 757
 758                 aips2: aips-bus@2100000 {
 759                         compatible = "fsl,aips-bus", "simple-bus";
 760                         #address-cells = <1>;
 761                         #size-cells = <1>;
 762                         reg = <0x02100000 0x100000>;
 763                         ranges;
 764
 765                         usbotg1: usb@2184000 {
 766                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 767                                 reg = <0x02184000 0x200>;
 768                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 769                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 770                                 fsl,usbphy = <&usbphy1>;
 771                                 fsl,usbmisc = <&usbmisc 0>;
 772                                 ahb-burst-config = <0x0>;
 773                                 tx-burst-size-dword = <0x10>;
 774                                 rx-burst-size-dword = <0x10>;
 775                                 status = "disabled";
 776                         };
 777
 778                         usbotg2: usb@2184200 {
 779                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 780                                 reg = <0x02184200 0x200>;
 781                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 782                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 783                                 fsl,usbphy = <&usbphy2>;
 784                                 fsl,usbmisc = <&usbmisc 1>;
 785                                 ahb-burst-config = <0x0>;
 786                                 tx-burst-size-dword = <0x10>;
 787                                 rx-burst-size-dword = <0x10>;
 788                                 status = "disabled";
 789                         };
 790
 791                         usbh: usb@2184400 {
 792                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 793                                 reg = <0x02184400 0x200>;
 794                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 795                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 796                                 fsl,usbmisc = <&usbmisc 2>;
 797                                 dr_mode = "host";
 798                                 ahb-burst-config = <0x0>;
 799                                 tx-burst-size-dword = <0x10>;
 800                                 rx-burst-size-dword = <0x10>;
 801                                 status = "disabled";
 802                         };
 803
 804                         usbmisc: usbmisc@2184800 {
 805                                 #index-cells = <1>;
 806                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 807                                 reg = <0x02184800 0x200>;
 808                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 809                         };
 810
 811                         fec: ethernet@2188000 {
 812                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 813                                 reg = <0x02188000 0x4000>;
 814                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 815                                 clocks = <&clks IMX6SL_CLK_ENET>,
 816                                          <&clks IMX6SL_CLK_ENET_REF>;
 817                                 clock-names = "ipg", "ahb";
 818                                 status = "disabled";
 819                         };
 820
 821                         usdhc1: usdhc@2190000 {
 822                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 823                                 reg = <0x02190000 0x4000>;
 824                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 825                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 826                                          <&clks IMX6SL_CLK_USDHC1>,
 827                                          <&clks IMX6SL_CLK_USDHC1>;
 828                                 clock-names = "ipg", "ahb", "per";
 829                                 bus-width = <4>;
 830                                 status = "disabled";
 831                         };
 832
 833                         usdhc2: usdhc@2194000 {
 834                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 835                                 reg = <0x02194000 0x4000>;
 836                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 837                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 838                                          <&clks IMX6SL_CLK_USDHC2>,
 839                                          <&clks IMX6SL_CLK_USDHC2>;
 840                                 clock-names = "ipg", "ahb", "per";
 841                                 bus-width = <4>;
 842                                 status = "disabled";
 843                         };
 844
 845                         usdhc3: usdhc@2198000 {
 846                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 847                                 reg = <0x02198000 0x4000>;
 848                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 849                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 850                                          <&clks IMX6SL_CLK_USDHC3>,
 851                                          <&clks IMX6SL_CLK_USDHC3>;
 852                                 clock-names = "ipg", "ahb", "per";
 853                                 bus-width = <4>;
 854                                 status = "disabled";
 855                         };
 856
 857                         usdhc4: usdhc@219c000 {
 858                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 859                                 reg = <0x0219c000 0x4000>;
 860                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 861                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 862                                          <&clks IMX6SL_CLK_USDHC4>,
 863                                          <&clks IMX6SL_CLK_USDHC4>;
 864                                 clock-names = "ipg", "ahb", "per";
 865                                 bus-width = <4>;
 866                                 status = "disabled";
 867                         };
 868
 869                         i2c1: i2c@21a0000 {
 870                                 #address-cells = <1>;
 871                                 #size-cells = <0>;
 872                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 873                                 reg = <0x021a0000 0x4000>;
 874                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 875                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 876                                 status = "disabled";
 877                         };
 878
 879                         i2c2: i2c@21a4000 {
 880                                 #address-cells = <1>;
 881                                 #size-cells = <0>;
 882                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 883                                 reg = <0x021a4000 0x4000>;
 884                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 885                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 886                                 status = "disabled";
 887                         };
 888
 889                         i2c3: i2c@21a8000 {
 890                                 #address-cells = <1>;
 891                                 #size-cells = <0>;
 892                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 893                                 reg = <0x021a8000 0x4000>;
 894                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 895                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 896                                 status = "disabled";
 897                         };
 898
 899                         mmdc: mmdc@21b0000 {
 900                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 901                                 reg = <0x021b0000 0x4000>;
 902                         };
 903
 904                         rngb: rngb@21b4000 {
 905                                 reg = <0x021b4000 0x4000>;
 906                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 907                         };
 908
 909                         weim: weim@21b8000 {
 910                                 #address-cells = <2>;
 911                                 #size-cells = <1>;
 912                                 reg = <0x021b8000 0x4000>;
 913                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 914                                 fsl,weim-cs-gpr = <&gpr>;
 915                                 status = "disabled";
 916                         };
 917
 918                         ocotp: ocotp@21bc000 {
 919                                 compatible = "fsl,imx6sl-ocotp", "syscon";
 920                                 reg = <0x021bc000 0x4000>;
 921                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 922                         };
 923
 924                         audmux: audmux@21d8000 {
 925                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 926                                 reg = <0x021d8000 0x4000>;
 927                                 status = "disabled";
 928                         };
 929                 };
 930         };
 931 };