Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6qp.dtsi
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Copyright 2016 Freescale Semiconductor, Inc.
4
5 #include "imx6q.dtsi"
6
7 / {
8         soc {
9                 ocram2: sram@940000 {
10                         compatible = "mmio-sram";
11                         reg = <0x00940000 0x20000>;
12                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
13                 };
14
15                 ocram3: sram@960000 {
16                         compatible = "mmio-sram";
17                         reg = <0x00960000 0x20000>;
18                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
19                 };
20
21                 aips-bus@2100000 {
22                         pre1: pre@21c8000 {
23                                 compatible = "fsl,imx6qp-pre";
24                                 reg = <0x021c8000 0x1000>;
25                                 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
26                                 clocks = <&clks IMX6QDL_CLK_PRE0>;
27                                 clock-names = "axi";
28                                 fsl,iram = <&ocram2>;
29                         };
30
31                         pre2: pre@21c9000 {
32                                 compatible = "fsl,imx6qp-pre";
33                                 reg = <0x021c9000 0x1000>;
34                                 interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
35                                 clocks = <&clks IMX6QDL_CLK_PRE1>;
36                                 clock-names = "axi";
37                                 fsl,iram = <&ocram2>;
38                         };
39
40                         pre3: pre@21ca000 {
41                                 compatible = "fsl,imx6qp-pre";
42                                 reg = <0x021ca000 0x1000>;
43                                 interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
44                                 clocks = <&clks IMX6QDL_CLK_PRE2>;
45                                 clock-names = "axi";
46                                 fsl,iram = <&ocram3>;
47                         };
48
49                         pre4: pre@21cb000 {
50                                 compatible = "fsl,imx6qp-pre";
51                                 reg = <0x021cb000 0x1000>;
52                                 interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
53                                 clocks = <&clks IMX6QDL_CLK_PRE3>;
54                                 clock-names = "axi";
55                                 fsl,iram = <&ocram3>;
56                         };
57
58                         prg1: prg@21cc000 {
59                                 compatible = "fsl,imx6qp-prg";
60                                 reg = <0x021cc000 0x1000>;
61                                 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
62                                          <&clks IMX6QDL_CLK_PRG0_AXI>;
63                                 clock-names = "ipg", "axi";
64                                 fsl,pres = <&pre1>, <&pre2>, <&pre3>;
65                         };
66
67                         prg2: prg@21cd000 {
68                                 compatible = "fsl,imx6qp-prg";
69                                 reg = <0x021cd000 0x1000>;
70                                 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
71                                          <&clks IMX6QDL_CLK_PRG1_AXI>;
72                                 clock-names = "ipg", "axi";
73                                 fsl,pres = <&pre4>, <&pre2>, <&pre3>;
74                         };
75                 };
76         };
77 };
78
79 &fec {
80         /delete-property/interrupts-extended;
81         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
82                      <0 119 IRQ_TYPE_LEVEL_HIGH>;
83 };
84
85 &gpc {
86         compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
87 };
88
89 &ipu1 {
90         compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
91         fsl,prg = <&prg1>;
92 };
93
94 &ipu2 {
95         compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
96         fsl,prg = <&prg2>;
97 };
98
99 &ldb {
100         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
101                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
102                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
103                  <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
104         clock-names = "di0_pll", "di1_pll",
105                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
106                       "di0", "di1";
107 };
108
109 &mmdc0 {
110         compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
111 };
112
113 &pcie {
114         compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
115 };