arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19         /*
  20          * The decompressor and also some bootloaders rely on a
  21          * pre-existing /chosen node to be available to insert the
  22          * command line and merge other ATAGS info.
  23          * Also for U-Boot there must be a pre-existing /memory node.
  24          */
  25         chosen {};
  26         memory { device_type = "memory"; reg = <0 0>; };
  27
  28         aliases {
  29                 ethernet0 = &fec;
  30                 can0 = &can1;
  31                 can1 = &can2;
  32                 gpio0 = &gpio1;
  33                 gpio1 = &gpio2;
  34                 gpio2 = &gpio3;
  35                 gpio3 = &gpio4;
  36                 gpio4 = &gpio5;
  37                 gpio5 = &gpio6;
  38                 gpio6 = &gpio7;
  39                 i2c0 = &i2c1;
  40                 i2c1 = &i2c2;
  41                 i2c2 = &i2c3;
  42                 ipu0 = &ipu1;
  43                 mmc0 = &usdhc1;
  44                 mmc1 = &usdhc2;
  45                 mmc2 = &usdhc3;
  46                 mmc3 = &usdhc4;
  47                 serial0 = &uart1;
  48                 serial1 = &uart2;
  49                 serial2 = &uart3;
  50                 serial3 = &uart4;
  51                 serial4 = &uart5;
  52                 spi0 = &ecspi1;
  53                 spi1 = &ecspi2;
  54                 spi2 = &ecspi3;
  55                 spi3 = &ecspi4;
  56                 usbphy0 = &usbphy1;
  57                 usbphy1 = &usbphy2;
  58         };
  59
  60         clocks {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 ckil {
  65                         compatible = "fsl,imx-ckil", "fixed-clock";
  66                         #clock-cells = <0>;
  67                         clock-frequency = <32768>;
  68                 };
  69
  70                 ckih1 {
  71                         compatible = "fsl,imx-ckih1", "fixed-clock";
  72                         #clock-cells = <0>;
  73                         clock-frequency = <0>;
  74                 };
  75
  76                 osc {
  77                         compatible = "fsl,imx-osc", "fixed-clock";
  78                         #clock-cells = <0>;
  79                         clock-frequency = <24000000>;
  80                 };
  81         };
  82
  83         soc {
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 compatible = "simple-bus";
  87                 interrupt-parent = <&gpc>;
  88                 ranges;
  89
  90                 dma_apbh: dma-apbh@00110000 {
  91                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  92                         reg = <0x00110000 0x2000>;
  93                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  95                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  96                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  97                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  98                         #dma-cells = <1>;
  99                         dma-channels = <4>;
 100                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
 101                 };
 102
 103                 gpmi: gpmi-nand@00112000 {
 104                         compatible = "fsl,imx6q-gpmi-nand";
 105                         #address-cells = <1>;
 106                         #size-cells = <1>;
 107                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 108                         reg-names = "gpmi-nand", "bch";
 109                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 110                         interrupt-names = "bch";
 111                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 112                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 113                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 114                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 115                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 116                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 117                                       "gpmi_bch_apb", "per1_bch";
 118                         dmas = <&dma_apbh 0>;
 119                         dma-names = "rx-tx";
 120                         status = "disabled";
 121                 };
 122
 123                 hdmi: hdmi@0120000 {
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         reg = <0x00120000 0x9000>;
 127                         interrupts = <0 115 0x04>;
 128                         gpr = <&gpr>;
 129                         clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
 130                                  <&clks IMX6QDL_CLK_HDMI_ISFR>;
 131                         clock-names = "iahb", "isfr";
 132                         status = "disabled";
 133
 134                         port@0 {
 135                                 reg = <0>;
 136
 137                                 hdmi_mux_0: endpoint {
 138                                         remote-endpoint = <&ipu1_di0_hdmi>;
 139                                 };
 140                         };
 141
 142                         port@1 {
 143                                 reg = <1>;
 144
 145                                 hdmi_mux_1: endpoint {
 146                                         remote-endpoint = <&ipu1_di1_hdmi>;
 147                                 };
 148                         };
 149                 };
 150
 151                 gpu_3d: gpu@00130000 {
 152                         compatible = "vivante,gc";
 153                         reg = <0x00130000 0x4000>;
 154                         interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 155                         clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
 156                                  <&clks IMX6QDL_CLK_GPU3D_CORE>,
 157                                  <&clks IMX6QDL_CLK_GPU3D_SHADER>;
 158                         clock-names = "bus", "core", "shader";
 159                         power-domains = <&pd_pu>;
 160                 };
 161
 162                 gpu_2d: gpu@00134000 {
 163                         compatible = "vivante,gc";
 164                         reg = <0x00134000 0x4000>;
 165                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 166                         clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
 167                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 168                         clock-names = "bus", "core";
 169                         power-domains = <&pd_pu>;
 170                 };
 171
 172                 timer@00a00600 {
 173                         compatible = "arm,cortex-a9-twd-timer";
 174                         reg = <0x00a00600 0x20>;
 175                         interrupts = <1 13 0xf01>;
 176                         interrupt-parent = <&intc>;
 177                         clocks = <&clks IMX6QDL_CLK_TWD>;
 178                 };
 179
 180                 intc: interrupt-controller@00a01000 {
 181                         compatible = "arm,cortex-a9-gic";
 182                         #interrupt-cells = <3>;
 183                         interrupt-controller;
 184                         reg = <0x00a01000 0x1000>,
 185                               <0x00a00100 0x100>;
 186                         interrupt-parent = <&intc>;
 187                 };
 188
 189                 L2: l2-cache@00a02000 {
 190                         compatible = "arm,pl310-cache";
 191                         reg = <0x00a02000 0x1000>;
 192                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 193                         cache-unified;
 194                         cache-level = <2>;
 195                         arm,tag-latency = <4 2 3>;
 196                         arm,data-latency = <4 2 3>;
 197                         arm,shared-override;
 198                 };
 199
 200                 pcie: pcie@1ffc000 {
 201                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 202                         reg = <0x01ffc000 0x04000>,
 203                               <0x01f00000 0x80000>;
 204                         reg-names = "dbi", "config";
 205                         #address-cells = <3>;
 206                         #size-cells = <2>;
 207                         device_type = "pci";
 208                         bus-range = <0x00 0xff>;
 209                         ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 210                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 211                         num-lanes = <1>;
 212                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 213                         interrupt-names = "msi";
 214                         #interrupt-cells = <1>;
 215                         interrupt-map-mask = <0 0 0 0x7>;
 216                         interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 217                                         <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 218                                         <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 219                                         <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 220                         clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
 221                                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
 222                                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 223                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 224                         status = "disabled";
 225                 };
 226
 227                 pmu {
 228                         compatible = "arm,cortex-a9-pmu";
 229                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 230                 };
 231
 232                 aips-bus@02000000 { /* AIPS1 */
 233                         compatible = "fsl,aips-bus", "simple-bus";
 234                         #address-cells = <1>;
 235                         #size-cells = <1>;
 236                         reg = <0x02000000 0x100000>;
 237                         ranges;
 238
 239                         spba-bus@02000000 {
 240                                 compatible = "fsl,spba-bus", "simple-bus";
 241                                 #address-cells = <1>;
 242                                 #size-cells = <1>;
 243                                 reg = <0x02000000 0x40000>;
 244                                 ranges;
 245
 246                                 spdif: spdif@02004000 {
 247                                         compatible = "fsl,imx35-spdif";
 248                                         reg = <0x02004000 0x4000>;
 249                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 250                                         dmas = <&sdma 14 18 0>,
 251                                                <&sdma 15 18 0>;
 252                                         dma-names = "rx", "tx";
 253                                         clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
 254                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
 255                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 256                                                  <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
 257                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
 258                                         clock-names = "core",  "rxtx0",
 259                                                       "rxtx1", "rxtx2",
 260                                                       "rxtx3", "rxtx4",
 261                                                       "rxtx5", "rxtx6",
 262                                                       "rxtx7", "spba";
 263                                         status = "disabled";
 264                                 };
 265
 266                                 ecspi1: ecspi@02008000 {
 267                                         #address-cells = <1>;
 268                                         #size-cells = <0>;
 269                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 270                                         reg = <0x02008000 0x4000>;
 271                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 272                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 273                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 274                                         clock-names = "ipg", "per";
 275                                         dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
 276                                         dma-names = "rx", "tx";
 277                                         status = "disabled";
 278                                 };
 279
 280                                 ecspi2: ecspi@0200c000 {
 281                                         #address-cells = <1>;
 282                                         #size-cells = <0>;
 283                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 284                                         reg = <0x0200c000 0x4000>;
 285                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 286                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 287                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 288                                         clock-names = "ipg", "per";
 289                                         dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
 290                                         dma-names = "rx", "tx";
 291                                         status = "disabled";
 292                                 };
 293
 294                                 ecspi3: ecspi@02010000 {
 295                                         #address-cells = <1>;
 296                                         #size-cells = <0>;
 297                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 298                                         reg = <0x02010000 0x4000>;
 299                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 300                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 301                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 302                                         clock-names = "ipg", "per";
 303                                         dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
 304                                         dma-names = "rx", "tx";
 305                                         status = "disabled";
 306                                 };
 307
 308                                 ecspi4: ecspi@02014000 {
 309                                         #address-cells = <1>;
 310                                         #size-cells = <0>;
 311                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 312                                         reg = <0x02014000 0x4000>;
 313                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 314                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 315                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 316                                         clock-names = "ipg", "per";
 317                                         dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
 318                                         dma-names = "rx", "tx";
 319                                         status = "disabled";
 320                                 };
 321
 322                                 uart1: serial@02020000 {
 323                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 324                                         reg = <0x02020000 0x4000>;
 325                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 326                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 327                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 328                                         clock-names = "ipg", "per";
 329                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 330                                         dma-names = "rx", "tx";
 331                                         status = "disabled";
 332                                 };
 333
 334                                 esai: esai@02024000 {
 335                                         #sound-dai-cells = <0>;
 336                                         compatible = "fsl,imx35-esai";
 337                                         reg = <0x02024000 0x4000>;
 338                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 339                                         clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
 340                                                  <&clks IMX6QDL_CLK_ESAI_MEM>,
 341                                                  <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 342                                                  <&clks IMX6QDL_CLK_ESAI_IPG>,
 343                                                  <&clks IMX6QDL_CLK_SPBA>;
 344                                         clock-names = "core", "mem", "extal", "fsys", "spba";
 345                                         dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
 346                                         dma-names = "rx", "tx";
 347                                         status = "disabled";
 348                                 };
 349
 350                                 ssi1: ssi@02028000 {
 351                                         #sound-dai-cells = <0>;
 352                                         compatible = "fsl,imx6q-ssi",
 353                                                         "fsl,imx51-ssi";
 354                                         reg = <0x02028000 0x4000>;
 355                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 356                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
 357                                                  <&clks IMX6QDL_CLK_SSI1>;
 358                                         clock-names = "ipg", "baud";
 359                                         dmas = <&sdma 37 1 0>,
 360                                                <&sdma 38 1 0>;
 361                                         dma-names = "rx", "tx";
 362                                         fsl,fifo-depth = <15>;
 363                                         status = "disabled";
 364                                 };
 365
 366                                 ssi2: ssi@0202c000 {
 367                                         #sound-dai-cells = <0>;
 368                                         compatible = "fsl,imx6q-ssi",
 369                                                         "fsl,imx51-ssi";
 370                                         reg = <0x0202c000 0x4000>;
 371                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 372                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
 373                                                  <&clks IMX6QDL_CLK_SSI2>;
 374                                         clock-names = "ipg", "baud";
 375                                         dmas = <&sdma 41 1 0>,
 376                                                <&sdma 42 1 0>;
 377                                         dma-names = "rx", "tx";
 378                                         fsl,fifo-depth = <15>;
 379                                         status = "disabled";
 380                                 };
 381
 382                                 ssi3: ssi@02030000 {
 383                                         #sound-dai-cells = <0>;
 384                                         compatible = "fsl,imx6q-ssi",
 385                                                         "fsl,imx51-ssi";
 386                                         reg = <0x02030000 0x4000>;
 387                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 388                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
 389                                                  <&clks IMX6QDL_CLK_SSI3>;
 390                                         clock-names = "ipg", "baud";
 391                                         dmas = <&sdma 45 1 0>,
 392                                                <&sdma 46 1 0>;
 393                                         dma-names = "rx", "tx";
 394                                         fsl,fifo-depth = <15>;
 395                                         status = "disabled";
 396                                 };
 397
 398                                 asrc: asrc@02034000 {
 399                                         compatible = "fsl,imx53-asrc";
 400                                         reg = <0x02034000 0x4000>;
 401                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 402                                         clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
 403                                                 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
 404                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 405                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 406                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 407                                                 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
 408                                                 <&clks IMX6QDL_CLK_SPBA>;
 409                                         clock-names = "mem", "ipg", "asrck_0",
 410                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 411                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 412                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 413                                                 "asrck_d", "asrck_e", "asrck_f", "spba";
 414                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 415                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 416                                         dma-names = "rxa", "rxb", "rxc",
 417                                                         "txa", "txb", "txc";
 418                                         fsl,asrc-rate  = <48000>;
 419                                         fsl,asrc-width = <16>;
 420                                         status = "okay";
 421                                 };
 422
 423                                 spba@0203c000 {
 424                                         reg = <0x0203c000 0x4000>;
 425                                 };
 426                         };
 427
 428                         vpu: vpu@02040000 {
 429                                 compatible = "cnm,coda960";
 430                                 reg = <0x02040000 0x3c000>;
 431                                 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
 432                                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 433                                 interrupt-names = "bit", "jpeg";
 434                                 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 435                                          <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
 436                                 clock-names = "per", "ahb";
 437                                 power-domains = <&pd_pu>;
 438                                 resets = <&src 1>;
 439                                 iram = <&ocram>;
 440                         };
 441
 442                         aipstz@0207c000 { /* AIPSTZ1 */
 443                                 reg = <0x0207c000 0x4000>;
 444                         };
 445
 446                         pwm1: pwm@02080000 {
 447                                 #pwm-cells = <2>;
 448                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 449                                 reg = <0x02080000 0x4000>;
 450                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 451                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 452                                          <&clks IMX6QDL_CLK_PWM1>;
 453                                 clock-names = "ipg", "per";
 454                                 status = "disabled";
 455                         };
 456
 457                         pwm2: pwm@02084000 {
 458                                 #pwm-cells = <2>;
 459                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 460                                 reg = <0x02084000 0x4000>;
 461                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 462                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 463                                          <&clks IMX6QDL_CLK_PWM2>;
 464                                 clock-names = "ipg", "per";
 465                                 status = "disabled";
 466                         };
 467
 468                         pwm3: pwm@02088000 {
 469                                 #pwm-cells = <2>;
 470                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 471                                 reg = <0x02088000 0x4000>;
 472                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 473                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 474                                          <&clks IMX6QDL_CLK_PWM3>;
 475                                 clock-names = "ipg", "per";
 476                                 status = "disabled";
 477                         };
 478
 479                         pwm4: pwm@0208c000 {
 480                                 #pwm-cells = <2>;
 481                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 482                                 reg = <0x0208c000 0x4000>;
 483                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 484                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 485                                          <&clks IMX6QDL_CLK_PWM4>;
 486                                 clock-names = "ipg", "per";
 487                                 status = "disabled";
 488                         };
 489
 490                         can1: flexcan@02090000 {
 491                                 compatible = "fsl,imx6q-flexcan";
 492                                 reg = <0x02090000 0x4000>;
 493                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 494                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 495                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 496                                 clock-names = "ipg", "per";
 497                                 status = "disabled";
 498                         };
 499
 500                         can2: flexcan@02094000 {
 501                                 compatible = "fsl,imx6q-flexcan";
 502                                 reg = <0x02094000 0x4000>;
 503                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 505                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 506                                 clock-names = "ipg", "per";
 507                                 status = "disabled";
 508                         };
 509
 510                         gpt: gpt@02098000 {
 511                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 512                                 reg = <0x02098000 0x4000>;
 513                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 514                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 515                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>,
 516                                          <&clks IMX6QDL_CLK_GPT_3M>;
 517                                 clock-names = "ipg", "per", "osc_per";
 518                         };
 519
 520                         gpio1: gpio@0209c000 {
 521                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 522                                 reg = <0x0209c000 0x4000>;
 523                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 524                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 525                                 gpio-controller;
 526                                 #gpio-cells = <2>;
 527                                 interrupt-controller;
 528                                 #interrupt-cells = <2>;
 529                         };
 530
 531                         gpio2: gpio@020a0000 {
 532                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 533                                 reg = <0x020a0000 0x4000>;
 534                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 535                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 536                                 gpio-controller;
 537                                 #gpio-cells = <2>;
 538                                 interrupt-controller;
 539                                 #interrupt-cells = <2>;
 540                         };
 541
 542                         gpio3: gpio@020a4000 {
 543                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 544                                 reg = <0x020a4000 0x4000>;
 545                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 546                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 547                                 gpio-controller;
 548                                 #gpio-cells = <2>;
 549                                 interrupt-controller;
 550                                 #interrupt-cells = <2>;
 551                         };
 552
 553                         gpio4: gpio@020a8000 {
 554                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 555                                 reg = <0x020a8000 0x4000>;
 556                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 557                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 558                                 gpio-controller;
 559                                 #gpio-cells = <2>;
 560                                 interrupt-controller;
 561                                 #interrupt-cells = <2>;
 562                         };
 563
 564                         gpio5: gpio@020ac000 {
 565                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 566                                 reg = <0x020ac000 0x4000>;
 567                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 568                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 569                                 gpio-controller;
 570                                 #gpio-cells = <2>;
 571                                 interrupt-controller;
 572                                 #interrupt-cells = <2>;
 573                         };
 574
 575                         gpio6: gpio@020b0000 {
 576                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 577                                 reg = <0x020b0000 0x4000>;
 578                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 579                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 580                                 gpio-controller;
 581                                 #gpio-cells = <2>;
 582                                 interrupt-controller;
 583                                 #interrupt-cells = <2>;
 584                         };
 585
 586                         gpio7: gpio@020b4000 {
 587                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 588                                 reg = <0x020b4000 0x4000>;
 589                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 590                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 591                                 gpio-controller;
 592                                 #gpio-cells = <2>;
 593                                 interrupt-controller;
 594                                 #interrupt-cells = <2>;
 595                         };
 596
 597                         kpp: kpp@020b8000 {
 598                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 599                                 reg = <0x020b8000 0x4000>;
 600                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 601                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 602                                 status = "disabled";
 603                         };
 604
 605                         wdog1: wdog@020bc000 {
 606                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 607                                 reg = <0x020bc000 0x4000>;
 608                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 609                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 610                         };
 611
 612                         wdog2: wdog@020c0000 {
 613                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 614                                 reg = <0x020c0000 0x4000>;
 615                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 616                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 617                                 status = "disabled";
 618                         };
 619
 620                         clks: ccm@020c4000 {
 621                                 compatible = "fsl,imx6q-ccm";
 622                                 reg = <0x020c4000 0x4000>;
 623                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 624                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 625                                 #clock-cells = <1>;
 626                         };
 627
 628                         anatop: anatop@020c8000 {
 629                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 630                                 reg = <0x020c8000 0x1000>;
 631                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 632                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 633                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 634
 635                                 regulator-1p1 {
 636                                         compatible = "fsl,anatop-regulator";
 637                                         regulator-name = "vdd1p1";
 638                                         regulator-min-microvolt = <1000000>;
 639                                         regulator-max-microvolt = <1200000>;
 640                                         regulator-always-on;
 641                                         anatop-reg-offset = <0x110>;
 642                                         anatop-vol-bit-shift = <8>;
 643                                         anatop-vol-bit-width = <5>;
 644                                         anatop-min-bit-val = <4>;
 645                                         anatop-min-voltage = <800000>;
 646                                         anatop-max-voltage = <1375000>;
 647                                         anatop-enable-bit = <0>;
 648                                 };
 649
 650                                 regulator-3p0 {
 651                                         compatible = "fsl,anatop-regulator";
 652                                         regulator-name = "vdd3p0";
 653                                         regulator-min-microvolt = <2800000>;
 654                                         regulator-max-microvolt = <3150000>;
 655                                         regulator-always-on;
 656                                         anatop-reg-offset = <0x120>;
 657                                         anatop-vol-bit-shift = <8>;
 658                                         anatop-vol-bit-width = <5>;
 659                                         anatop-min-bit-val = <0>;
 660                                         anatop-min-voltage = <2625000>;
 661                                         anatop-max-voltage = <3400000>;
 662                                         anatop-enable-bit = <0>;
 663                                 };
 664
 665                                 regulator-2p5 {
 666                                         compatible = "fsl,anatop-regulator";
 667                                         regulator-name = "vdd2p5";
 668                                         regulator-min-microvolt = <2250000>;
 669                                         regulator-max-microvolt = <2750000>;
 670                                         regulator-always-on;
 671                                         anatop-reg-offset = <0x130>;
 672                                         anatop-vol-bit-shift = <8>;
 673                                         anatop-vol-bit-width = <5>;
 674                                         anatop-min-bit-val = <0>;
 675                                         anatop-min-voltage = <2100000>;
 676                                         anatop-max-voltage = <2875000>;
 677                                         anatop-enable-bit = <0>;
 678                                 };
 679
 680                                 reg_arm: regulator-vddcore {
 681                                         compatible = "fsl,anatop-regulator";
 682                                         regulator-name = "vddarm";
 683                                         regulator-min-microvolt = <725000>;
 684                                         regulator-max-microvolt = <1450000>;
 685                                         regulator-always-on;
 686                                         anatop-reg-offset = <0x140>;
 687                                         anatop-vol-bit-shift = <0>;
 688                                         anatop-vol-bit-width = <5>;
 689                                         anatop-delay-reg-offset = <0x170>;
 690                                         anatop-delay-bit-shift = <24>;
 691                                         anatop-delay-bit-width = <2>;
 692                                         anatop-min-bit-val = <1>;
 693                                         anatop-min-voltage = <725000>;
 694                                         anatop-max-voltage = <1450000>;
 695                                 };
 696
 697                                 reg_pu: regulator-vddpu {
 698                                         compatible = "fsl,anatop-regulator";
 699                                         regulator-name = "vddpu";
 700                                         regulator-min-microvolt = <725000>;
 701                                         regulator-max-microvolt = <1450000>;
 702                                         regulator-enable-ramp-delay = <150>;
 703                                         anatop-reg-offset = <0x140>;
 704                                         anatop-vol-bit-shift = <9>;
 705                                         anatop-vol-bit-width = <5>;
 706                                         anatop-delay-reg-offset = <0x170>;
 707                                         anatop-delay-bit-shift = <26>;
 708                                         anatop-delay-bit-width = <2>;
 709                                         anatop-min-bit-val = <1>;
 710                                         anatop-min-voltage = <725000>;
 711                                         anatop-max-voltage = <1450000>;
 712                                 };
 713
 714                                 reg_soc: regulator-vddsoc {
 715                                         compatible = "fsl,anatop-regulator";
 716                                         regulator-name = "vddsoc";
 717                                         regulator-min-microvolt = <725000>;
 718                                         regulator-max-microvolt = <1450000>;
 719                                         regulator-always-on;
 720                                         anatop-reg-offset = <0x140>;
 721                                         anatop-vol-bit-shift = <18>;
 722                                         anatop-vol-bit-width = <5>;
 723                                         anatop-delay-reg-offset = <0x170>;
 724                                         anatop-delay-bit-shift = <28>;
 725                                         anatop-delay-bit-width = <2>;
 726                                         anatop-min-bit-val = <1>;
 727                                         anatop-min-voltage = <725000>;
 728                                         anatop-max-voltage = <1450000>;
 729                                 };
 730                         };
 731
 732                         tempmon: tempmon {
 733                                 compatible = "fsl,imx6q-tempmon";
 734                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 735                                 fsl,tempmon = <&anatop>;
 736                                 fsl,tempmon-data = <&ocotp>;
 737                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 738                         };
 739
 740                         usbphy1: usbphy@020c9000 {
 741                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 742                                 reg = <0x020c9000 0x1000>;
 743                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 744                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 745                                 fsl,anatop = <&anatop>;
 746                         };
 747
 748                         usbphy2: usbphy@020ca000 {
 749                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 750                                 reg = <0x020ca000 0x1000>;
 751                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 752                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 753                                 fsl,anatop = <&anatop>;
 754                         };
 755
 756                         snvs: snvs@020cc000 {
 757                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 758                                 reg = <0x020cc000 0x4000>;
 759
 760                                 snvs_rtc: snvs-rtc-lp {
 761                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 762                                         regmap = <&snvs>;
 763                                         offset = <0x34>;
 764                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 765                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 766                                 };
 767
 768                                 snvs_poweroff: snvs-poweroff {
 769                                         compatible = "syscon-poweroff";
 770                                         regmap = <&snvs>;
 771                                         offset = <0x38>;
 772                                         mask = <0x60>;
 773                                         status = "disabled";
 774                                 };
 775                         };
 776
 777                         epit1: epit@020d0000 { /* EPIT1 */
 778                                 reg = <0x020d0000 0x4000>;
 779                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 780                         };
 781
 782                         epit2: epit@020d4000 { /* EPIT2 */
 783                                 reg = <0x020d4000 0x4000>;
 784                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 785                         };
 786
 787                         src: src@020d8000 {
 788                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 789                                 reg = <0x020d8000 0x4000>;
 790                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 791                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 792                                 #reset-cells = <1>;
 793                         };
 794
 795                         gpc: gpc@020dc000 {
 796                                 compatible = "fsl,imx6q-gpc";
 797                                 reg = <0x020dc000 0x4000>;
 798                                 interrupt-controller;
 799                                 #interrupt-cells = <3>;
 800                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 801                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 802                                 interrupt-parent = <&intc>;
 803                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 804                                 clock-names = "ipg";
 805
 806                                 pgc {
 807                                         #address-cells = <1>;
 808                                         #size-cells = <0>;
 809
 810                                         power-domain@0 {
 811                                                 reg = <0>;
 812                                                 #power-domain-cells = <0>;
 813                                         };
 814                                         pd_pu: power-domain@1 {
 815                                                 reg = <1>;
 816                                                 #power-domain-cells = <0>;
 817                                                 power-supply = <&reg_pu>;
 818                                                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
 819                                                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
 820                                                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
 821                                                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
 822                                                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
 823                                                          <&clks IMX6QDL_CLK_VPU_AXI>;
 824                                         };
 825                                 };
 826                         };
 827
 828                         gpr: iomuxc-gpr@020e0000 {
 829                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
 830                                 reg = <0x020e0000 0x38>;
 831
 832                                 mux: mux-controller {
 833                                         compatible = "mmio-mux";
 834                                         #mux-control-cells = <1>;
 835                                 };
 836                         };
 837
 838                         iomuxc: iomuxc@020e0000 {
 839                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 840                                 reg = <0x020e0000 0x4000>;
 841                         };
 842
 843                         ldb: ldb {
 844                                 #address-cells = <1>;
 845                                 #size-cells = <0>;
 846                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 847                                 gpr = <&gpr>;
 848                                 status = "disabled";
 849
 850                                 lvds-channel@0 {
 851                                         #address-cells = <1>;
 852                                         #size-cells = <0>;
 853                                         reg = <0>;
 854                                         status = "disabled";
 855
 856                                         port@0 {
 857                                                 reg = <0>;
 858
 859                                                 lvds0_mux_0: endpoint {
 860                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 861                                                 };
 862                                         };
 863
 864                                         port@1 {
 865                                                 reg = <1>;
 866
 867                                                 lvds0_mux_1: endpoint {
 868                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 869                                                 };
 870                                         };
 871                                 };
 872
 873                                 lvds-channel@1 {
 874                                         #address-cells = <1>;
 875                                         #size-cells = <0>;
 876                                         reg = <1>;
 877                                         status = "disabled";
 878
 879                                         port@0 {
 880                                                 reg = <0>;
 881
 882                                                 lvds1_mux_0: endpoint {
 883                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 884                                                 };
 885                                         };
 886
 887                                         port@1 {
 888                                                 reg = <1>;
 889
 890                                                 lvds1_mux_1: endpoint {
 891                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 892                                                 };
 893                                         };
 894                                 };
 895                         };
 896
 897                         dcic1: dcic@020e4000 {
 898                                 reg = <0x020e4000 0x4000>;
 899                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 900                         };
 901
 902                         dcic2: dcic@020e8000 {
 903                                 reg = <0x020e8000 0x4000>;
 904                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 905                         };
 906
 907                         sdma: sdma@020ec000 {
 908                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 909                                 reg = <0x020ec000 0x4000>;
 910                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 911                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 912                                          <&clks IMX6QDL_CLK_SDMA>;
 913                                 clock-names = "ipg", "ahb";
 914                                 #dma-cells = <3>;
 915                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 916                         };
 917                 };
 918
 919                 aips-bus@02100000 { /* AIPS2 */
 920                         compatible = "fsl,aips-bus", "simple-bus";
 921                         #address-cells = <1>;
 922                         #size-cells = <1>;
 923                         reg = <0x02100000 0x100000>;
 924                         ranges;
 925
 926                         crypto: caam@2100000 {
 927                                 compatible = "fsl,sec-v4.0";
 928                                 fsl,sec-era = <4>;
 929                                 #address-cells = <1>;
 930                                 #size-cells = <1>;
 931                                 reg = <0x2100000 0x10000>;
 932                                 ranges = <0 0x2100000 0x10000>;
 933                                 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
 934                                          <&clks IMX6QDL_CLK_CAAM_ACLK>,
 935                                          <&clks IMX6QDL_CLK_CAAM_IPG>,
 936                                          <&clks IMX6QDL_CLK_EIM_SLOW>;
 937                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
 938
 939                                 sec_jr0: jr0@1000 {
 940                                         compatible = "fsl,sec-v4.0-job-ring";
 941                                         reg = <0x1000 0x1000>;
 942                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 943                                 };
 944
 945                                 sec_jr1: jr1@2000 {
 946                                         compatible = "fsl,sec-v4.0-job-ring";
 947                                         reg = <0x2000 0x1000>;
 948                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 949                                 };
 950                         };
 951
 952                         aipstz@0217c000 { /* AIPSTZ2 */
 953                                 reg = <0x0217c000 0x4000>;
 954                         };
 955
 956                         usbotg: usb@02184000 {
 957                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 958                                 reg = <0x02184000 0x200>;
 959                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 960                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 961                                 fsl,usbphy = <&usbphy1>;
 962                                 fsl,usbmisc = <&usbmisc 0>;
 963                                 ahb-burst-config = <0x0>;
 964                                 tx-burst-size-dword = <0x10>;
 965                                 rx-burst-size-dword = <0x10>;
 966                                 status = "disabled";
 967                         };
 968
 969                         usbh1: usb@02184200 {
 970                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 971                                 reg = <0x02184200 0x200>;
 972                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 973                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 974                                 fsl,usbphy = <&usbphy2>;
 975                                 fsl,usbmisc = <&usbmisc 1>;
 976                                 dr_mode = "host";
 977                                 ahb-burst-config = <0x0>;
 978                                 tx-burst-size-dword = <0x10>;
 979                                 rx-burst-size-dword = <0x10>;
 980                                 status = "disabled";
 981                         };
 982
 983                         usbh2: usb@02184400 {
 984                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 985                                 reg = <0x02184400 0x200>;
 986                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 987                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 988                                 fsl,usbmisc = <&usbmisc 2>;
 989                                 dr_mode = "host";
 990                                 ahb-burst-config = <0x0>;
 991                                 tx-burst-size-dword = <0x10>;
 992                                 rx-burst-size-dword = <0x10>;
 993                                 status = "disabled";
 994                         };
 995
 996                         usbh3: usb@02184600 {
 997                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 998                                 reg = <0x02184600 0x200>;
 999                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1000                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1001                                 fsl,usbmisc = <&usbmisc 3>;
1002                                 dr_mode = "host";
1003                                 ahb-burst-config = <0x0>;
1004                                 tx-burst-size-dword = <0x10>;
1005                                 rx-burst-size-dword = <0x10>;
1006                                 status = "disabled";
1007                         };
1008
1009                         usbmisc: usbmisc@02184800 {
1010                                 #index-cells = <1>;
1011                                 compatible = "fsl,imx6q-usbmisc";
1012                                 reg = <0x02184800 0x200>;
1013                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1014                         };
1015
1016                         fec: ethernet@02188000 {
1017                                 compatible = "fsl,imx6q-fec";
1018                                 reg = <0x02188000 0x4000>;
1019                                 interrupts-extended =
1020                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
1021                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1022                                 clocks = <&clks IMX6QDL_CLK_ENET>,
1023                                          <&clks IMX6QDL_CLK_ENET>,
1024                                          <&clks IMX6QDL_CLK_ENET_REF>;
1025                                 clock-names = "ipg", "ahb", "ptp";
1026                                 status = "disabled";
1027                         };
1028
1029                         mlb@0218c000 {
1030                                 reg = <0x0218c000 0x4000>;
1031                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1032                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1033                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
1034                         };
1035
1036                         usdhc1: usdhc@02190000 {
1037                                 compatible = "fsl,imx6q-usdhc";
1038                                 reg = <0x02190000 0x4000>;
1039                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1040                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1041                                          <&clks IMX6QDL_CLK_USDHC1>,
1042                                          <&clks IMX6QDL_CLK_USDHC1>;
1043                                 clock-names = "ipg", "ahb", "per";
1044                                 bus-width = <4>;
1045                                 status = "disabled";
1046                         };
1047
1048                         usdhc2: usdhc@02194000 {
1049                                 compatible = "fsl,imx6q-usdhc";
1050                                 reg = <0x02194000 0x4000>;
1051                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1052                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1053                                          <&clks IMX6QDL_CLK_USDHC2>,
1054                                          <&clks IMX6QDL_CLK_USDHC2>;
1055                                 clock-names = "ipg", "ahb", "per";
1056                                 bus-width = <4>;
1057                                 status = "disabled";
1058                         };
1059
1060                         usdhc3: usdhc@02198000 {
1061                                 compatible = "fsl,imx6q-usdhc";
1062                                 reg = <0x02198000 0x4000>;
1063                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1064                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1065                                          <&clks IMX6QDL_CLK_USDHC3>,
1066                                          <&clks IMX6QDL_CLK_USDHC3>;
1067                                 clock-names = "ipg", "ahb", "per";
1068                                 bus-width = <4>;
1069                                 status = "disabled";
1070                         };
1071
1072                         usdhc4: usdhc@0219c000 {
1073                                 compatible = "fsl,imx6q-usdhc";
1074                                 reg = <0x0219c000 0x4000>;
1075                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1076                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1077                                          <&clks IMX6QDL_CLK_USDHC4>,
1078                                          <&clks IMX6QDL_CLK_USDHC4>;
1079                                 clock-names = "ipg", "ahb", "per";
1080                                 bus-width = <4>;
1081                                 status = "disabled";
1082                         };
1083
1084                         i2c1: i2c@021a0000 {
1085                                 #address-cells = <1>;
1086                                 #size-cells = <0>;
1087                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1088                                 reg = <0x021a0000 0x4000>;
1089                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1090                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
1091                                 status = "disabled";
1092                         };
1093
1094                         i2c2: i2c@021a4000 {
1095                                 #address-cells = <1>;
1096                                 #size-cells = <0>;
1097                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1098                                 reg = <0x021a4000 0x4000>;
1099                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1100                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
1101                                 status = "disabled";
1102                         };
1103
1104                         i2c3: i2c@021a8000 {
1105                                 #address-cells = <1>;
1106                                 #size-cells = <0>;
1107                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1108                                 reg = <0x021a8000 0x4000>;
1109                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1110                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
1111                                 status = "disabled";
1112                         };
1113
1114                         romcp@021ac000 {
1115                                 reg = <0x021ac000 0x4000>;
1116                         };
1117
1118                         mmdc0: mmdc@021b0000 { /* MMDC0 */
1119                                 compatible = "fsl,imx6q-mmdc";
1120                                 reg = <0x021b0000 0x4000>;
1121                         };
1122
1123                         mmdc1: mmdc@021b4000 { /* MMDC1 */
1124                                 reg = <0x021b4000 0x4000>;
1125                         };
1126
1127                         weim: weim@021b8000 {
1128                                 #address-cells = <2>;
1129                                 #size-cells = <1>;
1130                                 compatible = "fsl,imx6q-weim";
1131                                 reg = <0x021b8000 0x4000>;
1132                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1133                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1134                                 fsl,weim-cs-gpr = <&gpr>;
1135                                 status = "disabled";
1136                         };
1137
1138                         ocotp: ocotp@021bc000 {
1139                                 compatible = "fsl,imx6q-ocotp", "syscon";
1140                                 reg = <0x021bc000 0x4000>;
1141                                 clocks = <&clks IMX6QDL_CLK_IIM>;
1142                         };
1143
1144                         tzasc@021d0000 { /* TZASC1 */
1145                                 reg = <0x021d0000 0x4000>;
1146                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1147                         };
1148
1149                         tzasc@021d4000 { /* TZASC2 */
1150                                 reg = <0x021d4000 0x4000>;
1151                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1152                         };
1153
1154                         audmux: audmux@021d8000 {
1155                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1156                                 reg = <0x021d8000 0x4000>;
1157                                 status = "disabled";
1158                         };
1159
1160                         mipi_csi: mipi@021dc000 {
1161                                 compatible = "fsl,imx6-mipi-csi2";
1162                                 reg = <0x021dc000 0x4000>;
1163                                 #address-cells = <1>;
1164                                 #size-cells = <0>;
1165                                 interrupts = <0 100 0x04>, <0 101 0x04>;
1166                                 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1167                                          <&clks IMX6QDL_CLK_VIDEO_27M>,
1168                                          <&clks IMX6QDL_CLK_EIM_PODF>;
1169                                 clock-names = "dphy", "ref", "pix";
1170                                 status = "disabled";
1171                         };
1172
1173                         mipi_dsi: mipi@021e0000 {
1174                                 #address-cells = <1>;
1175                                 #size-cells = <0>;
1176                                 reg = <0x021e0000 0x4000>;
1177                                 status = "disabled";
1178
1179                                 ports {
1180                                         #address-cells = <1>;
1181                                         #size-cells = <0>;
1182
1183                                         port@0 {
1184                                                 reg = <0>;
1185
1186                                                 mipi_mux_0: endpoint {
1187                                                         remote-endpoint = <&ipu1_di0_mipi>;
1188                                                 };
1189                                         };
1190
1191                                         port@1 {
1192                                                 reg = <1>;
1193
1194                                                 mipi_mux_1: endpoint {
1195                                                         remote-endpoint = <&ipu1_di1_mipi>;
1196                                                 };
1197                                         };
1198                                 };
1199                         };
1200
1201                         vdoa@021e4000 {
1202                                 compatible = "fsl,imx6q-vdoa";
1203                                 reg = <0x021e4000 0x4000>;
1204                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1205                                 clocks = <&clks IMX6QDL_CLK_VDOA>;
1206                         };
1207
1208                         uart2: serial@021e8000 {
1209                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1210                                 reg = <0x021e8000 0x4000>;
1211                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1212                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1213                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1214                                 clock-names = "ipg", "per";
1215                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1216                                 dma-names = "rx", "tx";
1217                                 status = "disabled";
1218                         };
1219
1220                         uart3: serial@021ec000 {
1221                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1222                                 reg = <0x021ec000 0x4000>;
1223                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1224                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1225                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1226                                 clock-names = "ipg", "per";
1227                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1228                                 dma-names = "rx", "tx";
1229                                 status = "disabled";
1230                         };
1231
1232                         uart4: serial@021f0000 {
1233                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1234                                 reg = <0x021f0000 0x4000>;
1235                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1236                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1237                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1238                                 clock-names = "ipg", "per";
1239                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1240                                 dma-names = "rx", "tx";
1241                                 status = "disabled";
1242                         };
1243
1244                         uart5: serial@021f4000 {
1245                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1246                                 reg = <0x021f4000 0x4000>;
1247                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1248                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1249                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1250                                 clock-names = "ipg", "per";
1251                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1252                                 dma-names = "rx", "tx";
1253                                 status = "disabled";
1254                         };
1255                 };
1256
1257                 ipu1: ipu@02400000 {
1258                         #address-cells = <1>;
1259                         #size-cells = <0>;
1260                         compatible = "fsl,imx6q-ipu";
1261                         reg = <0x02400000 0x400000>;
1262                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1263                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1264                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1265                                  <&clks IMX6QDL_CLK_IPU1_DI0>,
1266                                  <&clks IMX6QDL_CLK_IPU1_DI1>;
1267                         clock-names = "bus", "di0", "di1";
1268                         resets = <&src 2>;
1269
1270                         ipu1_csi0: port@0 {
1271                                 reg = <0>;
1272
1273                                 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1274                                         remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1275                                 };
1276                         };
1277
1278                         ipu1_csi1: port@1 {
1279                                 reg = <1>;
1280                         };
1281
1282                         ipu1_di0: port@2 {
1283                                 #address-cells = <1>;
1284                                 #size-cells = <0>;
1285                                 reg = <2>;
1286
1287                                 ipu1_di0_disp0: disp0-endpoint {
1288                                 };
1289
1290                                 ipu1_di0_hdmi: hdmi-endpoint {
1291                                         remote-endpoint = <&hdmi_mux_0>;
1292                                 };
1293
1294                                 ipu1_di0_mipi: mipi-endpoint {
1295                                         remote-endpoint = <&mipi_mux_0>;
1296                                 };
1297
1298                                 ipu1_di0_lvds0: lvds0-endpoint {
1299                                         remote-endpoint = <&lvds0_mux_0>;
1300                                 };
1301
1302                                 ipu1_di0_lvds1: lvds1-endpoint {
1303                                         remote-endpoint = <&lvds1_mux_0>;
1304                                 };
1305                         };
1306
1307                         ipu1_di1: port@3 {
1308                                 #address-cells = <1>;
1309                                 #size-cells = <0>;
1310                                 reg = <3>;
1311
1312                                 ipu1_di1_disp1: disp1-endpoint {
1313                                 };
1314
1315                                 ipu1_di1_hdmi: hdmi-endpoint {
1316                                         remote-endpoint = <&hdmi_mux_1>;
1317                                 };
1318
1319                                 ipu1_di1_mipi: mipi-endpoint {
1320                                         remote-endpoint = <&mipi_mux_1>;
1321                                 };
1322
1323                                 ipu1_di1_lvds0: lvds0-endpoint {
1324                                         remote-endpoint = <&lvds0_mux_1>;
1325                                 };
1326
1327                                 ipu1_di1_lvds1: lvds1-endpoint {
1328                                         remote-endpoint = <&lvds1_mux_1>;
1329                                 };
1330                         };
1331                 };
1332         };
1333 };