arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi

   1 /*
   2  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/sound/fsl-imx-audmux.h>
  44
  45 / {
  46         chosen {
  47                 stdout-path = &uart1;
  48         };
  49
  50         aliases {
  51                 mdio-gpio0 = &mdio1;
  52                 rtc0 = &ds1341;
  53         };
  54
  55         mdio1: mdio {
  56                 compatible = "virtual,mdio-gpio";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&pinctrl_mdio1>;
  61                 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
  62                          &gpio6 4 GPIO_ACTIVE_HIGH>;
  63
  64                 phy: ethernet-phy@0 {
  65                         pinctrl-0 = <&pinctrl_rmii_phy_irq>;
  66                         pinctrl-names = "default";
  67                         reg = <0>;
  68                         interrupt-parent = <&gpio3>;
  69                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  70                 };
  71         };
  72
  73         reg_28p0v: regulator-28p0v {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "28V_IN";
  76                 regulator-min-microvolt = <28000000>;
  77                 regulator-max-microvolt = <28000000>;
  78                 regulator-always-on;
  79         };
  80
  81         reg_12p0v: regulator-12p0v {
  82                 compatible = "regulator-fixed";
  83                 vin-supply = <&reg_28p0v>;
  84                 regulator-name = "12V_MAIN";
  85                 regulator-min-microvolt = <12000000>;
  86                 regulator-max-microvolt = <12000000>;
  87                 regulator-always-on;
  88         };
  89
  90         reg_5p0v_main: regulator-5p0v-main {
  91                 compatible = "regulator-fixed";
  92                 vin-supply = <&reg_12p0v>;
  93                 regulator-name = "5V_MAIN";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96                 regulator-always-on;
  97         };
  98
  99         reg_5p0v_user_usb: regulator-5p0v-user-usb {
 100                 compatible = "regulator-fixed";
 101                 pinctrl-names = "default";
 102                 pinctrl-0 = <&pinctrl_reg_user_usb>;
 103                 vin-supply = <&reg_5p0v_main>;
 104                 regulator-name = "5V_USER_USB";
 105                 regulator-min-microvolt = <5000000>;
 106                 regulator-max-microvolt = <5000000>;
 107                 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
 108                 startup-delay-us = <1000>;
 109         };
 110
 111         reg_3p3v_pmic: regulator-3p3v-pmic {
 112                 compatible = "regulator-fixed";
 113                 vin-supply = <&reg_12p0v>;
 114                 regulator-name = "PMIC_3V3";
 115                 regulator-min-microvolt = <3300000>;
 116                 regulator-max-microvolt = <3300000>;
 117                 regulator-always-on;
 118         };
 119
 120         reg_3p3v: regulator-3p3v {
 121                 compatible = "regulator-fixed";
 122                 vin-supply = <&reg_3p3v_pmic>;
 123                 regulator-name = "GEN_3V3";
 124                 regulator-min-microvolt = <3300000>;
 125                 regulator-max-microvolt = <3300000>;
 126                 regulator-always-on;
 127         };
 128
 129         reg_3p3v_sd: regulator-3p3v-sd {
 130                 compatible = "regulator-fixed";
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
 133                 vin-supply = <&reg_3p3v>;
 134                 regulator-name = "3V3_SD";
 135                 regulator-min-microvolt = <3300000>;
 136                 regulator-max-microvolt = <3300000>;
 137                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
 138                 startup-delay-us = <1000>;
 139                 enable-active-high;
 140                 regulator-always-on;
 141         };
 142
 143         reg_3p3v_display: regulator-3p3v-display {
 144                 compatible = "regulator-fixed";
 145                 vin-supply = <&reg_12p0v>;
 146                 regulator-name = "3V3_DISPLAY";
 147                 regulator-min-microvolt = <3300000>;
 148                 regulator-max-microvolt = <3300000>;
 149                 regulator-always-on;
 150         };
 151
 152         reg_3p3v_ssd: regulator-3p3v-ssd {
 153                 compatible = "regulator-fixed";
 154                 vin-supply = <&reg_12p0v>;
 155                 regulator-name = "3V3_SSD";
 156                 regulator-min-microvolt = <3300000>;
 157                 regulator-max-microvolt = <3300000>;
 158                 regulator-always-on;
 159         };
 160
 161         sound1 {
 162                 compatible = "simple-audio-card";
 163                 simple-audio-card,name = "Front";
 164                 simple-audio-card,format = "i2s";
 165                 simple-audio-card,bitclock-master = <&sound1_codec>;
 166                 simple-audio-card,frame-master = <&sound1_codec>;
 167                 simple-audio-card,widgets =
 168                         "Headphone", "Headphone Jack";
 169                 simple-audio-card,routing =
 170                         "Headphone Jack", "HPLEFT",
 171                         "Headphone Jack", "HPRIGHT",
 172                         "LEFTIN", "HPL",
 173                         "RIGHTIN", "HPR";
 174                 simple-audio-card,aux-devs = <&hpa1>;
 175
 176                 sound1_cpu: simple-audio-card,cpu {
 177                         sound-dai = <&ssi2>;
 178                 };
 179
 180                 sound1_codec: simple-audio-card,codec {
 181                         sound-dai = <&codec1>;
 182                         clocks = <&cs2000>;
 183                 };
 184         };
 185
 186         sound2 {
 187                 compatible = "simple-audio-card";
 188                 simple-audio-card,name = "Back";
 189                 simple-audio-card,format = "i2s";
 190                 simple-audio-card,bitclock-master = <&sound2_codec>;
 191                 simple-audio-card,frame-master = <&sound2_codec>;
 192                 simple-audio-card,widgets =
 193                         "Headphone", "Headphone Jack";
 194                 simple-audio-card,routing =
 195                         "Headphone Jack", "HPLEFT",
 196                         "Headphone Jack", "HPRIGHT",
 197                         "LEFTIN", "HPL",
 198                         "RIGHTIN", "HPR";
 199                 simple-audio-card,aux-devs = <&hpa2>;
 200
 201                 sound2_cpu: simple-audio-card,cpu {
 202                         sound-dai = <&ssi1>;
 203                 };
 204
 205                 sound2_codec: simple-audio-card,codec {
 206                         sound-dai = <&codec2>;
 207                         clocks = <&cs2000>;
 208                 };
 209         };
 210
 211         panel {
 212                 power-supply = <&reg_3p3v_display>;
 213                 status = "disabled";
 214
 215                 port {
 216                         panel_in: endpoint {
 217                                 remote-endpoint = <&lvds0_out>;
 218                         };
 219                 };
 220         };
 221
 222         disp0: disp0 {
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 compatible = "fsl,imx-parallel-display";
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&pinctrl_disp0>;
 228                 status = "disabled";
 229
 230                 port@0 {
 231                         reg = <0>;
 232
 233                         disp0_in_0: endpoint {
 234                                 remote-endpoint = <&ipu1_di0_disp0>;
 235                         };
 236                 };
 237
 238                 port@1 {
 239                         reg = <1>;
 240
 241                         disp0_out: endpoint {
 242                                 remote-endpoint = <&tc358767_in>;
 243                         };
 244                 };
 245         };
 246
 247         cs2000_ref: cs2000-ref {
 248                 compatible = "fixed-clock";
 249                 #clock-cells = <0>;
 250                 clock-frequency = <24576000>;
 251         };
 252
 253         cs2000_in_dummy: cs2000-in-dummy {
 254                 compatible = "fixed-clock";
 255                 #clock-cells = <0>;
 256                 clock-frequency = <0>;
 257         };
 258
 259         edp_refclk: edp-refclk {
 260                 compatible = "fixed-clock";
 261                 #clock-cells = <0>;
 262                 clock-frequency = <19200000>;
 263         };
 264 };
 265
 266 &cpu0 {
 267         fsl,soc-operating-points = <
 268                 /* ARM kHz  SOC-PU uV */
 269                 1200000 1300000
 270                 996000  1275000
 271                 852000  1275000
 272                 792000  1200000
 273                 396000  1200000
 274         >;
 275 };
 276
 277 &reg_arm {
 278         vin-supply = <&sw1a_reg>;
 279 };
 280
 281 &reg_pu {
 282         vin-supply = <&sw1c_reg>;
 283 };
 284
 285 &reg_soc {
 286         vin-supply = <&sw1c_reg>;
 287 };
 288
 289 &ldb {
 290         lvds-channel@0 {
 291                 port@4 {
 292                         reg = <4>;
 293
 294                         lvds0_out: endpoint {
 295                                 remote-endpoint = <&panel_in>;
 296                         };
 297                 };
 298         };
 299 };
 300
 301 &uart1 {
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_uart1>;
 304         status = "okay";
 305 };
 306
 307 &uart3 {
 308         pinctrl-names = "default";
 309         pinctrl-0 = <&pinctrl_uart3>;
 310         uart-has-rtscts;
 311         linux,rs485-enabled-at-boot-time;
 312         status = "okay";
 313 };
 314
 315 &uart4 {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&pinctrl_uart4>;
 318         status = "okay";
 319
 320         rave-sp {
 321                 compatible = "zii,rave-sp-rdu2";
 322                 current-speed = <1000000>;
 323
 324                 watchdog {
 325                         compatible = "zii,rave-sp-watchdog";
 326                 };
 327         };
 328 };
 329
 330 &ecspi1 {
 331         pinctrl-names = "default";
 332         pinctrl-0 = <&pinctrl_ecspi1>;
 333         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
 334         status = "okay";
 335
 336         flash@0 {
 337                 compatible = "st,m25p128", "jedec,spi-nor";
 338                 spi-max-frequency = <20000000>;
 339                 reg = <0>;
 340         };
 341 };
 342
 343 &i2c1 {
 344         pinctrl-names = "default";
 345         pinctrl-0 = <&pinctrl_i2c1>;
 346         clock-frequency = <100000>;
 347         status = "okay";
 348
 349         codec2: codec@18 {
 350                 compatible = "ti,tlv320dac3100";
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&pinctrl_codec2>;
 353                 reg = <0x18>;
 354                 #sound-dai-cells = <0>;
 355                 HPVDD-supply = <&reg_3p3v>;
 356                 SPRVDD-supply = <&reg_3p3v>;
 357                 SPLVDD-supply = <&reg_3p3v>;
 358                 AVDD-supply = <&reg_3p3v>;
 359                 IOVDD-supply = <&reg_3p3v>;
 360                 DVDD-supply = <&vgen4_reg>;
 361                 gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 362         };
 363
 364         accel@1c {
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&pinctrl_accel>;
 367                 compatible = "fsl,mma8451";
 368                 reg = <0x1c>;
 369                 interrupt-parent = <&gpio1>;
 370                 interrupt-names = "int1", "int2";
 371                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
 372         };
 373
 374         hpa2: amp@60 {
 375                 compatible = "ti,tpa6130a2";
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&pinctrl_tpa2>;
 378                 reg = <0x60>;
 379                 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 380                 Vdd-supply = <&reg_5p0v_main>;
 381         };
 382
 383         edp-bridge@68 {
 384                 compatible = "toshiba,tc358767";
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&pinctrl_tc358767>;
 387                 reg = <0x68>;
 388                 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 389                 clock-names = "ref";
 390                 clocks = <&edp_refclk>;
 391                 status = "disabled";
 392
 393                 ports {
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396
 397                         port@1 {
 398                                 reg = <1>;
 399
 400                                 tc358767_in: endpoint {
 401                                         remote-endpoint = <&disp0_out>;
 402                                 };
 403                         };
 404                 };
 405         };
 406 };
 407
 408 &i2c2 {
 409         pinctrl-names = "default";
 410         pinctrl-0 = <&pinctrl_i2c2>;
 411         clock-frequency = <100000>;
 412         status = "okay";
 413
 414         pmic@8 {
 415                 compatible = "fsl,pfuze100";
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&pinctrl_pfuze100_irq>;
 418                 reg = <0x08>;
 419                 interrupt-parent = <&gpio7>;
 420                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 421
 422                 regulators {
 423                         sw1a_reg: sw1ab {
 424                                 regulator-min-microvolt = <300000>;
 425                                 regulator-max-microvolt = <1875000>;
 426                                 regulator-boot-on;
 427                                 regulator-always-on;
 428                                 regulator-ramp-delay = <6250>;
 429                         };
 430
 431                         sw1c_reg: sw1c {
 432                                 regulator-min-microvolt = <300000>;
 433                                 regulator-max-microvolt = <1875000>;
 434                                 regulator-boot-on;
 435                                 regulator-always-on;
 436                                 regulator-ramp-delay = <6250>;
 437                         };
 438
 439                         sw2_reg: sw2 {
 440                                 regulator-min-microvolt = <800000>;
 441                                 regulator-max-microvolt = <3000000>;
 442                                 regulator-boot-on;
 443                                 regulator-always-on;
 444                         };
 445
 446                         sw3a_reg: sw3a {
 447                                 regulator-min-microvolt = <400000>;
 448                                 regulator-max-microvolt = <1500000>;
 449                                 regulator-boot-on;
 450                                 regulator-always-on;
 451                         };
 452
 453                         sw3b_reg: sw3b {
 454                                 regulator-min-microvolt = <400000>;
 455                                 regulator-max-microvolt = <1500000>;
 456                                 regulator-boot-on;
 457                                 regulator-always-on;
 458                         };
 459
 460                         sw4_reg: sw4 {
 461                                 regulator-min-microvolt = <800000>;
 462                                 regulator-max-microvolt = <1800000>;
 463                                 regulator-boot-on;
 464                                 regulator-always-on;
 465                         };
 466
 467                         snvs_reg: vsnvs {
 468                                 regulator-min-microvolt = <1000000>;
 469                                 regulator-max-microvolt = <3000000>;
 470                                 regulator-boot-on;
 471                                 regulator-always-on;
 472                         };
 473
 474                         vref_reg: vrefddr {
 475                                 regulator-boot-on;
 476                                 regulator-always-on;
 477                         };
 478
 479                         vgen2_reg: vgen2 {
 480                                 regulator-min-microvolt = <1000000>;
 481                                 regulator-max-microvolt = <1500000>;
 482                                 regulator-always-on;
 483                         };
 484
 485                         vgen4_reg: vgen4 {
 486                                 regulator-min-microvolt = <1200000>;
 487                                 regulator-max-microvolt = <1800000>;
 488                                 regulator-always-on;
 489                         };
 490
 491                         vgen5_reg: vgen5 {
 492                                 regulator-min-microvolt = <1800000>;
 493                                 regulator-max-microvolt = <2500000>;
 494                                 regulator-always-on;
 495                         };
 496
 497                         vgen6_reg: vgen6 {
 498                                 regulator-min-microvolt = <1800000>;
 499                                 regulator-max-microvolt = <2800000>;
 500                                 regulator-always-on;
 501                         };
 502                 };
 503         };
 504
 505         temp-sense@48 {
 506                 compatible = "national,lm75";
 507                 reg = <0x48>;
 508         };
 509
 510         cs2000: clkgen@4e {
 511                 compatible = "cirrus,cs2000-cp";
 512                 reg = <0x4e>;
 513                 #clock-cells = <0>;
 514                 clock-names = "clk_in", "ref_clk";
 515                 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
 516                 assigned-clocks = <&cs2000>;
 517                 assigned-clock-rates = <24000000>;
 518         };
 519
 520         eeprom@54 {
 521                 compatible = "atmel,24c128";
 522                 reg = <0x54>;
 523         };
 524
 525         ds1341: rtc@68 {
 526                 compatible = "dallas,ds1341";
 527                 reg = <0x68>;
 528         };
 529 };
 530
 531 &i2c3 {
 532         pinctrl-names = "default";
 533         pinctrl-0 = <&pinctrl_i2c3>;
 534         clock-frequency = <400000>;
 535         status = "okay";
 536
 537         codec1: codec@18 {
 538                 compatible = "ti,tlv320dac3100";
 539                 pinctrl-names = "default";
 540                 pinctrl-0 = <&pinctrl_codec1>;
 541                 reg = <0x18>;
 542                 #sound-dai-cells = <0>;
 543                 HPVDD-supply = <&reg_3p3v>;
 544                 SPRVDD-supply = <&reg_3p3v>;
 545                 SPLVDD-supply = <&reg_3p3v>;
 546                 AVDD-supply = <&reg_3p3v>;
 547                 IOVDD-supply = <&reg_3p3v>;
 548                 DVDD-supply = <&vgen4_reg>;
 549                 gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 550         };
 551
 552         touchscreen@20 {
 553                 compatible = "syna,rmi4-i2c";
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&pinctrl_ts>;
 556                 reg = <0x20>;
 557                 interrupt-parent = <&gpio1>;
 558                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 559                 vdd-supply = <&reg_5p0v_main>;
 560                 vio-supply = <&reg_3p3v>;
 561
 562                 #address-cells = <1>;
 563                 #size-cells = <0>;
 564
 565                 rmi4-f01@1 {
 566                         reg = <0x1>;
 567                         syna,nosleep-mode = <2>;
 568                 };
 569
 570                 rmi4-f11@11 {
 571                         reg = <0x11>;
 572                         touchscreen-inverted-y;
 573                         touchscreen-swapped-x-y;
 574                         syna,sensor-type = <1>;
 575                 };
 576
 577                 rmi4-f12@12 {
 578                         reg = <0x12>;
 579                         touchscreen-inverted-y;
 580                         touchscreen-swapped-x-y;
 581                         syna,sensor-type = <1>;
 582                 };
 583         };
 584
 585         touchscreen@2a {
 586                 compatible = "eeti,egalax_ts";
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&pinctrl_ts>;
 589                 reg = <0x2a>;
 590                 interrupt-parent = <&gpio1>;
 591                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 592                 wakeup-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
 593                 status = "disabled";
 594         };
 595
 596         hpa1: amp@60 {
 597                 compatible = "ti,tpa6130a2";
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&pinctrl_tpa1>;
 600                 reg = <0x60>;
 601                 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 602                 Vdd-supply = <&reg_5p0v_main>;
 603         };
 604 };
 605
 606 &ipu1_di0_disp0 {
 607         remote-endpoint = <&disp0_in_0>;
 608 };
 609
 610 &pcie {
 611         pinctrl-names = "default";
 612         pinctrl-0 = <&pinctrl_pcie>;
 613         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 614         status = "okay";
 615
 616         host@0 {
 617                 reg = <0 0 0 0 0>;
 618
 619                 #address-cells = <3>;
 620                 #size-cells = <2>;
 621
 622                 i210: i210@0 {
 623                         reg = <0 0 0 0 0>;
 624                 };
 625         };
 626 };
 627
 628 &usdhc2 {
 629         pinctrl-names = "default";
 630         pinctrl-0 = <&pinctrl_usdhc2>;
 631         bus-width = <4>;
 632         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 633         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 634         vmmc-supply = <&reg_3p3v_sd>;
 635         vqmmc-supply = <&reg_3p3v>;
 636         no-1-8-v;
 637         no-sdio;
 638         status = "okay";
 639 };
 640
 641 &usdhc3 {
 642         pinctrl-names = "default";
 643         pinctrl-0 = <&pinctrl_usdhc3>;
 644         bus-width = <4>;
 645         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 646         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 647         vmmc-supply = <&reg_3p3v_sd>;
 648         vqmmc-supply = <&reg_3p3v>;
 649         no-1-8-v;
 650         no-sdio;
 651         status = "okay";
 652 };
 653
 654 &usdhc4 {
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&pinctrl_usdhc4>;
 657         bus-width = <8>;
 658         vmmc-supply = <&reg_3p3v>;
 659         vqmmc-supply = <&reg_3p3v>;
 660         no-1-8-v;
 661         non-removable;
 662         no-sdio;
 663         no-sd;
 664         status = "okay";
 665 };
 666
 667 &sata {
 668         target-supply = <&reg_3p3v_ssd>;
 669         status = "okay";
 670 };
 671
 672 &fec {
 673         pinctrl-names = "default";
 674         pinctrl-0 = <&pinctrl_enet>;
 675         phy-mode = "rmii";
 676         phy-handle = <&phy>;
 677         phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
 678         phy-reset-duration = <100>;
 679         phy-supply = <&reg_3p3v>;
 680         status = "okay";
 681
 682         mdio {
 683                 #address-cells = <1>;
 684                 #size-cells = <0>;
 685                 status = "okay";
 686
 687                 switch: switch@0 {
 688                         compatible = "marvell,mv88e6085";
 689                         pinctrl-0 = <&pinctrl_switch_irq>;
 690                         pinctrl-names = "default";
 691                         reg = <0>;
 692                         dsa,member = <0 0>;
 693                         eeprom-length = <512>;
 694                         interrupt-parent = <&gpio6>;
 695                         interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
 696                         interrupt-controller;
 697                         #interrupt-cells = <2>;
 698
 699                         ports {
 700                                 #address-cells = <1>;
 701                                 #size-cells = <0>;
 702
 703                                 port@0 {
 704                                         reg = <0>;
 705                                         label = "gigabit_proc";
 706                                         phy-handle = <&switchphy0>;
 707                                 };
 708
 709                                 port@1 {
 710                                         reg = <1>;
 711                                         label = "netaux";
 712                                         phy-handle = <&switchphy1>;
 713                                 };
 714
 715                                 port@2 {
 716                                         reg = <2>;
 717                                         label = "cpu";
 718                                         ethernet = <&fec>;
 719
 720                                         fixed-link {
 721                                                 speed = <100>;
 722                                                 full-duplex;
 723                                         };
 724                                 };
 725
 726                                 port@3 {
 727                                         reg = <3>;
 728                                         label = "netright";
 729                                         phy-handle = <&switchphy3>;
 730                                 };
 731
 732                                 port@4 {
 733                                         reg = <4>;
 734                                         label = "netleft";
 735                                         phy-handle = <&switchphy4>;
 736                                 };
 737                         };
 738
 739                         mdio {
 740                                 #address-cells = <1>;
 741                                 #size-cells = <0>;
 742
 743                                 switchphy0: switchphy@0 {
 744                                         reg = <0>;
 745                                         interrupt-parent = <&switch>;
 746                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 747                                 };
 748
 749                                 switchphy1: switchphy@1 {
 750                                         reg = <1>;
 751                                         interrupt-parent = <&switch>;
 752                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 753                                 };
 754
 755                                 switchphy2: switchphy@2 {
 756                                         reg = <2>;
 757                                         interrupt-parent = <&switch>;
 758                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 759                                 };
 760
 761                                 switchphy3: switchphy@3 {
 762                                         reg = <3>;
 763                                         interrupt-parent = <&switch>;
 764                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 765                                 };
 766
 767                                 switchphy4: switchphy@4 {
 768                                         reg = <4>;
 769                                         interrupt-parent = <&switch>;
 770                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 771                                 };
 772                         };
 773                 };
 774         };
 775 };
 776
 777 &usbh1 {
 778         vbus-supply = <&reg_5p0v_main>;
 779         disable-over-current;
 780         status = "okay";
 781 };
 782
 783 &usbotg {
 784         vbus-supply = <&reg_5p0v_user_usb>;
 785         disable-over-current;
 786         dr_mode = "host";
 787         status = "okay";
 788 };
 789
 790 &ssi1 {
 791         status = "okay";
 792 };
 793
 794 &ssi2 {
 795         status = "okay";
 796 };
 797
 798 &audmux {
 799         pinctrl-names = "default";
 800         pinctrl-0 = <&pinctrl_audmux>;
 801         status = "okay";
 802
 803         ssi1 {
 804                 fsl,audmux-port = <0>;
 805                 fsl,port-config = <
 806                         (IMX_AUDMUX_V2_PTCR_SYN |
 807                          IMX_AUDMUX_V2_PTCR_TFSEL(2) |
 808                          IMX_AUDMUX_V2_PTCR_TCSEL(2) |
 809                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 810                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 811                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
 812                 >;
 813         };
 814
 815         aud3 {
 816                 fsl,audmux-port = <2>;
 817                 fsl,port-config = <
 818                         IMX_AUDMUX_V2_PTCR_SYN
 819                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 820                 >;
 821         };
 822
 823         ssi2 {
 824                 fsl,audmux-port = <1>;
 825                 fsl,port-config = <
 826                         (IMX_AUDMUX_V2_PTCR_SYN |
 827                          IMX_AUDMUX_V2_PTCR_TFSEL(4) |
 828                          IMX_AUDMUX_V2_PTCR_TCSEL(4) |
 829                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 830                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 831                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 832                 >;
 833         };
 834
 835         aud5 {
 836                 fsl,audmux-port = <4>;
 837                 fsl,port-config = <
 838                         IMX_AUDMUX_V2_PTCR_SYN
 839                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
 840                 >;
 841         };
 842 };
 843
 844 &wdog1 {
 845         status = "disabled";
 846 };
 847
 848 &iomuxc {
 849         pinctrl_accel: accelgrp {
 850                 fsl,pins = <
 851                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x4001b000
 852                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x4001b000
 853                 >;
 854         };
 855
 856         pinctrl_audmux: audmuxgrp {
 857                 fsl,pins = <
 858                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
 859                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x130b0
 860                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
 861                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 862                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
 863                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 864                 >;
 865         };
 866
 867         pinctrl_codec1: dac1grp {
 868                 fsl,pins = <
 869                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x40000038
 870                 >;
 871         };
 872
 873         pinctrl_codec2: dac2grp {
 874                 fsl,pins = <
 875                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x40000038
 876                 >;
 877         };
 878
 879         pinctrl_disp0: disp0grp {
 880                 fsl,pins = <
 881                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
 882                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
 883                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
 884                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
 885                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
 886                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
 887                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
 888                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
 889                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
 890                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
 891                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
 892                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
 893                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
 894                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
 895                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
 896                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
 897                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
 898                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
 899                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
 900                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
 901                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
 902                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
 903                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
 904                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
 905                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
 906                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
 907                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
 908                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
 909                 >;
 910         };
 911
 912         pinctrl_ecspi1: ecspi1grp {
 913                 fsl,pins = <
 914                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 915                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 916                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 917                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b1
 918                 >;
 919         };
 920
 921         pinctrl_enet: enetgrp {
 922                 fsl,pins = <
 923                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x000b1
 924                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b1
 925                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x100f5
 926                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x100f5
 927                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x100c0
 928                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x100c0
 929                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x100f5
 930                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x100f5
 931                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x40010040
 932                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x100b0
 933                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 934                 >;
 935         };
 936
 937         pinctrl_i2c1: i2c1grp {
 938                 fsl,pins = <
 939                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 940                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 941                 >;
 942         };
 943
 944         pinctrl_i2c2: i2c2grp {
 945                 fsl,pins = <
 946                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 947                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 948                 >;
 949         };
 950
 951         pinctrl_i2c3: i2c3grp {
 952                 fsl,pins = <
 953                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 954                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 955                 >;
 956         };
 957
 958         pinctrl_mdio1: bitbangmdiogrp {
 959                 fsl,pins = <
 960                         /* Bitbang MDIO for DEB Switch */
 961                         MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x4001b030
 962                         MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40018830
 963                 >;
 964         };
 965
 966         pinctrl_pcie: pciegrp {
 967                 fsl,pins = <
 968                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x10038
 969                 >;
 970         };
 971
 972         pinctrl_pfuze100_irq: pfuze100grp {
 973                 fsl,pins = <
 974                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x40010000
 975                 >;
 976         };
 977
 978         pinctrl_reg_3p3v_sd: mmcsupply1grp {
 979                 fsl,pins = <
 980                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x858
 981                 >;
 982         };
 983
 984         pinctrl_reg_user_usb: usbotggrp {
 985                 fsl,pins = <
 986                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x40000038
 987                 >;
 988         };
 989
 990         pinctrl_rmii_phy_irq: phygrp {
 991                 fsl,pins = <
 992                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x40010000
 993                 >;
 994         };
 995
 996         pinctrl_switch_irq: switchgrp {
 997                 fsl,pins = <
 998                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x4001b000
 999                 >;
1000         };
1001
1002         pinctrl_tc358767: tc358767grp {
1003                 fsl,pins = <
1004                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x10
1005                 >;
1006         };
1007
1008         pinctrl_tpa1: tpa6130-1grp {
1009                 fsl,pins = <
1010                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x40000038
1011                 >;
1012         };
1013
1014         pinctrl_tpa2: tpa6130-2grp {
1015                 fsl,pins = <
1016                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x40000038
1017                 >;
1018         };
1019
1020         pinctrl_ts: tsgrp {
1021                 fsl,pins = <
1022                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0
1023                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
1024                 >;
1025         };
1026
1027         pinctrl_uart1: uart1grp {
1028                 fsl,pins = <
1029                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
1030                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
1031                 >;
1032         };
1033
1034         pinctrl_uart3: uart3grp {
1035                 fsl,pins = <
1036                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
1037                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
1038                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
1039                 >;
1040         };
1041
1042         pinctrl_uart4: uart4grp {
1043                 fsl,pins = <
1044                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
1045                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
1046                 >;
1047         };
1048
1049         pinctrl_usdhc2: usdhc2grp {
1050                 fsl,pins = <
1051                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x10059
1052                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
1053                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
1054                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
1055                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
1056                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
1057                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x40010040
1058                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x40010040
1059                 >;
1060         };
1061
1062         pinctrl_usdhc3: usdhc3grp {
1063                 fsl,pins = <
1064                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x10059
1065                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10069
1066                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
1067                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
1068                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
1069                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
1070                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x40010040
1071                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x40010040
1072
1073                 >;
1074         };
1075
1076         pinctrl_usdhc4: usdhc4grp {
1077                 fsl,pins = <
1078                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
1079                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
1080                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
1081                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
1082                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
1083                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
1084                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
1085                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
1086                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
1087                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
1088                         MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x1b0b1
1089                 >;
1090         };
1091 };