arch/arm/boot/dts/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/input/input.h>
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/pwm/pwm.h>
  46 #include <dt-bindings/sound/fsl-imx-audmux.h>
  47
  48 / {
  49         aliases {
  50                 can0 = &can2;
  51                 can1 = &can1;
  52                 ethernet0 = &fec;
  53                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  54                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  55                 pwm0 = &pwm1;
  56                 pwm1 = &pwm2;
  57                 reg_can_xcvr = &reg_can_xcvr;
  58                 stk5led = &user_led;
  59                 usbotg = &usbotg;
  60                 sdhc0 = &usdhc1;
  61                 sdhc1 = &usdhc2;
  62         };
  63
  64         memory {
  65                 reg = <0 0>; /* will be filled by U-Boot */
  66         };
  67
  68         clocks {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 mclk: clock@0 {
  73                         compatible = "fixed-clock";
  74                         reg = <0>;
  75                         #clock-cells = <0>;
  76                         clock-frequency = <26000000>;
  77                 };
  78         };
  79
  80         gpio-keys {
  81                 compatible = "gpio-keys";
  82
  83                 power {
  84                         label = "Power Button";
  85                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  86                         linux,code = <KEY_POWER>;
  87                         wakeup-source;
  88                 };
  89         };
  90
  91         leds {
  92                 compatible = "gpio-leds";
  93
  94                 user_led: user {
  95                         label = "Heartbeat";
  96                         pinctrl-names = "default";
  97                         pinctrl-0 = <&pinctrl_user_led>;
  98                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  99                         linux,default-trigger = "heartbeat";
 100                 };
 101         };
 102
 103         reg_3v3_etn: regulator-3v3-etn {
 104                 compatible = "regulator-fixed";
 105                 regulator-name = "3V3_ETN";
 106                 regulator-min-microvolt = <3300000>;
 107                 regulator-max-microvolt = <3300000>;
 108                 pinctrl-names = "default";
 109                 pinctrl-0 = <&pinctrl_etnphy_power>;
 110                 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 111                 enable-active-high;
 112         };
 113
 114         reg_2v5: regulator-2v5 {
 115                 compatible = "regulator-fixed";
 116                 regulator-name = "2V5";
 117                 regulator-min-microvolt = <2500000>;
 118                 regulator-max-microvolt = <2500000>;
 119                 regulator-always-on;
 120         };
 121
 122         reg_3v3: regulator-3v3 {
 123                 compatible = "regulator-fixed";
 124                 regulator-name = "3V3";
 125                 regulator-min-microvolt = <3300000>;
 126                 regulator-max-microvolt = <3300000>;
 127                 regulator-always-on;
 128         };
 129
 130         reg_can_xcvr: regulator-can-xcvr {
 131                 compatible = "regulator-fixed";
 132                 regulator-name = "CAN XCVR";
 133                 regulator-min-microvolt = <3300000>;
 134                 regulator-max-microvolt = <3300000>;
 135                 pinctrl-names = "default";
 136                 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 137                 gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
 138         };
 139
 140         reg_lcd0_pwr: regulator-lcd0-pwr {
 141                 compatible = "regulator-fixed";
 142                 regulator-name = "LCD0 POWER";
 143                 regulator-min-microvolt = <3300000>;
 144                 regulator-max-microvolt = <3300000>;
 145                 pinctrl-names = "default";
 146                 pinctrl-0 = <&pinctrl_lcd0_pwr>;
 147                 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 148                 enable-active-high;
 149                 status = "disabled";
 150         };
 151
 152         reg_lcd1_pwr: regulator-lcd1-pwr {
 153                 compatible = "regulator-fixed";
 154                 regulator-name = "LCD1 POWER";
 155                 regulator-min-microvolt = <3300000>;
 156                 regulator-max-microvolt = <3300000>;
 157                 pinctrl-names = "default";
 158                 pinctrl-0 = <&pinctrl_lcd1_pwr>;
 159                 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
 160                 enable-active-high;
 161                 status = "disabled";
 162         };
 163
 164         reg_usbh1_vbus: regulator-usbh1-vbus {
 165                 compatible = "regulator-fixed";
 166                 regulator-name = "usbh1_vbus";
 167                 regulator-min-microvolt = <5000000>;
 168                 regulator-max-microvolt = <5000000>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&pinctrl_usbh1_vbus>;
 171                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 172                 enable-active-high;
 173         };
 174
 175         reg_usbotg_vbus: regulator-usbotg-vbus {
 176                 compatible = "regulator-fixed";
 177                 regulator-name = "usbotg_vbus";
 178                 regulator-min-microvolt = <5000000>;
 179                 regulator-max-microvolt = <5000000>;
 180                 pinctrl-names = "default";
 181                 pinctrl-0 = <&pinctrl_usbotg_vbus>;
 182                 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 183                 enable-active-high;
 184         };
 185
 186         sound {
 187                 compatible = "karo,imx6qdl-tx6-sgtl5000",
 188                              "simple-audio-card";
 189                 simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio";
 190                 pinctrl-names = "default";
 191                 pinctrl-0 = <&pinctrl_audmux>;
 192                 simple-audio-card,format = "i2s";
 193                 simple-audio-card,bitclock-master = <&codec_dai>;
 194                 simple-audio-card,frame-master = <&codec_dai>;
 195                 simple-audio-card,widgets =
 196                         "Microphone", "Mic Jack",
 197                         "Line", "Line In",
 198                         "Line", "Line Out",
 199                         "Headphone", "Headphone Jack";
 200                 simple-audio-card,routing =
 201                         "MIC_IN", "Mic Jack",
 202                         "Mic Jack", "Mic Bias",
 203                         "Headphone Jack", "HP_OUT";
 204
 205                 cpu_dai: simple-audio-card,cpu {
 206                         sound-dai = <&ssi1>;
 207                 };
 208
 209                 codec_dai: simple-audio-card,codec {
 210                         sound-dai = <&sgtl5000>;
 211                 };
 212         };
 213 };
 214
 215 &audmux {
 216         status = "okay";
 217
 218         ssi1 {
 219                 fsl,audmux-port = <0>;
 220                 fsl,port-config = <
 221                         (IMX_AUDMUX_V2_PTCR_SYN |
 222                         IMX_AUDMUX_V2_PTCR_TFSEL(4) |
 223                         IMX_AUDMUX_V2_PTCR_TCSEL(4) |
 224                         IMX_AUDMUX_V2_PTCR_TFSDIR |
 225                         IMX_AUDMUX_V2_PTCR_TCLKDIR)
 226                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 227                 >;
 228         };
 229
 230         pins5 {
 231                 fsl,audmux-port = <4>;
 232                 fsl,port-config = <
 233                         IMX_AUDMUX_V2_PTCR_SYN
 234                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 235                 >;
 236         };
 237 };
 238
 239 &can1 {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_flexcan1>;
 242         xceiver-supply = <&reg_can_xcvr>;
 243         status = "okay";
 244 };
 245
 246 &can2 {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_flexcan2>;
 249         xceiver-supply = <&reg_can_xcvr>;
 250         status = "okay";
 251 };
 252
 253 &ecspi1 {
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_ecspi1>;
 256         cs-gpios = <
 257                 &gpio2 30 GPIO_ACTIVE_HIGH
 258                 &gpio3 19 GPIO_ACTIVE_HIGH
 259         >;
 260         status = "disabled";
 261
 262         spidev0: spi@0 {
 263                 compatible = "spidev";
 264                 reg = <0>;
 265                 spi-max-frequency = <54000000>;
 266         };
 267
 268         spidev1: spi@1 {
 269                 compatible = "spidev";
 270                 reg = <1>;
 271                 spi-max-frequency = <54000000>;
 272         };
 273 };
 274
 275 &fec {
 276         pinctrl-names = "default";
 277         pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;
 278         clocks = <&clks IMX6QDL_CLK_ENET>,
 279                  <&clks IMX6QDL_CLK_ENET>,
 280                  <&clks IMX6QDL_CLK_ENET_REF>,
 281                  <&clks IMX6QDL_CLK_ENET_REF>;
 282         clock-names = "ipg", "ahb", "ptp", "enet_out";
 283         phy-mode = "rmii";
 284         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
 285         phy-reset-post-delay = <10>;
 286         phy-handle = <&etnphy>;
 287         phy-supply = <&reg_3v3_etn>;
 288         status = "okay";
 289
 290         mdio {
 291                 #address-cells = <1>;
 292                 #size-cells = <0>;
 293
 294                 etnphy: ethernet-phy@0 {
 295                         compatible = "ethernet-phy-ieee802.3-c22";
 296                         reg = <0>;
 297                         pinctrl-names = "default";
 298                         pinctrl-0 = <&pinctrl_etnphy_int>;
 299                         interrupt-parent = <&gpio7>;
 300                         interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
 301                 };
 302         };
 303 };
 304
 305 &gpmi {
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_gpmi_nand>;
 308         nand-on-flash-bbt;
 309         fsl,no-blockmark-swap;
 310         status = "okay";
 311 };
 312
 313 &i2c1 {
 314         pinctrl-names = "default", "gpio";
 315         pinctrl-0 = <&pinctrl_i2c1>;
 316         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 317         scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
 318         sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 319         clock-frequency = <400000>;
 320         status = "okay";
 321
 322         ds1339: rtc@68 {
 323                 compatible = "dallas,ds1339";
 324                 reg = <0x68>;
 325                 trickle-resistor-ohms = <250>;
 326                 trickle-diode-disable;
 327         };
 328 };
 329
 330 &i2c3 {
 331         pinctrl-names = "default", "gpio";
 332         pinctrl-0 = <&pinctrl_i2c3>;
 333         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 334         scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 335         sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
 336         clock-frequency = <400000>;
 337         status = "okay";
 338
 339         sgtl5000: sgtl5000@a {
 340                 compatible = "fsl,sgtl5000";
 341                 #sound-dai-cells = <0>;
 342                 reg = <0x0a>;
 343                 VDDA-supply = <&reg_2v5>;
 344                 VDDIO-supply = <&reg_3v3>;
 345                 clocks = <&mclk>;
 346         };
 347
 348         polytouch: edt-ft5x06@38 {
 349                 compatible = "edt,edt-ft5x06";
 350                 reg = <0x38>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 353                 interrupt-parent = <&gpio6>;
 354                 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
 355                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 356                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 357                 wakeup-source;
 358         };
 359
 360         touchscreen: tsc2007@48 {
 361                 compatible = "ti,tsc2007";
 362                 reg = <0x48>;
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&pinctrl_tsc2007>;
 365                 interrupt-parent = <&gpio3>;
 366                 interrupts = <26 0>;
 367                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 368                 ti,x-plate-ohms = <660>;
 369                 wakeup-source;
 370         };
 371 };
 372
 373 &iomuxc {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_hog>;
 376
 377         pinctrl_hog: hoggrp {
 378                 fsl,pins = <
 379                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* PWR BTN */
 380                 >;
 381         };
 382
 383         pinctrl_audmux: audmuxgrp {
 384                 fsl,pins = <
 385                         MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
 386                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
 387                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
 388                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
 389                 >;
 390         };
 391
 392         pinctrl_disp0_1: disp0grp-1 {
 393                 fsl,pins = <
 394                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 395                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 396                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 397                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 398                         /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 399                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 400                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 401                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 402                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 403                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 404                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 405                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 406                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 407                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 408                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 409                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 410                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 411                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 412                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 413                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 414                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 415                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 416                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 417                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 418                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 419                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 420                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 421                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 422                 >;
 423         };
 424
 425         pinctrl_disp0_2: disp0grp-2 {
 426                 fsl,pins = <
 427                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 428                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 429                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 430                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 431                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 432                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 433                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 434                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 435                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 436                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 437                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 438                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 439                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 440                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 441                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 442                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 443                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 444                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 445                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 446                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 447                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 448                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 449                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 450                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 451                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 452                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 453                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 454                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 455                 >;
 456         };
 457
 458         pinctrl_ecspi1: ecspi1grp {
 459                 fsl,pins = <
 460                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
 461                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
 462                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
 463                         MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
 464                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
 465                         MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
 466                 >;
 467         };
 468
 469         pinctrl_edt_ft5x06: edt-ft5x06grp {
 470                 fsl,pins = <
 471                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
 472                         MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
 473                         MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
 474                 >;
 475         };
 476
 477         pinctrl_enet: enetgrp {
 478                 fsl,pins = <
 479                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 480                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 481                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 482                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 483                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 484                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 485                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 486                 >;
 487         };
 488
 489         pinctrl_enet_mdio: enet-mdiogrp {
 490                 fsl,pins = <
 491                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 492                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 493                 >;
 494         };
 495
 496         pinctrl_etnphy_int: etnphy-intgrp {
 497                 fsl,pins = <
 498                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
 499                 >;
 500         };
 501
 502         pinctrl_etnphy_power: etnphy-pwrgrp {
 503                 fsl,pins = <
 504                         MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
 505                 >;
 506         };
 507
 508         pinctrl_etnphy_rst: etnphy-rstgrp {
 509                 fsl,pins = <
 510                         MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
 511                 >;
 512         };
 513
 514         pinctrl_flexcan1: flexcan1grp {
 515                 fsl,pins = <
 516                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 517                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 518                 >;
 519         };
 520
 521         pinctrl_flexcan2: flexcan2grp {
 522                 fsl,pins = <
 523                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 524                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 525                 >;
 526         };
 527
 528         pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 529                 fsl,pins = <
 530                         MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21       0x1b0b0 /* Flexcan XCVR enable */
 531                 >;
 532         };
 533
 534         pinctrl_gpmi_nand: gpminandgrp {
 535                 fsl,pins = <
 536                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
 537                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
 538                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
 539                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
 540                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
 541                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
 542                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
 543                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
 544                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
 545                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
 546                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
 547                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
 548                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
 549                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
 550                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
 551                 >;
 552         };
 553
 554         pinctrl_i2c1: i2c1grp {
 555                 fsl,pins = <
 556                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 557                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 558                 >;
 559         };
 560
 561         pinctrl_i2c1_gpio: i2c1-gpiogrp {
 562                 fsl,pins = <
 563                         MX6QDL_PAD_EIM_D21__GPIO3_IO21          0x4001b8b1
 564                         MX6QDL_PAD_EIM_D28__GPIO3_IO28          0x4001b8b1
 565                 >;
 566         };
 567
 568         pinctrl_i2c3: i2c3grp {
 569                 fsl,pins = <
 570                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 571                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 572                 >;
 573         };
 574
 575         pinctrl_i2c3_gpio: i2c3-gpiogrp {
 576                 fsl,pins = <
 577                         MX6QDL_PAD_GPIO_3__GPIO1_IO03           0x4001b8b1
 578                         MX6QDL_PAD_GPIO_6__GPIO1_IO06           0x4001b8b1
 579                 >;
 580         };
 581
 582         pinctrl_kpp: kppgrp {
 583                 fsl,pins = <
 584                         MX6QDL_PAD_GPIO_9__KEY_COL6             0x1b0b1
 585                         MX6QDL_PAD_GPIO_4__KEY_COL7             0x1b0b1
 586                         MX6QDL_PAD_KEY_COL2__KEY_COL2           0x1b0b1
 587                         MX6QDL_PAD_KEY_COL3__KEY_COL3           0x1b0b1
 588                         MX6QDL_PAD_GPIO_2__KEY_ROW6             0x1b0b1
 589                         MX6QDL_PAD_GPIO_5__KEY_ROW7             0x1b0b1
 590                         MX6QDL_PAD_KEY_ROW2__KEY_ROW2           0x1b0b1
 591                         MX6QDL_PAD_KEY_ROW3__KEY_ROW3           0x1b0b1
 592                 >;
 593         };
 594
 595         pinctrl_lcd0_pwr: lcd0-pwrgrp {
 596                 fsl,pins = <
 597                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1 /* LCD Reset */
 598                 >;
 599         };
 600
 601         pinctrl_lcd1_pwr: lcd-pwrgrp {
 602                 fsl,pins = <
 603                         MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b1 /* LCD Power Enable */
 604                 >;
 605         };
 606
 607         pinctrl_pwm1: pwm1grp {
 608                 fsl,pins = <
 609                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 610                 >;
 611         };
 612
 613         pinctrl_pwm2: pwm2grp {
 614                 fsl,pins = <
 615                         MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
 616                 >;
 617         };
 618
 619         pinctrl_tsc2007: tsc2007grp {
 620                 fsl,pins = <
 621                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0 /* Interrupt */
 622                 >;
 623         };
 624
 625         pinctrl_uart1: uart1grp {
 626                 fsl,pins = <
 627                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 628                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 629                 >;
 630         };
 631
 632         pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 633                 fsl,pins = <
 634                         MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
 635                         MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
 636                 >;
 637         };
 638
 639         pinctrl_uart2: uart2grp {
 640                 fsl,pins = <
 641                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 642                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 643                 >;
 644         };
 645
 646         pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 647                 fsl,pins = <
 648                         MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 649                         MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 650                 >;
 651         };
 652
 653         pinctrl_uart3: uart3grp {
 654                 fsl,pins = <
 655                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 656                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 657                 >;
 658         };
 659
 660         pinctrl_uart3_rtscts: uart3_rtsctsgrp {
 661                 fsl,pins = <
 662                         MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
 663                         MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
 664                 >;
 665         };
 666
 667         pinctrl_usbh1_vbus: usbh1-vbusgrp {
 668                 fsl,pins = <
 669                         MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
 670                 >;
 671         };
 672
 673         pinctrl_usbotg: usbotggrp {
 674                 fsl,pins = <
 675                         MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
 676                 >;
 677         };
 678
 679         pinctrl_usbotg_vbus: usbotg-vbusgrp {
 680                 fsl,pins = <
 681                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
 682                 >;
 683         };
 684
 685         pinctrl_usdhc1: usdhc1grp {
 686                 fsl,pins = <
 687                         MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
 688                         MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
 689                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
 690                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
 691                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
 692                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
 693                         MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
 694                 >;
 695         };
 696
 697         pinctrl_usdhc2: usdhc2grp {
 698                 fsl,pins = <
 699                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
 700                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
 701                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
 702                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
 703                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
 704                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
 705                         MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
 706                 >;
 707         };
 708
 709         pinctrl_user_led: user-ledgrp {
 710                 fsl,pins = <
 711                         MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1 /* LED */
 712                 >;
 713         };
 714 };
 715
 716 &kpp {
 717         pinctrl-names = "default";
 718         pinctrl-0 = <&pinctrl_kpp>;
 719         /* sample keymap */
 720         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 721         linux,keymap = <
 722                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
 723                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
 724                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
 725                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
 726                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
 727                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
 728                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
 729                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
 730                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
 731                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
 732                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
 733         >;
 734         status = "okay";
 735 };
 736
 737 &pwm1 {
 738         pinctrl-names = "default";
 739         pinctrl-0 = <&pinctrl_pwm1>;
 740         #pwm-cells = <3>;
 741         status = "disabled";
 742 };
 743
 744 &pwm2 {
 745         pinctrl-names = "default";
 746         pinctrl-0 = <&pinctrl_pwm2>;
 747         #pwm-cells = <3>;
 748         status = "okay";
 749 };
 750
 751 &ssi1 {
 752         status = "okay";
 753 };
 754
 755 &uart1 {
 756         pinctrl-names = "default";
 757         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 758         uart-has-rtscts;
 759         status = "okay";
 760 };
 761
 762 &uart2 {
 763         pinctrl-names = "default";
 764         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 765         uart-has-rtscts;
 766         status = "okay";
 767 };
 768
 769 &uart3 {
 770         pinctrl-names = "default";
 771         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
 772         uart-has-rtscts;
 773         status = "okay";
 774 };
 775
 776 &usbh1 {
 777         vbus-supply = <&reg_usbh1_vbus>;
 778         dr_mode = "host";
 779         disable-over-current;
 780         status = "okay";
 781 };
 782
 783 &usbotg {
 784         vbus-supply = <&reg_usbotg_vbus>;
 785         pinctrl-names = "default";
 786         pinctrl-0 = <&pinctrl_usbotg>;
 787         dr_mode = "peripheral";
 788         disable-over-current;
 789         status = "okay";
 790 };
 791
 792 &usdhc1 {
 793         pinctrl-names = "default";
 794         pinctrl-0 = <&pinctrl_usdhc1>;
 795         bus-width = <4>;
 796         no-1-8-v;
 797         cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
 798         fsl,wp-controller;
 799         status = "okay";
 800 };
 801
 802 &usdhc2 {
 803         pinctrl-names = "default";
 804         pinctrl-0 = <&pinctrl_usdhc2>;
 805         bus-width = <4>;
 806         no-1-8-v;
 807         cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
 808         fsl,wp-controller;
 809         status = "okay";
 810 };