arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/input/input.h>
  15
  16 / {
  17         chosen {
  18                 stdout-path = &uart1;
  19         };
  20
  21         memory {
  22                 reg = <0x10000000 0x40000000>;
  23         };
  24
  25         regulators {
  26                 compatible = "simple-bus";
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 reg_usb_otg_vbus: regulator@0 {
  31                         compatible = "regulator-fixed";
  32                         reg = <0>;
  33                         regulator-name = "usb_otg_vbus";
  34                         regulator-min-microvolt = <5000000>;
  35                         regulator-max-microvolt = <5000000>;
  36                         gpio = <&gpio3 22 0>;
  37                         enable-active-high;
  38                         vin-supply = <&swbst_reg>;
  39                 };
  40
  41                 reg_usb_h1_vbus: regulator@1 {
  42                         compatible = "regulator-fixed";
  43                         reg = <1>;
  44                         regulator-name = "usb_h1_vbus";
  45                         regulator-min-microvolt = <5000000>;
  46                         regulator-max-microvolt = <5000000>;
  47                         gpio = <&gpio1 29 0>;
  48                         enable-active-high;
  49                         vin-supply = <&swbst_reg>;
  50                 };
  51
  52                 reg_audio: regulator@2 {
  53                         compatible = "regulator-fixed";
  54                         reg = <2>;
  55                         regulator-name = "wm8962-supply";
  56                         gpio = <&gpio4 10 0>;
  57                         enable-active-high;
  58                 };
  59
  60                 reg_pcie: regulator@3 {
  61                         compatible = "regulator-fixed";
  62                         reg = <3>;
  63                         pinctrl-names = "default";
  64                         pinctrl-0 = <&pinctrl_pcie_reg>;
  65                         regulator-name = "MPCIE_3V3";
  66                         regulator-min-microvolt = <3300000>;
  67                         regulator-max-microvolt = <3300000>;
  68                         gpio = <&gpio3 19 0>;
  69                         regulator-always-on;
  70                         enable-active-high;
  71                 };
  72         };
  73
  74         gpio-keys {
  75                 compatible = "gpio-keys";
  76                 pinctrl-names = "default";
  77                 pinctrl-0 = <&pinctrl_gpio_keys>;
  78
  79                 power {
  80                         label = "Power Button";
  81                         gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
  82                         wakeup-source;
  83                         linux,code = <KEY_POWER>;
  84                 };
  85
  86                 volume-up {
  87                         label = "Volume Up";
  88                         gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  89                         wakeup-source;
  90                         linux,code = <KEY_VOLUMEUP>;
  91                 };
  92
  93                 volume-down {
  94                         label = "Volume Down";
  95                         gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  96                         wakeup-source;
  97                         linux,code = <KEY_VOLUMEDOWN>;
  98                 };
  99         };
 100
 101         sound {
 102                 compatible = "fsl,imx6q-sabresd-wm8962",
 103                            "fsl,imx-audio-wm8962";
 104                 model = "wm8962-audio";
 105                 ssi-controller = <&ssi2>;
 106                 audio-codec = <&codec>;
 107                 audio-routing =
 108                         "Headphone Jack", "HPOUTL",
 109                         "Headphone Jack", "HPOUTR",
 110                         "Ext Spk", "SPKOUTL",
 111                         "Ext Spk", "SPKOUTR",
 112                         "AMIC", "MICBIAS",
 113                         "IN3R", "AMIC";
 114                 mux-int-port = <2>;
 115                 mux-ext-port = <3>;
 116         };
 117
 118         backlight_lvds: backlight-lvds {
 119                 compatible = "pwm-backlight";
 120                 pwms = <&pwm1 0 5000000>;
 121                 brightness-levels = <0 4 8 16 32 64 128 255>;
 122                 default-brightness-level = <7>;
 123                 status = "okay";
 124         };
 125
 126         leds {
 127                 compatible = "gpio-leds";
 128                 pinctrl-names = "default";
 129                 pinctrl-0 = <&pinctrl_gpio_leds>;
 130
 131                 red {
 132                         gpios = <&gpio1 2 0>;
 133                         default-state = "on";
 134                 };
 135         };
 136
 137         panel {
 138                 compatible = "hannstar,hsd100pxn1";
 139                 backlight = <&backlight_lvds>;
 140
 141                 port {
 142                         panel_in: endpoint {
 143                                 remote-endpoint = <&lvds0_out>;
 144                         };
 145                 };
 146         };
 147 };
 148
 149 &audmux {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_audmux>;
 152         status = "okay";
 153 };
 154
 155 &clks {
 156         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 157                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 158         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 159                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 160 };
 161
 162 &ecspi1 {
 163         cs-gpios = <&gpio4 9 0>;
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_ecspi1>;
 166         status = "okay";
 167
 168         flash: m25p80@0 {
 169                 #address-cells = <1>;
 170                 #size-cells = <1>;
 171                 compatible = "st,m25p32", "jedec,spi-nor";
 172                 spi-max-frequency = <20000000>;
 173                 reg = <0>;
 174         };
 175 };
 176
 177 &fec {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_enet>;
 180         phy-mode = "rgmii";
 181         phy-reset-gpios = <&gpio1 25 0>;
 182         status = "okay";
 183 };
 184
 185 &hdmi {
 186         ddc-i2c-bus = <&i2c2>;
 187         status = "okay";
 188 };
 189
 190 &i2c1 {
 191         clock-frequency = <100000>;
 192         pinctrl-names = "default";
 193         pinctrl-0 = <&pinctrl_i2c1>;
 194         status = "okay";
 195
 196         codec: wm8962@1a {
 197                 compatible = "wlf,wm8962";
 198                 reg = <0x1a>;
 199                 clocks = <&clks IMX6QDL_CLK_CKO>;
 200                 DCVDD-supply = <&reg_audio>;
 201                 DBVDD-supply = <&reg_audio>;
 202                 AVDD-supply = <&reg_audio>;
 203                 CPVDD-supply = <&reg_audio>;
 204                 MICVDD-supply = <&reg_audio>;
 205                 PLLVDD-supply = <&reg_audio>;
 206                 SPKVDD1-supply = <&reg_audio>;
 207                 SPKVDD2-supply = <&reg_audio>;
 208                 gpio-cfg = <
 209                         0x0000 /* 0:Default */
 210                         0x0000 /* 1:Default */
 211                         0x0013 /* 2:FN_DMICCLK */
 212                         0x0000 /* 3:Default */
 213                         0x8014 /* 4:FN_DMICCDAT */
 214                         0x0000 /* 5:Default */
 215                 >;
 216        };
 217 };
 218
 219 &i2c2 {
 220         clock-frequency = <100000>;
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&pinctrl_i2c2>;
 223         status = "okay";
 224
 225         pmic: pfuze100@08 {
 226                 compatible = "fsl,pfuze100";
 227                 reg = <0x08>;
 228
 229                 regulators {
 230                         sw1a_reg: sw1ab {
 231                                 regulator-min-microvolt = <300000>;
 232                                 regulator-max-microvolt = <1875000>;
 233                                 regulator-boot-on;
 234                                 regulator-always-on;
 235                                 regulator-ramp-delay = <6250>;
 236                         };
 237
 238                         sw1c_reg: sw1c {
 239                                 regulator-min-microvolt = <300000>;
 240                                 regulator-max-microvolt = <1875000>;
 241                                 regulator-boot-on;
 242                                 regulator-always-on;
 243                                 regulator-ramp-delay = <6250>;
 244                         };
 245
 246                         sw2_reg: sw2 {
 247                                 regulator-min-microvolt = <800000>;
 248                                 regulator-max-microvolt = <3300000>;
 249                                 regulator-boot-on;
 250                                 regulator-always-on;
 251                                 regulator-ramp-delay = <6250>;
 252                         };
 253
 254                         sw3a_reg: sw3a {
 255                                 regulator-min-microvolt = <400000>;
 256                                 regulator-max-microvolt = <1975000>;
 257                                 regulator-boot-on;
 258                                 regulator-always-on;
 259                         };
 260
 261                         sw3b_reg: sw3b {
 262                                 regulator-min-microvolt = <400000>;
 263                                 regulator-max-microvolt = <1975000>;
 264                                 regulator-boot-on;
 265                                 regulator-always-on;
 266                         };
 267
 268                         sw4_reg: sw4 {
 269                                 regulator-min-microvolt = <800000>;
 270                                 regulator-max-microvolt = <3300000>;
 271                         };
 272
 273                         swbst_reg: swbst {
 274                                 regulator-min-microvolt = <5000000>;
 275                                 regulator-max-microvolt = <5150000>;
 276                         };
 277
 278                         snvs_reg: vsnvs {
 279                                 regulator-min-microvolt = <1000000>;
 280                                 regulator-max-microvolt = <3000000>;
 281                                 regulator-boot-on;
 282                                 regulator-always-on;
 283                         };
 284
 285                         vref_reg: vrefddr {
 286                                 regulator-boot-on;
 287                                 regulator-always-on;
 288                         };
 289
 290                         vgen1_reg: vgen1 {
 291                                 regulator-min-microvolt = <800000>;
 292                                 regulator-max-microvolt = <1550000>;
 293                         };
 294
 295                         vgen2_reg: vgen2 {
 296                                 regulator-min-microvolt = <800000>;
 297                                 regulator-max-microvolt = <1550000>;
 298                         };
 299
 300                         vgen3_reg: vgen3 {
 301                                 regulator-min-microvolt = <1800000>;
 302                                 regulator-max-microvolt = <3300000>;
 303                         };
 304
 305                         vgen4_reg: vgen4 {
 306                                 regulator-min-microvolt = <1800000>;
 307                                 regulator-max-microvolt = <3300000>;
 308                                 regulator-always-on;
 309                         };
 310
 311                         vgen5_reg: vgen5 {
 312                                 regulator-min-microvolt = <1800000>;
 313                                 regulator-max-microvolt = <3300000>;
 314                                 regulator-always-on;
 315                         };
 316
 317                         vgen6_reg: vgen6 {
 318                                 regulator-min-microvolt = <1800000>;
 319                                 regulator-max-microvolt = <3300000>;
 320                                 regulator-always-on;
 321                         };
 322                 };
 323         };
 324 };
 325
 326 &i2c3 {
 327         clock-frequency = <100000>;
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_i2c3>;
 330         status = "okay";
 331
 332         egalax_ts@04 {
 333                 compatible = "eeti,egalax_ts";
 334                 reg = <0x04>;
 335                 interrupt-parent = <&gpio6>;
 336                 interrupts = <7 2>;
 337                 wakeup-gpios = <&gpio6 7 0>;
 338         };
 339 };
 340
 341 &iomuxc {
 342         pinctrl-names = "default";
 343         pinctrl-0 = <&pinctrl_hog>;
 344
 345         imx6qdl-sabresd {
 346                 pinctrl_hog: hoggrp {
 347                         fsl,pins = <
 348                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
 349                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
 350                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
 351                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
 352                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 353                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
 354                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
 355                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
 356                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
 357                         >;
 358                 };
 359
 360                 pinctrl_audmux: audmuxgrp {
 361                         fsl,pins = <
 362                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 363                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 364                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 365                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 366                         >;
 367                 };
 368
 369                 pinctrl_ecspi1: ecspi1grp {
 370                         fsl,pins = <
 371                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 372                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 373                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 374                                 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x1b0b0
 375                         >;
 376                 };
 377
 378                 pinctrl_enet: enetgrp {
 379                         fsl,pins = <
 380                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 381                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 382                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 383                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 384                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 385                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 386                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 387                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 388                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 389                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 390                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 391                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 392                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 393                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 394                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 395                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 396                         >;
 397                 };
 398
 399                 pinctrl_gpio_keys: gpio_keysgrp {
 400                         fsl,pins = <
 401                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
 402                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
 403                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
 404                         >;
 405                 };
 406
 407                 pinctrl_i2c1: i2c1grp {
 408                         fsl,pins = <
 409                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 410                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 411                         >;
 412                 };
 413
 414                 pinctrl_i2c2: i2c2grp {
 415                         fsl,pins = <
 416                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 417                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 418                         >;
 419                 };
 420
 421                 pinctrl_i2c3: i2c3grp {
 422                         fsl,pins = <
 423                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 424                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 425                         >;
 426                 };
 427
 428                 pinctrl_pcie: pciegrp {
 429                         fsl,pins = <
 430                                 MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x1b0b0
 431                         >;
 432                 };
 433
 434                 pinctrl_pcie_reg: pciereggrp {
 435                         fsl,pins = <
 436                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x1b0b0
 437                         >;
 438                 };
 439
 440                 pinctrl_pwm1: pwm1grp {
 441                         fsl,pins = <
 442                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 443                         >;
 444                 };
 445
 446                 pinctrl_uart1: uart1grp {
 447                         fsl,pins = <
 448                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 449                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 450                         >;
 451                 };
 452
 453                 pinctrl_usbotg: usbotggrp {
 454                         fsl,pins = <
 455                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 456                         >;
 457                 };
 458
 459                 pinctrl_usdhc2: usdhc2grp {
 460                         fsl,pins = <
 461                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 462                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 463                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 464                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 465                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 466                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 467                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 468                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 469                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 470                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 471                         >;
 472                 };
 473
 474                 pinctrl_usdhc3: usdhc3grp {
 475                         fsl,pins = <
 476                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 477                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 478                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 479                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 480                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 481                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 482                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 483                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 484                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 485                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 486                         >;
 487                 };
 488
 489                 pinctrl_usdhc4: usdhc4grp {
 490                         fsl,pins = <
 491                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 492                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 493                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 494                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 495                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 496                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 497                                 MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 498                                 MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 499                                 MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 500                                 MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 501                         >;
 502                 };
 503
 504                 pinctrl_wdog: wdoggrp {
 505                         fsl,pins = <
 506                                 MX6QDL_PAD_GPIO_1__WDOG2_B              0x1b0b0
 507                         >;
 508                 };
 509         };
 510
 511         gpio_leds {
 512                 pinctrl_gpio_leds: gpioledsgrp {
 513                         fsl,pins = <
 514                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
 515                         >;
 516                 };
 517         };
 518 };
 519
 520 &ldb {
 521         status = "okay";
 522
 523         lvds-channel@1 {
 524                 fsl,data-mapping = "spwg";
 525                 fsl,data-width = <18>;
 526                 status = "okay";
 527
 528                 port@4 {
 529                         reg = <4>;
 530
 531                         lvds0_out: endpoint {
 532                                 remote-endpoint = <&panel_in>;
 533                         };
 534                 };
 535         };
 536 };
 537
 538 &pcie {
 539         pinctrl-names = "default";
 540         pinctrl-0 = <&pinctrl_pcie>;
 541         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 542         status = "okay";
 543 };
 544
 545 &pwm1 {
 546         pinctrl-names = "default";
 547         pinctrl-0 = <&pinctrl_pwm1>;
 548         status = "okay";
 549 };
 550
 551 &reg_arm {
 552        vin-supply = <&sw1a_reg>;
 553 };
 554
 555 &reg_pu {
 556        vin-supply = <&sw1c_reg>;
 557 };
 558
 559 &reg_soc {
 560        vin-supply = <&sw1c_reg>;
 561 };
 562
 563 &snvs_poweroff {
 564         status = "okay";
 565 };
 566
 567 &ssi2 {
 568         status = "okay";
 569 };
 570
 571 &uart1 {
 572         pinctrl-names = "default";
 573         pinctrl-0 = <&pinctrl_uart1>;
 574         status = "okay";
 575 };
 576
 577 &usbh1 {
 578         vbus-supply = <&reg_usb_h1_vbus>;
 579         status = "okay";
 580 };
 581
 582 &usbotg {
 583         vbus-supply = <&reg_usb_otg_vbus>;
 584         pinctrl-names = "default";
 585         pinctrl-0 = <&pinctrl_usbotg>;
 586         disable-over-current;
 587         status = "okay";
 588 };
 589
 590 &usdhc2 {
 591         pinctrl-names = "default";
 592         pinctrl-0 = <&pinctrl_usdhc2>;
 593         bus-width = <8>;
 594         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 595         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 596         status = "okay";
 597 };
 598
 599 &usdhc3 {
 600         pinctrl-names = "default";
 601         pinctrl-0 = <&pinctrl_usdhc3>;
 602         bus-width = <8>;
 603         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 604         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 605         status = "okay";
 606 };
 607
 608 &usdhc4 {
 609         pinctrl-names = "default";
 610         pinctrl-0 = <&pinctrl_usdhc4>;
 611         bus-width = <8>;
 612         non-removable;
 613         no-1-8-v;
 614         status = "okay";
 615 };
 616
 617 &wdog1 {
 618         status = "disabled";
 619 };
 620
 621 &wdog2 {
 622         pinctrl-names = "default";
 623         pinctrl-0 = <&pinctrl_wdog>;
 624         fsl,ext-reset-output;
 625         status = "okay";
 626 };