arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2012 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 #include <dt-bindings/clock/imx6qdl-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9
  10 / {
  11         chosen {
  12                 stdout-path = &uart1;
  13         };
  14
  15         memory@10000000 {
  16                 device_type = "memory";
  17                 reg = <0x10000000 0x40000000>;
  18         };
  19
  20         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  21                 compatible = "regulator-fixed";
  22                 regulator-name = "usb_otg_vbus";
  23                 regulator-min-microvolt = <5000000>;
  24                 regulator-max-microvolt = <5000000>;
  25                 gpio = <&gpio3 22 0>;
  26                 enable-active-high;
  27                 vin-supply = <&swbst_reg>;
  28         };
  29
  30         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "usb_h1_vbus";
  33                 regulator-min-microvolt = <5000000>;
  34                 regulator-max-microvolt = <5000000>;
  35                 gpio = <&gpio1 29 0>;
  36                 enable-active-high;
  37                 vin-supply = <&swbst_reg>;
  38         };
  39
  40         reg_audio: regulator-audio {
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "wm8962-supply";
  43                 gpio = <&gpio4 10 0>;
  44                 enable-active-high;
  45         };
  46
  47         reg_pcie: regulator-pcie {
  48                 compatible = "regulator-fixed";
  49                 pinctrl-names = "default";
  50                 pinctrl-0 = <&pinctrl_pcie_reg>;
  51                 regulator-name = "MPCIE_3V3";
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54                 gpio = <&gpio3 19 0>;
  55                 enable-active-high;
  56         };
  57
  58         reg_sensors: regulator-sensors {
  59                 compatible = "regulator-fixed";
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pinctrl_sensors_reg>;
  62                 regulator-name = "sensors-supply";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65                 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
  66                 enable-active-high;
  67                 regulator-always-on;
  68         };
  69
  70         gpio-keys {
  71                 compatible = "gpio-keys";
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&pinctrl_gpio_keys>;
  74
  75                 power {
  76                         label = "Power Button";
  77                         gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
  78                         wakeup-source;
  79                         linux,code = <KEY_POWER>;
  80                 };
  81
  82                 volume-up {
  83                         label = "Volume Up";
  84                         gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  85                         wakeup-source;
  86                         linux,code = <KEY_VOLUMEUP>;
  87                 };
  88
  89                 volume-down {
  90                         label = "Volume Down";
  91                         gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  92                         wakeup-source;
  93                         linux,code = <KEY_VOLUMEDOWN>;
  94                 };
  95         };
  96
  97         sound {
  98                 compatible = "fsl,imx6q-sabresd-wm8962",
  99                            "fsl,imx-audio-wm8962";
 100                 model = "wm8962-audio";
 101                 ssi-controller = <&ssi2>;
 102                 audio-codec = <&codec>;
 103                 audio-routing =
 104                         "Headphone Jack", "HPOUTL",
 105                         "Headphone Jack", "HPOUTR",
 106                         "Ext Spk", "SPKOUTL",
 107                         "Ext Spk", "SPKOUTR",
 108                         "AMIC", "MICBIAS",
 109                         "IN3R", "AMIC";
 110                 mux-int-port = <2>;
 111                 mux-ext-port = <3>;
 112         };
 113
 114         backlight_lvds: backlight-lvds {
 115                 compatible = "pwm-backlight";
 116                 pwms = <&pwm1 0 5000000>;
 117                 brightness-levels = <0 4 8 16 32 64 128 255>;
 118                 default-brightness-level = <7>;
 119                 status = "okay";
 120         };
 121
 122         leds {
 123                 compatible = "gpio-leds";
 124                 pinctrl-names = "default";
 125                 pinctrl-0 = <&pinctrl_gpio_leds>;
 126
 127                 red {
 128                         gpios = <&gpio1 2 0>;
 129                         default-state = "on";
 130                 };
 131         };
 132
 133         panel {
 134                 compatible = "hannstar,hsd100pxn1";
 135                 backlight = <&backlight_lvds>;
 136
 137                 port {
 138                         panel_in: endpoint {
 139                                 remote-endpoint = <&lvds0_out>;
 140                         };
 141                 };
 142         };
 143 };
 144
 145 &ipu1_csi0_from_ipu1_csi0_mux {
 146         bus-width = <8>;
 147         data-shift = <12>; /* Lines 19:12 used */
 148         hsync-active = <1>;
 149         vsync-active = <1>;
 150 };
 151
 152 &ipu1_csi0_mux_from_parallel_sensor {
 153         remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
 154 };
 155
 156 &ipu1_csi0 {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 159 };
 160
 161 &mipi_csi {
 162         status = "okay";
 163
 164         port@0 {
 165                 reg = <0>;
 166
 167                 mipi_csi2_in: endpoint {
 168                         remote-endpoint = <&ov5640_to_mipi_csi2>;
 169                         clock-lanes = <0>;
 170                         data-lanes = <1 2>;
 171                 };
 172         };
 173 };
 174
 175 &audmux {
 176         pinctrl-names = "default";
 177         pinctrl-0 = <&pinctrl_audmux>;
 178         status = "okay";
 179 };
 180
 181 &clks {
 182         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 183                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 184         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 185                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 186 };
 187
 188 &ecspi1 {
 189         cs-gpios = <&gpio4 9 0>;
 190         pinctrl-names = "default";
 191         pinctrl-0 = <&pinctrl_ecspi1>;
 192         status = "okay";
 193
 194         flash: m25p80@0 {
 195                 #address-cells = <1>;
 196                 #size-cells = <1>;
 197                 compatible = "st,m25p32", "jedec,spi-nor";
 198                 spi-max-frequency = <20000000>;
 199                 reg = <0>;
 200         };
 201 };
 202
 203 &fec {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_enet>;
 206         phy-mode = "rgmii";
 207         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 208         status = "okay";
 209 };
 210
 211 &hdmi {
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&pinctrl_hdmi_cec>;
 214         ddc-i2c-bus = <&i2c2>;
 215         status = "okay";
 216 };
 217
 218 &i2c1 {
 219         clock-frequency = <100000>;
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pinctrl_i2c1>;
 222         status = "okay";
 223
 224         codec: wm8962@1a {
 225                 compatible = "wlf,wm8962";
 226                 reg = <0x1a>;
 227                 clocks = <&clks IMX6QDL_CLK_CKO>;
 228                 DCVDD-supply = <&reg_audio>;
 229                 DBVDD-supply = <&reg_audio>;
 230                 AVDD-supply = <&reg_audio>;
 231                 CPVDD-supply = <&reg_audio>;
 232                 MICVDD-supply = <&reg_audio>;
 233                 PLLVDD-supply = <&reg_audio>;
 234                 SPKVDD1-supply = <&reg_audio>;
 235                 SPKVDD2-supply = <&reg_audio>;
 236                 gpio-cfg = <
 237                         0x0000 /* 0:Default */
 238                         0x0000 /* 1:Default */
 239                         0x0013 /* 2:FN_DMICCLK */
 240                         0x0000 /* 3:Default */
 241                         0x8014 /* 4:FN_DMICCDAT */
 242                         0x0000 /* 5:Default */
 243                 >;
 244         };
 245
 246         ov5642: camera@3c {
 247                 compatible = "ovti,ov5642";
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&pinctrl_ov5642>;
 250                 clocks = <&clks IMX6QDL_CLK_CKO>;
 251                 clock-names = "xclk";
 252                 reg = <0x3c>;
 253                 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
 254                 AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
 255                                                 rev B board is VGEN5 */
 256                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 257                 powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
 258                 reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
 259                 status = "disabled";
 260
 261                 port {
 262                         ov5642_to_ipu1_csi0_mux: endpoint {
 263                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 264                                 bus-width = <8>;
 265                                 hsync-active = <1>;
 266                                 vsync-active = <1>;
 267                         };
 268                 };
 269         };
 270 };
 271
 272 &i2c2 {
 273         clock-frequency = <100000>;
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_i2c2>;
 276         status = "okay";
 277
 278         touchscreen@4 {
 279                 compatible = "eeti,egalax_ts";
 280                 reg = <0x04>;
 281                 pinctrl-names = "default";
 282                 pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
 283                 interrupt-parent = <&gpio6>;
 284                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 285                 wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
 286         };
 287
 288         ov5640: camera@3c {
 289                 compatible = "ovti,ov5640";
 290                 pinctrl-names = "default";
 291                 pinctrl-0 = <&pinctrl_ov5640>;
 292                 reg = <0x3c>;
 293                 clocks = <&clks IMX6QDL_CLK_CKO>;
 294                 clock-names = "xclk";
 295                 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
 296                 AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
 297                                                 rev B board is VGEN5 */
 298                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 299                 powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
 300                 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
 301
 302                 port {
 303                         ov5640_to_mipi_csi2: endpoint {
 304                                 remote-endpoint = <&mipi_csi2_in>;
 305                                 clock-lanes = <0>;
 306                                 data-lanes = <1 2>;
 307                         };
 308                 };
 309         };
 310
 311         pmic: pfuze100@8 {
 312                 compatible = "fsl,pfuze100";
 313                 reg = <0x08>;
 314
 315                 regulators {
 316                         sw1a_reg: sw1ab {
 317                                 regulator-min-microvolt = <300000>;
 318                                 regulator-max-microvolt = <1875000>;
 319                                 regulator-boot-on;
 320                                 regulator-always-on;
 321                                 regulator-ramp-delay = <6250>;
 322                         };
 323
 324                         sw1c_reg: sw1c {
 325                                 regulator-min-microvolt = <300000>;
 326                                 regulator-max-microvolt = <1875000>;
 327                                 regulator-boot-on;
 328                                 regulator-always-on;
 329                                 regulator-ramp-delay = <6250>;
 330                         };
 331
 332                         sw2_reg: sw2 {
 333                                 regulator-min-microvolt = <800000>;
 334                                 regulator-max-microvolt = <3300000>;
 335                                 regulator-boot-on;
 336                                 regulator-always-on;
 337                                 regulator-ramp-delay = <6250>;
 338                         };
 339
 340                         sw3a_reg: sw3a {
 341                                 regulator-min-microvolt = <400000>;
 342                                 regulator-max-microvolt = <1975000>;
 343                                 regulator-boot-on;
 344                                 regulator-always-on;
 345                         };
 346
 347                         sw3b_reg: sw3b {
 348                                 regulator-min-microvolt = <400000>;
 349                                 regulator-max-microvolt = <1975000>;
 350                                 regulator-boot-on;
 351                                 regulator-always-on;
 352                         };
 353
 354                         sw4_reg: sw4 {
 355                                 regulator-min-microvolt = <800000>;
 356                                 regulator-max-microvolt = <3300000>;
 357                                 regulator-always-on;
 358                         };
 359
 360                         swbst_reg: swbst {
 361                                 regulator-min-microvolt = <5000000>;
 362                                 regulator-max-microvolt = <5150000>;
 363                         };
 364
 365                         snvs_reg: vsnvs {
 366                                 regulator-min-microvolt = <1000000>;
 367                                 regulator-max-microvolt = <3000000>;
 368                                 regulator-boot-on;
 369                                 regulator-always-on;
 370                         };
 371
 372                         vref_reg: vrefddr {
 373                                 regulator-boot-on;
 374                                 regulator-always-on;
 375                         };
 376
 377                         vgen1_reg: vgen1 {
 378                                 regulator-min-microvolt = <800000>;
 379                                 regulator-max-microvolt = <1550000>;
 380                         };
 381
 382                         vgen2_reg: vgen2 {
 383                                 regulator-min-microvolt = <800000>;
 384                                 regulator-max-microvolt = <1550000>;
 385                         };
 386
 387                         vgen3_reg: vgen3 {
 388                                 regulator-min-microvolt = <1800000>;
 389                                 regulator-max-microvolt = <3300000>;
 390                         };
 391
 392                         vgen4_reg: vgen4 {
 393                                 regulator-min-microvolt = <1800000>;
 394                                 regulator-max-microvolt = <3300000>;
 395                                 regulator-always-on;
 396                         };
 397
 398                         vgen5_reg: vgen5 {
 399                                 regulator-min-microvolt = <1800000>;
 400                                 regulator-max-microvolt = <3300000>;
 401                                 regulator-always-on;
 402                         };
 403
 404                         vgen6_reg: vgen6 {
 405                                 regulator-min-microvolt = <1800000>;
 406                                 regulator-max-microvolt = <3300000>;
 407                                 regulator-always-on;
 408                         };
 409                 };
 410         };
 411 };
 412
 413 &i2c3 {
 414         clock-frequency = <100000>;
 415         pinctrl-names = "default";
 416         pinctrl-0 = <&pinctrl_i2c3>;
 417         status = "okay";
 418
 419         egalax_ts@4 {
 420                 compatible = "eeti,egalax_ts";
 421                 reg = <0x04>;
 422                 interrupt-parent = <&gpio6>;
 423                 interrupts = <7 2>;
 424                 wakeup-gpios = <&gpio6 7 0>;
 425         };
 426
 427         magnetometer@e {
 428                 compatible = "fsl,mag3110";
 429                 reg = <0x0e>;
 430                 pinctrl-names = "default";
 431                 pinctrl-0 = <&pinctrl_i2c3_mag3110_int>;
 432                 interrupt-parent = <&gpio3>;
 433                 interrupts = <16 IRQ_TYPE_EDGE_RISING>;
 434         };
 435
 436         light-sensor@44 {
 437                 compatible = "isil,isl29023";
 438                 reg = <0x44>;
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&pinctrl_i2c3_isl29023_int>;
 441                 interrupt-parent = <&gpio3>;
 442                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
 443         };
 444 };
 445
 446 &iomuxc {
 447         pinctrl-names = "default";
 448         pinctrl-0 = <&pinctrl_hog>;
 449
 450         imx6qdl-sabresd {
 451                 pinctrl_hog: hoggrp {
 452                         fsl,pins = <
 453                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
 454                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
 455                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
 456                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
 457                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 458                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
 459                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
 460                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
 461                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
 462                         >;
 463                 };
 464
 465                 pinctrl_audmux: audmuxgrp {
 466                         fsl,pins = <
 467                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 468                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 469                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 470                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 471                         >;
 472                 };
 473
 474                 pinctrl_ecspi1: ecspi1grp {
 475                         fsl,pins = <
 476                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 477                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 478                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 479                                 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x1b0b0
 480                         >;
 481                 };
 482
 483                 pinctrl_enet: enetgrp {
 484                         fsl,pins = <
 485                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 486                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 487                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 488                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 489                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 490                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 491                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 492                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 493                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 494                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 495                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 496                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 497                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 498                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 499                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 500                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 501                         >;
 502                 };
 503
 504                 pinctrl_gpio_keys: gpio_keysgrp {
 505                         fsl,pins = <
 506                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
 507                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
 508                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
 509                         >;
 510                 };
 511
 512                 pinctrl_hdmi_cec: hdmicecgrp {
 513                         fsl,pins = <
 514                                 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE   0x1f8b0
 515                         >;
 516                 };
 517
 518                 pinctrl_i2c1: i2c1grp {
 519                         fsl,pins = <
 520                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 521                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 522                         >;
 523                 };
 524
 525                 pinctrl_i2c2: i2c2grp {
 526                         fsl,pins = <
 527                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 528                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 529                         >;
 530                 };
 531
 532                 pinctrl_i2c2_egalax_int: i2c2egalaxintgrp {
 533                         fsl,pins = <
 534                                 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x1b0b0
 535                         >;
 536                 };
 537
 538                 pinctrl_i2c3: i2c3grp {
 539                         fsl,pins = <
 540                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 541                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 542                         >;
 543                 };
 544
 545                 pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp {
 546                         fsl,pins = <
 547                                 MX6QDL_PAD_EIM_DA9__GPIO3_IO09          0xb0b1
 548                         >;
 549                 };
 550
 551                 pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp {
 552                         fsl,pins = <
 553                                 MX6QDL_PAD_EIM_D16__GPIO3_IO16          0xb0b1
 554                         >;
 555                 };
 556
 557                 pinctrl_ipu1_csi0: ipu1csi0grp {
 558                         fsl,pins = <
 559                                 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
 560                                 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
 561                                 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
 562                                 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
 563                                 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
 564                                 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
 565                                 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
 566                                 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
 567                                 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
 568                                 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
 569                                 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
 570                         >;
 571                 };
 572
 573                 pinctrl_ov5640: ov5640grp {
 574                         fsl,pins = <
 575                                 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
 576                                 MX6QDL_PAD_SD1_CLK__GPIO1_IO20  0x1b0b0
 577                         >;
 578                 };
 579
 580                 pinctrl_ov5642: ov5642grp {
 581                         fsl,pins = <
 582                                 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
 583                                 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
 584                         >;
 585                 };
 586
 587                 pinctrl_pcie: pciegrp {
 588                         fsl,pins = <
 589                                 MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x1b0b0
 590                         >;
 591                 };
 592
 593                 pinctrl_pcie_reg: pciereggrp {
 594                         fsl,pins = <
 595                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x1b0b0
 596                         >;
 597                 };
 598
 599                 pinctrl_pwm1: pwm1grp {
 600                         fsl,pins = <
 601                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 602                         >;
 603                 };
 604
 605                 pinctrl_sensors_reg: sensorsreggrp {
 606                         fsl,pins = <
 607                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b0
 608                         >;
 609                 };
 610
 611                 pinctrl_uart1: uart1grp {
 612                         fsl,pins = <
 613                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 614                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 615                         >;
 616                 };
 617
 618                 pinctrl_usbotg: usbotggrp {
 619                         fsl,pins = <
 620                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 621                         >;
 622                 };
 623
 624                 pinctrl_usdhc2: usdhc2grp {
 625                         fsl,pins = <
 626                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 627                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 628                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 629                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 630                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 631                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 632                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 633                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 634                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 635                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 636                         >;
 637                 };
 638
 639                 pinctrl_usdhc3: usdhc3grp {
 640                         fsl,pins = <
 641                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 642                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 643                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 644                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 645                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 646                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 647                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 648                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 649                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 650                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 651                         >;
 652                 };
 653
 654                 pinctrl_usdhc4: usdhc4grp {
 655                         fsl,pins = <
 656                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 657                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 658                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 659                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 660                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 661                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 662                                 MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 663                                 MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 664                                 MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 665                                 MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 666                         >;
 667                 };
 668
 669                 pinctrl_wdog: wdoggrp {
 670                         fsl,pins = <
 671                                 MX6QDL_PAD_GPIO_1__WDOG2_B              0x1b0b0
 672                         >;
 673                 };
 674         };
 675
 676         gpio_leds {
 677                 pinctrl_gpio_leds: gpioledsgrp {
 678                         fsl,pins = <
 679                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
 680                         >;
 681                 };
 682         };
 683 };
 684
 685 &ldb {
 686         status = "okay";
 687
 688         lvds-channel@1 {
 689                 fsl,data-mapping = "spwg";
 690                 fsl,data-width = <18>;
 691                 status = "okay";
 692
 693                 port@4 {
 694                         reg = <4>;
 695
 696                         lvds0_out: endpoint {
 697                                 remote-endpoint = <&panel_in>;
 698                         };
 699                 };
 700         };
 701 };
 702
 703 &pcie {
 704         pinctrl-names = "default";
 705         pinctrl-0 = <&pinctrl_pcie>;
 706         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 707         vpcie-supply = <&reg_pcie>;
 708         status = "okay";
 709 };
 710
 711 &pwm1 {
 712         pinctrl-names = "default";
 713         pinctrl-0 = <&pinctrl_pwm1>;
 714         status = "okay";
 715 };
 716
 717 &reg_arm {
 718        vin-supply = <&sw1a_reg>;
 719 };
 720
 721 &reg_pu {
 722        vin-supply = <&sw1c_reg>;
 723 };
 724
 725 &reg_soc {
 726        vin-supply = <&sw1c_reg>;
 727 };
 728
 729 &snvs_poweroff {
 730         status = "okay";
 731 };
 732
 733 &ssi2 {
 734         status = "okay";
 735 };
 736
 737 &uart1 {
 738         pinctrl-names = "default";
 739         pinctrl-0 = <&pinctrl_uart1>;
 740         status = "okay";
 741 };
 742
 743 &usbh1 {
 744         vbus-supply = <&reg_usb_h1_vbus>;
 745         status = "okay";
 746 };
 747
 748 &usbotg {
 749         vbus-supply = <&reg_usb_otg_vbus>;
 750         pinctrl-names = "default";
 751         pinctrl-0 = <&pinctrl_usbotg>;
 752         disable-over-current;
 753         status = "okay";
 754 };
 755
 756 &usdhc2 {
 757         pinctrl-names = "default";
 758         pinctrl-0 = <&pinctrl_usdhc2>;
 759         bus-width = <8>;
 760         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 761         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 762         status = "okay";
 763 };
 764
 765 &usdhc3 {
 766         pinctrl-names = "default";
 767         pinctrl-0 = <&pinctrl_usdhc3>;
 768         bus-width = <8>;
 769         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 770         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 771         status = "okay";
 772 };
 773
 774 &usdhc4 {
 775         pinctrl-names = "default";
 776         pinctrl-0 = <&pinctrl_usdhc4>;
 777         bus-width = <8>;
 778         non-removable;
 779         no-1-8-v;
 780         status = "okay";
 781 };
 782
 783 &wdog1 {
 784         status = "disabled";
 785 };
 786
 787 &wdog2 {
 788         pinctrl-names = "default";
 789         pinctrl-0 = <&pinctrl_wdog>;
 790         fsl,ext-reset-output;
 791         status = "okay";
 792 };