arch/arm/boot/dts/imx6qdl-sabrelite.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License
  12  *     version 2 as published by the Free Software Foundation.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/imx6qdl-clock.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/input/input.h>
  46
  47 / {
  48         chosen {
  49                 stdout-path = &uart2;
  50         };
  51
  52         memory {
  53                 reg = <0x10000000 0x40000000>;
  54         };
  55
  56         regulators {
  57                 compatible = "simple-bus";
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 reg_2p5v: regulator@0 {
  62                         compatible = "regulator-fixed";
  63                         reg = <0>;
  64                         regulator-name = "2P5V";
  65                         regulator-min-microvolt = <2500000>;
  66                         regulator-max-microvolt = <2500000>;
  67                         regulator-always-on;
  68                 };
  69
  70                 reg_3p3v: regulator@1 {
  71                         compatible = "regulator-fixed";
  72                         reg = <1>;
  73                         regulator-name = "3P3V";
  74                         regulator-min-microvolt = <3300000>;
  75                         regulator-max-microvolt = <3300000>;
  76                         regulator-always-on;
  77                 };
  78
  79                 reg_usb_otg_vbus: regulator@2 {
  80                         compatible = "regulator-fixed";
  81                         reg = <2>;
  82                         regulator-name = "usb_otg_vbus";
  83                         regulator-min-microvolt = <5000000>;
  84                         regulator-max-microvolt = <5000000>;
  85                         gpio = <&gpio3 22 0>;
  86                         enable-active-high;
  87                 };
  88
  89                 reg_can_xcvr: regulator@3 {
  90                         compatible = "regulator-fixed";
  91                         reg = <3>;
  92                         regulator-name = "CAN XCVR";
  93                         regulator-min-microvolt = <3300000>;
  94                         regulator-max-microvolt = <3300000>;
  95                         pinctrl-names = "default";
  96                         pinctrl-0 = <&pinctrl_can_xcvr>;
  97                         gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
  98                 };
  99
 100                 reg_1p5v: regulator@4 {
 101                         compatible = "regulator-fixed";
 102                         reg = <4>;
 103                         regulator-name = "1P5V";
 104                         regulator-min-microvolt = <1500000>;
 105                         regulator-max-microvolt = <1500000>;
 106                         regulator-always-on;
 107                 };
 108
 109                 reg_1p8v: regulator@5 {
 110                         compatible = "regulator-fixed";
 111                         reg = <5>;
 112                         regulator-name = "1P8V";
 113                         regulator-min-microvolt = <1800000>;
 114                         regulator-max-microvolt = <1800000>;
 115                         regulator-always-on;
 116                 };
 117
 118                 reg_2p8v: regulator@6 {
 119                         compatible = "regulator-fixed";
 120                         reg = <6>;
 121                         regulator-name = "2P8V";
 122                         regulator-min-microvolt = <2800000>;
 123                         regulator-max-microvolt = <2800000>;
 124                         regulator-always-on;
 125                 };
 126         };
 127
 128         mipi_xclk: mipi_xclk {
 129                 compatible = "pwm-clock";
 130                 #clock-cells = <0>;
 131                 clock-frequency = <22000000>;
 132                 clock-output-names = "mipi_pwm3";
 133                 pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
 134                 status = "okay";
 135         };
 136
 137         gpio-keys {
 138                 compatible = "gpio-keys";
 139                 pinctrl-names = "default";
 140                 pinctrl-0 = <&pinctrl_gpio_keys>;
 141
 142                 power {
 143                         label = "Power Button";
 144                         gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
 145                         linux,code = <KEY_POWER>;
 146                         wakeup-source;
 147                 };
 148
 149                 menu {
 150                         label = "Menu";
 151                         gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 152                         linux,code = <KEY_MENU>;
 153                 };
 154
 155                 home {
 156                         label = "Home";
 157                         gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 158                         linux,code = <KEY_HOME>;
 159                 };
 160
 161                 back {
 162                         label = "Back";
 163                         gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 164                         linux,code = <KEY_BACK>;
 165                 };
 166
 167                 volume-up {
 168                         label = "Volume Up";
 169                         gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
 170                         linux,code = <KEY_VOLUMEUP>;
 171                 };
 172
 173                 volume-down {
 174                         label = "Volume Down";
 175                         gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
 176                         linux,code = <KEY_VOLUMEDOWN>;
 177                 };
 178         };
 179
 180         sound {
 181                 compatible = "fsl,imx6q-sabrelite-sgtl5000",
 182                              "fsl,imx-audio-sgtl5000";
 183                 model = "imx6q-sabrelite-sgtl5000";
 184                 ssi-controller = <&ssi1>;
 185                 audio-codec = <&codec>;
 186                 audio-routing =
 187                         "MIC_IN", "Mic Jack",
 188                         "Mic Jack", "Mic Bias",
 189                         "Headphone Jack", "HP_OUT";
 190                 mux-int-port = <1>;
 191                 mux-ext-port = <4>;
 192         };
 193
 194         backlight_lcd: backlight-lcd {
 195                 compatible = "pwm-backlight";
 196                 pwms = <&pwm1 0 5000000>;
 197                 brightness-levels = <0 4 8 16 32 64 128 255>;
 198                 default-brightness-level = <7>;
 199                 power-supply = <&reg_3p3v>;
 200                 status = "okay";
 201         };
 202
 203         backlight_lvds: backlight-lvds {
 204                 compatible = "pwm-backlight";
 205                 pwms = <&pwm4 0 5000000>;
 206                 brightness-levels = <0 4 8 16 32 64 128 255>;
 207                 default-brightness-level = <7>;
 208                 power-supply = <&reg_3p3v>;
 209                 status = "okay";
 210         };
 211
 212         lcd_display: display@di0 {
 213                 compatible = "fsl,imx-parallel-display";
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216                 interface-pix-fmt = "bgr666";
 217                 pinctrl-names = "default";
 218                 pinctrl-0 = <&pinctrl_j15>;
 219                 status = "okay";
 220
 221                 port@0 {
 222                         reg = <0>;
 223
 224                         lcd_display_in: endpoint {
 225                                 remote-endpoint = <&ipu1_di0_disp0>;
 226                         };
 227                 };
 228
 229                 port@1 {
 230                         reg = <1>;
 231
 232                         lcd_display_out: endpoint {
 233                                 remote-endpoint = <&lcd_panel_in>;
 234                         };
 235                 };
 236         };
 237
 238         panel-lcd {
 239                 compatible = "okaya,rs800480t-7x0gp";
 240                 backlight = <&backlight_lcd>;
 241
 242                 port {
 243                         lcd_panel_in: endpoint {
 244                                 remote-endpoint = <&lcd_display_out>;
 245                         };
 246                 };
 247         };
 248
 249         panel-lvds0 {
 250                 compatible = "hannstar,hsd100pxn1";
 251                 backlight = <&backlight_lvds>;
 252
 253                 port {
 254                         panel_in: endpoint {
 255                                 remote-endpoint = <&lvds0_out>;
 256                         };
 257                 };
 258         };
 259 };
 260
 261 &ipu1_csi0_from_ipu1_csi0_mux {
 262         bus-width = <8>;
 263         data-shift = <12>; /* Lines 19:12 used */
 264         hsync-active = <1>;
 265         vync-active = <1>;
 266 };
 267
 268 &ipu1_csi0_mux_from_parallel_sensor {
 269         remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
 270 };
 271
 272 &ipu1_csi0 {
 273         pinctrl-names = "default";
 274         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 275 };
 276
 277 &audmux {
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_audmux>;
 280         status = "okay";
 281 };
 282
 283 &can1 {
 284         pinctrl-names = "default";
 285         pinctrl-0 = <&pinctrl_can1>;
 286         xceiver-supply = <&reg_can_xcvr>;
 287         status = "okay";
 288 };
 289
 290 &clks {
 291         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 292                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 293         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 294                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 295 };
 296
 297 &ecspi1 {
 298         cs-gpios = <&gpio3 19 0>;
 299         pinctrl-names = "default";
 300         pinctrl-0 = <&pinctrl_ecspi1>;
 301         status = "okay";
 302
 303         flash: m25p80@0 {
 304                 compatible = "sst,sst25vf016b", "jedec,spi-nor";
 305                 spi-max-frequency = <20000000>;
 306                 reg = <0>;
 307         };
 308 };
 309
 310 &fec {
 311         pinctrl-names = "default";
 312         pinctrl-0 = <&pinctrl_enet>;
 313         phy-mode = "rgmii";
 314         phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 315         txen-skew-ps = <0>;
 316         txc-skew-ps = <3000>;
 317         rxdv-skew-ps = <0>;
 318         rxc-skew-ps = <3000>;
 319         rxd0-skew-ps = <0>;
 320         rxd1-skew-ps = <0>;
 321         rxd2-skew-ps = <0>;
 322         rxd3-skew-ps = <0>;
 323         txd0-skew-ps = <0>;
 324         txd1-skew-ps = <0>;
 325         txd2-skew-ps = <0>;
 326         txd3-skew-ps = <0>;
 327         status = "okay";
 328 };
 329
 330 &hdmi {
 331         ddc-i2c-bus = <&i2c2>;
 332         status = "okay";
 333 };
 334
 335 &i2c1 {
 336         clock-frequency = <100000>;
 337         pinctrl-names = "default";
 338         pinctrl-0 = <&pinctrl_i2c1>;
 339         status = "okay";
 340
 341         codec: sgtl5000@0a {
 342                 compatible = "fsl,sgtl5000";
 343                 reg = <0x0a>;
 344                 clocks = <&clks IMX6QDL_CLK_CKO>;
 345                 VDDA-supply = <&reg_2p5v>;
 346                 VDDIO-supply = <&reg_3p3v>;
 347         };
 348 };
 349
 350 &i2c2 {
 351         clock-frequency = <100000>;
 352         pinctrl-names = "default";
 353         pinctrl-0 = <&pinctrl_i2c2>;
 354         status = "okay";
 355
 356         ov5640: camera@40 {
 357                 compatible = "ovti,ov5640";
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&pinctrl_ov5640>;
 360                 reg = <0x40>;
 361                 clocks = <&mipi_xclk>;
 362                 clock-names = "xclk";
 363                 DOVDD-supply = <&reg_1p8v>;
 364                 AVDD-supply = <&reg_2p8v>;
 365                 DVDD-supply = <&reg_1p5v>;
 366                 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
 367                 powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
 368
 369                 port {
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372
 373                         ov5640_to_mipi_csi2: endpoint {
 374                                 remote-endpoint = <&mipi_csi2_in>;
 375                                 clock-lanes = <0>;
 376                                 data-lanes = <1 2>;
 377                         };
 378                 };
 379         };
 380
 381         ov5642: camera@42 {
 382                 compatible = "ovti,ov5642";
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&pinctrl_ov5642>;
 385                 clocks = <&clks IMX6QDL_CLK_CKO2>;
 386                 clock-names = "xclk";
 387                 reg = <0x42>;
 388                 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
 389                 powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
 390                 gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
 391                 status = "disabled";
 392
 393                 port {
 394                         ov5642_to_ipu1_csi0_mux: endpoint {
 395                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 396                                 bus-width = <8>;
 397                                 hsync-active = <1>;
 398                                 vsync-active = <1>;
 399                         };
 400                 };
 401         };
 402 };
 403
 404 &i2c3 {
 405         clock-frequency = <100000>;
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&pinctrl_i2c3>;
 408         status = "okay";
 409 };
 410
 411 &iomuxc {
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_hog>;
 414
 415         imx6q-sabrelite {
 416                 pinctrl_hog: hoggrp {
 417                         fsl,pins = <
 418                                 /* SGTL5000 sys_mclk */
 419                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x030b0
 420                         >;
 421                 };
 422
 423                 pinctrl_audmux: audmuxgrp {
 424                         fsl,pins = <
 425                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 426                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 427                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 428                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 429                         >;
 430                 };
 431
 432                 pinctrl_can1: can1grp {
 433                         fsl,pins = <
 434                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
 435                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
 436                         >;
 437                 };
 438
 439                 pinctrl_can_xcvr: can-xcvrgrp {
 440                         fsl,pins = <
 441                                 /* Flexcan XCVR enable */
 442                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 443                         >;
 444                 };
 445
 446                 pinctrl_ecspi1: ecspi1grp {
 447                         fsl,pins = <
 448                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 449                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 450                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 451                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x000b1 /* CS */
 452                         >;
 453                 };
 454
 455                 pinctrl_enet: enetgrp {
 456                         fsl,pins = <
 457                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 458                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 459                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x10030
 460                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x10030
 461                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x10030
 462                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x10030
 463                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x10030
 464                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x10030
 465                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 466                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 467                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 468                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 469                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 470                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 471                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 472                                 /* Phy reset */
 473                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x000b0
 474                         >;
 475                 };
 476
 477                 pinctrl_gpio_keys: gpio-keysgrp {
 478                         fsl,pins = <
 479                                 /* Power Button */
 480                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x1b0b0
 481                                 /* Menu Button */
 482                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 483                                 /* Home Button */
 484                                 MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x1b0b0
 485                                 /* Back Button */
 486                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x1b0b0
 487                                 /* Volume Up Button */
 488                                 MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b0
 489                                 /* Volume Down Button */
 490                                 MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
 491                         >;
 492                 };
 493
 494                 pinctrl_i2c1: i2c1grp {
 495                         fsl,pins = <
 496                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 497                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 498                         >;
 499                 };
 500
 501                 pinctrl_i2c2: i2c2grp {
 502                         fsl,pins = <
 503                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 504                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 505                         >;
 506                 };
 507
 508                 pinctrl_i2c3: i2c3grp {
 509                         fsl,pins = <
 510                                 MX6QDL_PAD_GPIO_5__I2C3_SCL             0x4001b8b1
 511                                 MX6QDL_PAD_GPIO_16__I2C3_SDA            0x4001b8b1
 512                         >;
 513                 };
 514
 515                 pinctrl_ipu1_csi0: ipu1csi0grp {
 516                         fsl,pins = <
 517                                 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
 518                                 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
 519                                 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
 520                                 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
 521                                 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
 522                                 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
 523                                 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
 524                                 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
 525                                 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
 526                                 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
 527                                 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
 528                                 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
 529                         >;
 530                 };
 531
 532                 pinctrl_j15: j15grp {
 533                         fsl,pins = <
 534                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 535                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 536                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 537                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 538                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 539                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 540                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 541                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 542                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 543                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 544                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 545                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 546                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 547                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 548                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 549                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 550                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 551                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 552                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 553                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 554                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 555                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 556                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 557                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 558                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 559                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 560                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 561                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 562                         >;
 563                 };
 564
 565                 pinctrl_ov5640: ov5640grp {
 566                         fsl,pins = <
 567                                 MX6QDL_PAD_NANDF_D5__GPIO2_IO05   0x000b0
 568                                 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
 569                         >;
 570                 };
 571
 572                 pinctrl_ov5642: ov5642grp {
 573                         fsl,pins = <
 574                                 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
 575                                 MX6QDL_PAD_GPIO_6__GPIO1_IO06   0x1b0b0
 576                                 MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x130b0
 577                                 MX6QDL_PAD_GPIO_3__CCM_CLKO2    0x000b0
 578                         >;
 579                 };
 580
 581                 pinctrl_pwm1: pwm1grp {
 582                         fsl,pins = <
 583                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
 584                         >;
 585                 };
 586
 587                 pinctrl_pwm3: pwm3grp {
 588                         fsl,pins = <
 589                                 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
 590                         >;
 591                 };
 592
 593                 pinctrl_pwm4: pwm4grp {
 594                         fsl,pins = <
 595                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
 596                         >;
 597                 };
 598
 599                 pinctrl_uart1: uart1grp {
 600                         fsl,pins = <
 601                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 602                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 603                         >;
 604                 };
 605
 606                 pinctrl_uart2: uart2grp {
 607                         fsl,pins = <
 608                                 MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
 609                                 MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
 610                         >;
 611                 };
 612
 613                 pinctrl_usbotg: usbotggrp {
 614                         fsl,pins = <
 615                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 616                                 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
 617                                 /* power enable, high active */
 618                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x000b0
 619                         >;
 620                 };
 621
 622                 pinctrl_usdhc3: usdhc3grp {
 623                         fsl,pins = <
 624                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 625                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 626                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 627                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 628                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 629                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 630                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
 631                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
 632                         >;
 633                 };
 634
 635                 pinctrl_usdhc4: usdhc4grp {
 636                         fsl,pins = <
 637                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 638                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 639                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 640                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 641                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 642                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 643                                 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
 644                         >;
 645                 };
 646         };
 647 };
 648
 649 &ipu1_di0_disp0 {
 650         remote-endpoint = <&lcd_display_in>;
 651 };
 652
 653 &ldb {
 654         status = "okay";
 655
 656         lvds-channel@0 {
 657                 status = "okay";
 658
 659                 port@4 {
 660                         reg = <4>;
 661
 662                         lvds0_out: endpoint {
 663                                 remote-endpoint = <&panel_in>;
 664                         };
 665                 };
 666         };
 667 };
 668
 669 &pcie {
 670         status = "okay";
 671 };
 672
 673 &pwm1 {
 674         pinctrl-names = "default";
 675         pinctrl-0 = <&pinctrl_pwm1>;
 676         status = "okay";
 677 };
 678
 679 &pwm3 {
 680         pinctrl-names = "default";
 681         pinctrl-0 = <&pinctrl_pwm3>;
 682         status = "okay";
 683 };
 684
 685 &pwm4 {
 686         pinctrl-names = "default";
 687         pinctrl-0 = <&pinctrl_pwm4>;
 688         status = "okay";
 689 };
 690
 691 &ssi1 {
 692         status = "okay";
 693 };
 694
 695 &uart1 {
 696         pinctrl-names = "default";
 697         pinctrl-0 = <&pinctrl_uart1>;
 698         status = "okay";
 699 };
 700
 701 &uart2 {
 702         pinctrl-names = "default";
 703         pinctrl-0 = <&pinctrl_uart2>;
 704         status = "okay";
 705 };
 706
 707 &usbh1 {
 708         status = "okay";
 709 };
 710
 711 &usbotg {
 712         vbus-supply = <&reg_usb_otg_vbus>;
 713         pinctrl-names = "default";
 714         pinctrl-0 = <&pinctrl_usbotg>;
 715         disable-over-current;
 716         status = "okay";
 717 };
 718
 719 &usdhc3 {
 720         pinctrl-names = "default";
 721         pinctrl-0 = <&pinctrl_usdhc3>;
 722         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 723         wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 724         vmmc-supply = <&reg_3p3v>;
 725         status = "okay";
 726 };
 727
 728 &usdhc4 {
 729         pinctrl-names = "default";
 730         pinctrl-0 = <&pinctrl_usdhc4>;
 731         cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
 732         vmmc-supply = <&reg_3p3v>;
 733         status = "okay";
 734 };
 735
 736 &mipi_csi {
 737         status = "okay";
 738
 739         port@0 {
 740                 reg = <0>;
 741
 742                 mipi_csi2_in: endpoint {
 743                         remote-endpoint = <&ov5640_to_mipi_csi2>;
 744                         clock-lanes = <0>;
 745                         data-lanes = <1 2>;
 746                 };
 747         };
 748 };